JP3516296B2 - Semiconductor integrated circuit and semiconductor integrated circuit device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, a circuit configuration method using pass transistor logic has been proposed as a technology that enables low power consumption, high speed, and small chip area ("Technical White Paper on Low-Power LSI", Nikkei BP Mori; p98-104).

Hitachi's CPL (Complementar)
In y Pass-Transistor Logic, a CMOS inverter is attached to the output to restore the dulled high-level logic level to the original level and enhance the driving force of the latter-stage load. At this time, a circuit configuration method is adopted in which a PMOS cross latch is attached to suppress the static current of the inverter (K. Yano, T. Yamanak).
a. Nishida, M .; Saito, K .; Shi
mohashi, and A. Shimizu, "A
3.8ns CMOS 16x16-b Multiply
r Using Complementary Pass
-Transistor Logic, "IEEE
J. Solid-State Circuits. , V
ol. 25, No. 2, pp. 388-395, (19
90). ).

Toshiba's SRPL (Swing Resto)
red Pass-Transistor Logi
In c), a circuit configuration method using a CMOS latch to guarantee the output is proposed (A. Parameswar, H. et al.
Hara and T. Sakurai, "A High
Speed, Low Power, Swing Re
Stored Pass-Transistor Lo
gic Based Multiply and Ac
-Cumulate Circuit for Milt
immedia Applications, "Pro
c. IEEE 1994 CICC, pp. 278-2
81, May 1994. ).

Further, in these pass transistor logic circuits, a circuit structure is adopted in which a CMOS buffer is inserted into a continuous transistor connection for every fixed number of stages to recover a signal delay.

By adopting the circuit configuration as described above, the rise / fall of the signal is made steep, and the increase of the through current and the increase of the delay time due to the waveform rounding are eliminated,
Differentiating from CMOS is realized from the viewpoint of low power consumption and high speed.

As another method for increasing the circuit speed, CMOS is used regardless of the pass transistor logic circuit.
Methods have been proposed to improve circuit speed by using low threshold transistors in the circuit.

However, while a low-threshold transistor can achieve higher speed, it generally has a large leak current when it is off, so a circuit configuration combined with this leak current reduction method is proposed.

MTCMOS (S. Mutoh, et al.
l. 1V high-speed digital ci
rcuit technology with 0.5
μm multi-threshold. CMOS. I
n Proceedings of the IEEE
ASIC Conference, pp. 186-1
89.1993. ) Adopts a configuration in which a logic gate is composed of a low-threshold transistor and is connected to a pseudo power supply line. The pseudo power supply line is a high threshold transistor for sleep control and is directly connected to the power supply line. Since the pseudo power supply line operates as a power supply line during operation, low-voltage high-speed operation is possible with a low-threshold transistor. During standby, a high threshold transistor cuts off the pseudo power supply line and the power supply line to reduce the leakage current.

VT-CMOS (Tadahiro Kuroda, Kenji Matsuo, Takayasu Sakurai. Cut the current consumption by one digit at maximum by changing the threshold voltage.-Providing guidelines for optimum design.-Nikkei Microdevice, pp.57-66, In August 1996.), by controlling the substrate voltage that was conventionally fixed to the power supply, the threshold of the transistor was lowered during operation to perform low-voltage high-speed operation, and the threshold was increased during standby to reduce leakage current. There is.

[0011]

When considering application of a low-threshold transistor in order to speed up the circuit, there is a potential problem of off-leakage current of the transistor.

Each time the threshold value is lowered by 0.1 V, the leak current of the transistor which is turned off increases by about one digit. Therefore, in the case of a circuit for a mobile device, the current consumption during standby increases, resulting in faster consumption of the battery of the mobile device.

Therefore, conventionally, the threshold value is determined from the trade-off between circuit speed and leakage current, and the trade-off has been a big problem.

There is a demand for a circuit configuration which can suppress the current consumption at the time of turning off without impairing the high speed operation by using the low threshold transistor. The present invention proposes a semiconductor integrated circuit according to still another solution.

[0015]

A semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit including a first transistor having a first threshold value, which constitutes a semiconductor integrated circuit including a MOSFET. , Or
At least one of the first transistors existing between the power supply or ground and the output circuit to the semiconductor integrated circuit or between the output circuits of the semiconductor integrated circuit to form a current path is connected to the first transistor. It is characterized in that it is replaced with a transistor portion including a second transistor having a second threshold value higher than the threshold value of 1, whereby the above object is achieved.

The semiconductor integrated circuit may be a pass transistor logic circuit, and the first transistor and the second transistor may be NMOS transistors.

The source of the second transistor may be connected to the ground.

The source of the second transistor is connected to the power supply, and the transistor section has a pull-up PMOS that operates only when the second transistor is on.
A transistor may be further included.

The source of the second transistor is connected to the output circuit, and the transistor section may further include a pull-up PMOS transistor that operates only when a high-level signal passes through the second transistor. Good.

In a semiconductor integrated circuit including a first transistor having a first threshold value, which constitutes a semiconductor integrated circuit including a MOSFET, a transistor pair of a pass transistor logic circuit constituting the semiconductor integrated circuit is claimed in claims 3 to 4. It may be replaced by a combination of any two of the transistor units described in the item 5.

A plurality of semiconductor integrated circuits according to any one of claims 1 to 6 may be provided.

The semiconductor integrated circuit is a pass transistor logic circuit, and the pass transistor logic circuit is an NMO.
The semiconductor integrated circuit device may include an S transistor, and the semiconductor integrated circuit device may further include a CMOS logic circuit.

The first transistor is an NMOS transistor, the second transistor is a PMOS transistor, the second transistor has a source, and the source is connected to the power supply. Good.

The output circuit includes a CMOS logic circuit,
The second transistor includes a transmission gate, the transmission gate includes a PMOS transistor and an NMOS transistor, and each of the PMOS transistor and the NMOS transistor includes:
A source may be connected to the CMOS logic circuit.

When a low threshold NMOS transistor is used for the purpose of increasing the speed of the pass transistor logic circuit, the leak current of the transistor which is turned off increases by about one digit each time the threshold is lowered by 0.1V. Therefore, conventionally, the trade-off between circuit speed and leakage current has been a big problem.

Therefore, according to the present invention, 1 directly connecting to the power path
A high threshold NMOS transistor is used as the stage NMOS transistor, and a low threshold NMOS transistor is used as the subsequent NMOS transistors.

As a result, the leakage current of the transistor in the off state is up to a level corresponding to the characteristic of the high threshold NMOS transistor applied to the first stage of the pass transistor logic circuit because the transistors are connected in series. It becomes possible to suppress.

However, in the pass transistor logic circuit, N
Since the logic is composed of MOS transistors, the conductivity of low-level signals is excellent, but when passing high-level signals, the voltage level of the output is reduced by the threshold value of the NMOS transistors due to the influence of the substrate effect. There is a problem. (Here, the signal level is described as a low level being a low level and a high level being an H level. The same applies hereinafter.) Therefore, the NMO of the first stage directly connected to the power supply path.
When a high threshold NMOS transistor is used as the S transistor, the H level is reduced by a high threshold at the first stage, and as a result, the circuit speed of the pass transistor network at the first stage and thereafter is suppressed. The problem comes out.

Therefore, in order to avoid a decrease in the circuit speed due to the deterioration of the signal level corresponding to the high threshold value, which is caused by applying the high threshold NMOS transistor to the first stage,
A PMOS transistor for pull-up that restores the H level of the signal to a level equal to the power supply voltage is added to the output of the first-stage NMOS transistor. As a result, it is possible to achieve the reduction of the leak current at the time of turning off, while enjoying the merit of the circuit speed using the low threshold transistor.

The flow of the leak current in the pass transistor logic circuit is shown in FIGS. 13 (a) and 13 (b) for further explanation.

As shown in FIG. 13, the pass transistor logic circuit has two NMOS transistors as one set,
The logic is configured by selecting either one of them. Therefore, NMOS with a node that directly connects to the power path
In the pass transistor pair, as shown by the arrow in FIG. 13, there is a DC path for the leak current of the transistor when it is off. (A DC signal path of the current to the ground is formed by the high signal of the CMOS inverter output becoming a leak current of one of the OFF transistors via the ON transistor of the pass transistor pair.) FIG. The pass transistor logic circuit has a low threshold N
The leak LIA current in the case of only MOS transistors TrL1 and TrL2 is shown. FIG. 13B shows a leak current L in the case where a pass transistor logic circuit is composed of only high threshold NMOS transistors TrH1 and TrH2.
IB is shown. Every time the threshold is lowered by 0.1 V, the leak current of the transistor which is turned off increases by about one digit. Therefore, for example, the low threshold NMOS transistor T
rL1 and TrL2 (FIG. 13A) and high threshold NMOS
When the threshold difference between the transistors TrH1 and TrH2 (FIG. 13B) is, for example, 0.3 V, the difference in the leak current at the time of OFF is about 1000 times.

For this reason, the pass-transistor logic circuit using the low-threshold NMOS transistor can be sped up, but on the other hand, the standby current consumption becomes very large.
For example, when applying the pass transistor logic circuit to a portable device in which most of the operation is in standby, the low power consumption feature of the pass transistor logic circuit is impaired.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the basic configuration of the present invention.

The input of the pass transistor logic circuit receives the output of the pass transistor logic circuit PTr of the previous stage as it is (FIG. 1A), the ground GND as an input (FIG. 1B), and the power supply VDD. Input (Fig. 1 (c)), other CMOS output (Fig. 1)
(D)). These are a pair of NMOS pass transistors, and one gate has an Enable-
(I), an inverted signal of Enable- (i) (i = a, b, c, d) is input to the other gate.

Regarding the one shown in FIG. 1A which receives the output of the pass transistor logic circuit of the preceding stage as it is,
The low threshold NMOS transistor TrL is used as it is. This is because there is no DC path that directly connects to the power supply in this portion of the pass transistor logic circuit, so that the leak current of the entire circuit is not affected. This allows low threshold NMOS without the disadvantage of increased off-leakage current.
The effect of improving the circuit speed by applying the transistor can be enjoyed.

Referring to FIG. 1B, a high threshold NMOS
The transistor TrH exists between the ground GND and the preceding pass transistor logic circuit PTr. Figure 1
For the node of the NMOS transistor directly connected to the ground GND shown in (b), the high threshold NMOS transistor TrH is used as it is. This is because only a low-level signal ideally passes through this node, so it is not necessary to consider the speed-down of the circuit due to the high-level signal deterioration corresponding to the high threshold generated by using the high-threshold NMOS transistor TrH.

Referring to FIG. 1C, a high threshold NMOS
The transistor TrH exists between the power supply VDD and the pass transistor logic circuit PTr at the previous stage. Figure 1
The high threshold NMOS transistor TrH is also used for the node of the NMOS transistor directly connected to the power supply VDD shown in (c). However, since this node passes only a high level signal, the high threshold NMOS transistor T
When rH is used, high level signal deterioration corresponding to a high threshold value occurs, and the circuit speed is reduced. Then power supply V
When an NMOS node succeeding DD is selected (that is, E
enable- (c) is high level, Enable-
A pull-up PMOS transistor TrP that operates only when the inverted signal of (c) is at a low level is added. As a result, the deterioration of the high level signal that has deteriorated through the high threshold NMOS transistor TrH can be restored to a level equal to the power supply voltage by turning on the PMOS transistor TrP.
It avoids the demerit in the circuit speed using H.

Referring to FIG. 1D, a high threshold NMOS
The transistor TrH exists between the CMOS output CM of the preceding stage and the pass transistor logic circuit PTr of the preceding stage. NM succeeding CMOS output CM shown in FIG.
Also for the OS transistor node, a high threshold NMOS transistor TrH is used. Both a high level signal and a low level signal may be transmitted to this node. Therefore, a pull-up PMOS transistor TrP that operates only when a high-level signal is passed to the node
Is added, and at the time of high level, the PMOS transistor TrP
Is turned on to restore the signal level to a level equal to the power supply voltage. When the signal is at the low level, the pull-up PMOSTrP is turned off, which does not affect the circuit operation.

Another basic structure of the pass transistor logic circuit according to the embodiment will be described with reference to FIG.

For the node of the NMOS transistor directly connected to the power supply VDD shown in FIG. 2A, a high threshold PMOS transistor TrPH is used. PMO
When the S-transistor TrPH is used, the same inversion signal of Enable- (e) as the control signal of the gate of the NMOS transistor TrL can be used as the control signal of the gate. By using the TrPH, it is possible to prevent a decrease in circuit speed due to a decrease in the signal level of the H (high) level signal corresponding to the threshold value, which has been a problem in the pass transistor logic circuit including the NMOS transistor. . Since the high-threshold PMOS transistor TrPH is directly connected to the power supply VDD, the pull-up PMOS, which is a node at the H (high) level, is not required, and the pass transistor logic circuit can be simplified.

Regarding the node of the NMOS transistor connected to the CMOS output CM shown in FIG. 2B,
The transmission gate TMG is used. The transmission gate TMG is an NMOS transistor TrH.
And a PMOS transistor TrPH. Regarding the node of the NMOS transistor connected to the CMOS output CM, both the H (high) level signal and the L (low) level signal may be communicated. By using the transmission gate TMG, the signal can be transmitted to the next stage without deterioration of the signal. This is because the transmission gate TMG has a low on-resistance between the power supply VDD level and the GND level. As a control signal for the gate of the PMOS transistor TrPH, a control signal having an opposite phase to the control signal for the gate of the NMOS transistor TrH is required.

Since the pass transistor logic circuit shown in FIG. 2B does not have the pull-up PMOS transistor TrP shown in FIG. 1D, the circuit is simpler than the pass transistor logic circuit shown in FIG. 1D. Turn into.

Another basic configuration of the pass transistor logic circuit will be described with reference to FIG. FIG. 3A shows an example in which the high threshold NMOS transistor TrH exists between the power supply VDD and the ground GND. In this example, it is necessary to use a high threshold NMOS transistor TrH for both NMOS transistors of the pass transistor logic circuit.

FIG. 3B shows an example in which the high threshold NMOS transistor TrH is present between the CMOS output CM and the ground GND. Also in this example, FIG.
Both NMs of the pass transistor logic circuit are the same as in (a).
High threshold NMOS transistor Tr for OS transistor
It is necessary to use H.

FIG. 3C shows an example in which the high threshold NMOS transistor TrH exists between the CMOS output CM and the power supply VDD. Also in this example, FIG.
As in (a) and FIG. 3 (b), it is necessary to use a high threshold NMOS transistor TrH for both NMOS transistors of the pass transistor logic circuit.

Next, FIG. 4 shows a pass transistor logic cell used in the pass transistor logic circuit. The actual circuit is composed of the combination of cells shown in FIG. By designing this cell and making it into a library, the subsequent design by CAD becomes easy.

FIG. 4 (a) is applied to a portion directly receiving the output of the pass transistor logic circuit of the preceding stage. Since there is no NMOS transistor node directly connected to the power supply, the circuit speed is increased by using the low clique value NMOS transistor TrL as it is.

FIG. 4B shows the case where one side of the NMOS transistor node is the ground GND. Since this node passes only a low level signal, the high threshold NMOS transistor TrH is used as it is to suppress the leak current when it is turned off. It is used in the case of FIG.

FIG. 4C shows the case where one side of the NMOS transistor node is the power supply VDD. By using the high-threshold NMOS transistor TrH and the pull-up PMOS transistor TrP which operates only when the node is selected, the disadvantage in the circuit speed when using the high-threshold NMOS transistor TrH is avoided. It is used in the case of FIG.

FIG. 4D shows the case where the node on one side directly receives the CMOS output CM. By using the high-threshold NMOS transistor TrH and the pull-up PMOS transistor TrP that operates only when a high-level signal is transmitted, the high-threshold NMOS transistor T
Avoid the disadvantage of circuit speed by using rH. It is used in the case of FIG.

FIGS. 4E and 4F show the combination,
Also, one is for connecting to the ground GND or the power supply VDD, and the other is for receiving the CMOS output CM. Figure 4 (g) shows that both nodes are CMOS
This is the case where the output CM is received.

In addition to the above, various combinations are possible depending on the configuration of the pass transistor logic circuit. Actual circuit configuration example (actual circuit configuration and BDD (Binary)
Decision on Diagram (binary decision tree))
An example is shown in FIG. BDD is one of the methods of constructing a pass transistor logic circuit (see “White Paper on Low-Power LSI Technology Challenge 1 Milliwatt, p98-104, Nikkei BP Nikkei Microdevices Edition, October 1994”). In terms of circuit function, this is an example of a 3-input AND (Y = A · B · C). First, a BDD is created as shown in FIG. The pass transistor logic circuit shown in FIG. 5A is obtained by replacing this with a transistor. This pass transistor logic circuit comprises logic only with NMOS transistors.

In FIG. 5 (a), the NM connected to the ground GND
High threshold NMOS transistors TrH1, TrH2, and TrH3 are used for all OS nodes, and a high threshold NMOS transistor TrH4 is used as a node connected to the power supply VDD, and a high level recovery pull-up PMOS transistor TrP that operates only when the node is selected. Is added. A low threshold NMOS transistor Tr is provided at the other nodes.
By using L, the speed of the pass transistor logic circuit is increased. As a result, the leak current is suppressed and the speed is increased.

The threshold value of the NMOS transistor can be increased by ion implantation of boron ("B ⁺ ") into the channel portion of the NMOS transistor or by increasing the gate thickness, which are well known techniques. The description is omitted here.

As described above, it is possible to suppress the leak current at the time of turning off, and it is possible to realize both high speed operation and low power operation of the pass transistor logic circuit.

As described above, it is possible to suppress the leak current of the NMOS transistor at the time of off which occurs when a high speed NMOS transistor is used for the pass transistor logic circuit to increase the speed. As described above, it greatly contributes to low power consumption in a circuit in which many transistors are in a standby state or off.

The relationship between the low threshold voltage and the power consumption is, for example,
"The ASIC threshold voltage is variable and the maximum power consumption is 1
The details are described in "Nikkei Microdevice, August 1996, p. 57-66".

According to the configuration of the present invention, there is no need to add a complicated circuit, and there is no increase in the circuit due to a large increase in the number of transistors.

In the present invention, the ground GND and the power supply VDD
At least one of the transistor groups on the current path between the ground GND or the power supply VDD and the semiconductor integrated circuit or the output of the semiconductor integrated circuit is replaced with a high threshold NMOS transistor. The leakage current of this high threshold transistor determines the leakage of this current path, so that a low leakage current is realized (In order to realize low power consumption, the pass transistor logic circuit and its peripheral circuit are formed by a CMOS logic circuit. The best match is to configure it.).

FIG. 6 is a circuit diagram showing another implementation example of the actual pass transistor logic circuit according to the embodiment. The pass transistor logic circuit shown in FIG.
In the pass transistor logic circuit shown in (a), a high threshold NMOS transistor TrH4 and pull-up PMO are provided.
The S-transistor TrP is a high-threshold PMOS transistor T
In this example, it is replaced with rPH. A control signal common to the control signal of the high-threshold NMOS transistor TrH3 (control signal having a phase opposite to that of the control signal C) can be used. Figure 5
Since the pull-up PMOS transistor TrP used in the pass transistor logic circuit shown in (a) is unnecessary, the circuit can be simplified. Further, as described above, the circuit speed at H level does not decrease.

Similar to the pass transistor logic circuit shown in FIG. 5 (a), in terms of circuit function, a 3-input AND (Y = A.B.
It is an example of C).

In the pass-transistor logic circuit shown in FIG. 6A, all the high-threshold NMOS transistors TrH1 and TrH are connected to the NMOS node connected to the ground GND.
2, TrH3 is used, and a high threshold PMOS transistor TrPH is used for a node connected to the power supply VDD. Low threshold NMOS transistors TrL are used for the other nodes to speed up the pass transistor logic circuit.

Unlike the pass-transistor logic circuit shown in FIG. 5A, the node connected to the power supply VDD has a high threshold PM.
Since the OS transistor TrPH is used, the speed of the pass transistor logic circuit can be further improved,
Further, the circuit configuration can be simplified.

As described above, it is possible to suppress the leak current at the time of turning off, and it is possible to realize both high speed operation and low power operation of the pass transistor logic circuit.

Next, an example in which the high speed realization of the pass transistor logic circuit according to the present invention is easy to understand will be verified with the circuit configuration of FIG. 7, and the effect of the present invention will be further described.

Configuration of the Present Invention FIG. 7A shows, as described above, a PMOS which is turned on only when the CMOS output CM has a high threshold NMOS transistor TrH and a high level signal to guarantee a high level without signal deterioration. Transistor TrP
It is equipped with. The other NMOS transistors forming the pass transistor logic circuit are low-threshold transistors TrL.

This pass transistor section (NMOS in FIG. 7)
Chain part CHA. Two to eight steps should be connected. ), The leakage current at
Moreover, since it is determined by the PMOS transistor TrP, the circuit as a whole maintains a low leak circuit.

On the other hand, as for high speed, the delay time of the output signal of the output terminal Out when the waveform of FIG. 7 (c) is input to the input terminal In is set at the time of rising [delay (ris
e)] and at fall [delay (fall)]
The simulation was performed.

The power supply VDD is 3.3V, the Vth of the high threshold transistor TrH is 0.55V, and the Vth of the low threshold transistor TrL is 0.35V. Delay time is V
It is measured at the point of DD / 2.

FIG. 8 shows the delay time of the falling waveform (the rising waveform in the pass transistor circuit (NMOS chain portion CHA)) and the rising time in the rising waveform (pass transistor circuit (NMOS chain portion CHA)) in FIG. This corresponds to the falling waveform).

NMOS chain portion CHA and FIG.
N of the NMOS chain portion CHB of the conventional circuit shown in (b)
The delay times are compared by changing the number of stages in the chain of MOS transistors.

In FIG. 8, it can be seen that the circuit of the present invention has a shorter delay time than the conventional circuit and has a high speed by the low threshold transistor regardless of the number of stages of the NMOS transistors.

On the other hand, in FIG. 9, the pass transistor section falls through the inverter circuit, and when the previous state of the pass transistor circuit (NMOS chain CHA) is high level, the PMOS transistor Tr
Since P is on, it is difficult for the NMOS chain CHA to go low.

Therefore, when the number of NMOS transistors TrL is 3 or less, the delay time of the circuit is P
The delay time until the MOS transistor TrP turns off cannot be ignored, and the delay time becomes longer than the conventional circuit. However, when the NMOS transistor TrL has four or more stages,
It can be seen that the speedup effect of the low threshold value cancels the delay time for turning off the PMOS transistor TrP, so that the delay time is shorter than that of the conventional circuit and the speed is increased.

Next, another example in which the high speed realization of the pass transistor logic circuit according to the present invention is easy to understand will be verified with the circuit configuration of FIG. 10, and the effect of the present invention will be further described.

The conventional pass transistor logic circuit shown in FIG. 10B includes a high threshold NMOS transistor TrH including the output stage of the CMOS inverter INV0, a high threshold PMOS transistor TrP1 and a high threshold NMOS transistor TrH. A configured inverter INV,
A pull-up PMOS transistor Tr which is turned on at the LOW level of the output of the inverter INV and guarantees a drop in the signal of the High level at the input stage of the inverter INV.
P2 and. The pull-up of the PMOS transistor TrP2 prevents a through current from flowing through the inverter INV.

In the pass transistor logic circuit shown in FIG. 10A, a transmission gate TMG is used in the output stage of the CMOS inverter INV0, and a low threshold NMOS transistor TrL is used in the NMOS chain CHC. The NMOS chain portion CHC is connected to the NMOS transistors TrL of 2 to 8 stages. Since the leak current is determined by the high threshold PMOS transistor TrPH and the high threshold NMOS transistor TrH, the pass transistor logic circuit as a whole maintains a low leak current.

The high speed of the pass transistor logic circuit will be described. The delay time of the output signal of the output terminal Out when the waveform of FIG. 10 (c) is input to the input terminal In is simulated for rising [delay (rise)] and falling [delay (fall)]. The results are shown in FIGS. 11 and 12. To do.

As a simulation condition, the power supply VDD
3.3V, Vth of the high threshold transistor TrH is 0.55V, Vth of the low threshold transistor TrL is 0.
It is set to 35V. The delay time is measured at the point of VDD / 2.

FIG. 11 shows the delay time of the falling waveform (the rising waveform in the pass transistor circuit (NMOS chain portion CHC)) and the rising waveform (pass transistor circuit (NMOS chain portion CHC)) in FIG.
Then, hit the falling waveform. ) Delay time of NMO
The number of stages of the S chain portions CHC and CHD is shown by being changed.

It can be seen from FIG. 11 that the circuit of the present invention has a shorter delay time than the conventional circuit and has a high speed by the low threshold transistor regardless of the number of stages of the NMOS transistors.

On the other hand, in FIG. 12, the inverter circuit INV
Through 0, the pass transistor sections CHC and CHD fall. In this case, the PMOS transistor Tr forming the transmission gate TMG
Due to the back gate effect of PH, it is less likely to go to a low level than when a single NMOS is configured.

Therefore, the NMOS transistor TrL
When the number of stages of the (NMOS chain portion CHC) is 4 or less, the delay time for returning the level of the PMOS transistor TrP and discharging the path becomes larger than the delay time of the entire circuit, and therefore the delay time is longer than that of the conventional circuit. However, it can be seen that when the NMOS transistor TrL (NMOS chain portion CHC) has five or more stages, the high-speed effect of the low-threshold NMOS transistor TrL is exerted, and the delay time is shortened and the speed is increased as compared with the conventional circuit.

[0084]

As described above, it is understood that, when a low-threshold transistor is used as a basic component for speeding up, low power consumption is realized by reducing leak current. This greatly contributes to the development of semiconductor integrated circuit devices used in portable equipment.

The leakage current due to a current path between the ground GND and the power supply VDD, between the ground GND or the power supply VDD, and the output portion of the semiconductor integrated circuit, for example, has a high threshold value for one or both transistors in the current path. It can be suppressed by forming a transistor.

According to the circuit configuration of the present invention, the ground GN
D, power supply VDD, and a high-threshold transistor or a PMOS transistor for high-level guarantee without signal deterioration are arranged together with the NMOS transistor connected to the CMOS output section that outputs to the pass transistor logic circuit, so that the arrangement location is unique. It is not necessary to examine the location of the high-threshold NMOS transistor by verifying the current path, and the design becomes easy.

Furthermore, by designing the main circuit components of the present invention as logic cells as shown in FIG. 4 and forming a library, there is an effect that the design by CAD can be facilitated.

Finally, the present invention is not limited to expansion to other combinations of pass transistor logic circuits, but can be expanded to other logic circuits and other circuits such as CMOS circuits. Of course.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a basic configuration of a pass transistor logic circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing another basic configuration of the pass transistor logic circuit according to the embodiment of the present invention.

FIG. 3 is a circuit diagram showing still another basic configuration of the pass transistor logic circuit according to the embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of an actual transistor logic cell used in the pass transistor logic circuit according to the embodiment. The combination of these forms a pass transistor logic circuit.

FIG. 5 is a circuit diagram showing an implementation example of an actual pass transistor logic circuit according to the embodiment.

FIG. 6 is a circuit diagram showing another implementation example of the actual pass transistor logic circuit according to the embodiment.

FIG. 7 is a circuit diagram of a pass transistor logic circuit according to an embodiment of the present invention.

FIG. 8 is a table for comparing the delay times of the falling waveforms of the pass transistor logic circuit according to the embodiment and the conventional circuit.

FIG. 9 is a table for comparing delay times of rising waveforms of the pass transistor logic circuit according to the embodiment and the conventional circuit.

FIG. 10 is a circuit diagram of another pass transistor logic circuit according to the exemplary embodiment of the present invention.

FIG. 11 is a table for comparing delay times of falling waveforms of another pass transistor logic circuit according to the embodiment and a conventional circuit.

FIG. 12 is a table for comparing delay times of rising waveforms of another pass transistor logic circuit according to the embodiment and a conventional circuit.

FIG. 13 is a diagram illustrating a leak current in a pass transistor logic circuit.

[Explanation of symbols]

TrL Low threshold NMOS transistor TrH High threshold NMOS transistor TrP pull-up PMOS transistor GND ground VDD power supply CM CMOS output

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP 10-224206 (JP, A) JP 10-200394 (JP, A) JP 9-148916 (JP, A) JP 9- 64283 (JP, A) JP 9-18332 (JP, A) JP 7-168874 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03K 19/0944 H01L 21 / 822 H01L 27/04

Claims (10)

(57) [Claims] 1. A semiconductor integrated circuit comprising a first transistor having a first threshold value, which constitutes a semiconductor integrated circuit including a MOSFET, wherein a power source and a ground are provided, or a power source or a ground and the semiconductor integrated circuit are provided. Between the output circuit, or
At least one of the first transistors existing between output circuits of the semiconductor integrated circuit and forming a current path includes a second transistor having a second threshold value higher than the first threshold value. A semiconductor integrated circuit characterized by being replaced by a transistor section. 2. The semiconductor integrated circuit is a pass transistor logic circuit, and the first transistor and the second transistor are NMOS transistors.
The semiconductor integrated circuit according to 1. 3. The semiconductor integrated circuit according to claim 2, wherein the source of the second transistor is connected to the ground. 4. The source of the second transistor is connected to the power supply, and the transistor portion further includes a pull-up PMOS transistor that operates only when the second transistor is on. Item 2. The semiconductor integrated circuit according to item 2. 5. The source of the second transistor is connected to the output circuit, and the transistor section is a pull-up PMOS that operates only when a high-level signal passes through the second transistor.
The semiconductor integrated circuit according to claim 2, further comprising a transistor. 6. A semiconductor integrated circuit including a first transistor having a first threshold value that constitutes a semiconductor integrated circuit including a MOSFET, wherein a transistor pair of a pass transistor logic circuit that constitutes the semiconductor integrated circuit is defined by claim 3. 6. A semiconductor integrated circuit characterized by being replaced by any two combinations of the transistor parts according to claim 5. 7. A semiconductor integrated circuit device comprising a plurality of semiconductor integrated circuits according to claim 1. Description: 8. The semiconductor integrated circuit is a pass transistor logic circuit, the pass transistor logic circuit is configured by an NMOS transistor, and the semiconductor integrated circuit device further includes a CMOS logic circuit. Item 8. A semiconductor integrated circuit device according to item 7. 9. The first transistor is an NMOS transistor, the second transistor is a PMOS transistor, the second transistor has a source, and the source is connected to the power supply. The semiconductor integrated circuit device according to claim 1. 10. The output circuit includes a CMOS logic circuit, the second transistor includes a transmission gate, the transmission gate includes a PMOS transistor and an NMOS transistor, and the PMOS transistor and the NMOS transistor. 2. The semiconductor integrated circuit device according to claim 1, wherein each has a source, and the source is connected to the CMOS logic circuit.