JP3516877B2 - AD converter with integration function - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AD (analog-digital) converter having an integration function in an analog-digital mixed electronic circuit. It also relates to an AD converter that integrates a plurality of analog input signals and performs AD conversion.

[0002]

2. Description of the Related Art Conventionally, a delta-sigma AD converter has been known as a type of AD converter. This Delta Sigma A
The characteristic of the D converter is that as the oversampling rate is increased, the noise in the low frequency band is reduced, and instead the noise is biased to the high frequency band. Therefore, the output of the delta-sigma AD converter has a decimation low-pass filter to remove this high frequency noise. However, in order to improve the performance (resolution) of this delta-sigma AD converter, it is necessary to improve the characteristics of the decimation low-pass filter. Therefore, when the high-resolution delta-sigma AD converter is implemented as an LSI, the circuit scale of the filter becomes large.
There was a problem that the cost of SI becomes high. Therefore,
A means for increasing the resolution without increasing the cost is being considered. As one of them, special table 10-5081
There is a PR (Pulse Reset) -AD converter disclosed in Japanese Patent No. 67. The configuration of this PR-AD converter is shown in FIG. The operation of the PR-AD converter will be briefly described below.

The PR-AD converter comprises a primary delta sigma modulator 81, an N1 bit counter 82, an N2 bit AD converter 83 and an adder 84. The primary delta sigma modulator 81 comprises an adder 811 and an integrator. 812, the comparator 813,
It comprises a one-sample delay device 814 and a DA converter 815.
The first-order delta-sigma modulator 81 outputs 1-bit data. Since each of these functions is publicly known or described in the above-mentioned publication, a detailed description of each operation will be omitted and an outline of the overall operation will be described. Integrator 812
And the delay device 814 have a reset (also called dump) function, and the residual voltage of the integrator 812 and the contents of the delay device 814 are set to 0.
You can Therefore, before starting the AD conversion, the integrator 812, the delay device 814 and the counter 82 are reset. When the analog signal is input to the first-order delta-sigma modulator 81, 2 ^N1 −
The operation of a normal delta-sigma modulator is performed over one sample period. The counter 82 counts the number of 1s in the 1-bit data output for each sample section of the comparator 813. Here, the comparator 813 outputs 1 when the input is positive,
Assuming that 0 is output when it is negative, N1 bit offset binary data obtained by AD converting the analog input signal is obtained. What is offset binary data?
It is data in which the numerical value 0 is assigned to the minimum quantized value (the value on which the absolute value of the quantized value is maximum on the negative side), and the numerical values 1, 2, ... Are assigned in the order of increasing quantized value. . Furthermore, by moving the delta-sigma modulator 81 by setting the analog input to 0 in the next 1 sample interval, 2 ^N1
The comparison result of the comparator 813 performed at the -1st sample is reflected in the residual voltage of the integrator 812. As a result, the residual voltage of the integrator 812 stores the quantization error due to the conversion of the analog input signal into N1 bit digital data. Therefore, the N2 bit AD converter 83
AD-converts the residual voltage of the integrator 812 to obtain N2-bit digital data, and then the adder 84 performs the N conversion.
N1 + N2 bit digital data is obtained by performing weighted addition with 1 bit offset binary data.
Here, if the AD converter 83 also outputs offset binary data, the N1 and N2 bits of data are simply bit-combined, and the adder 84 is not necessary. However, since the offset binary may be inconvenient in the data processing after AD, an adder 84 for converting it to normal complement 2 binary data (adding an offset from the original numerical value) may be required. It goes without saying that the structure of the counter 82 and the adder 84 in this PR-AD converter is simple. The AD converter 83 can be realized by various methods, but the circuit scale can be small if the conversion bit number N2 is small. If the conversion time has a margin, the delta-sigma modulator 81 can be used as the AD converter 83. Therefore, this PR-AD converter can be made considerably smaller than the circuit scale of a general delta-sigma AD converter that requires a high-performance decimation low-pass filter.

Now, consider a 2-bit output delta-sigma modulator as the delta-sigma modulator 81 of the PR-AD converter. That is, the comparator 91 of FIG. 9 is replaced by the delta-sigma modulator 8
Use for 1. This comparator 91 includes two comparators 911 and 9
12 and the comparator 911 outputs the integrator 812 output Iout
And positive reference voltage ref ₊ are compared and 1-bit data Cout
1, the comparator 912 compares the negative reference voltage ref ₋ with the output Iout of the integrator 812, and outputs 1-bit data Cout2. ref ₊ = -ref _- to. That is, the integrator 812
Cout1 outputs 1 when the output Iout is larger than the positive reference voltage ref _+, and Cout2 outputs 1 when the integrator 812 output Iout is smaller than the negative reference voltage ref ₋ . Integrator 812 output Io
If ut is between the positive side reference voltage ref ₊ and the negative side reference voltage ref ₋ , both Cout1 and Cout2 output 0. Therefore, an N1 + 1 bit up / down counter is used as the counter 82 and counts up when Cout1 is 1 and counts down when Cout2 is 1. Also, the DA converter 815
When the outputs Cout1 and Cout2 of the comparator 91 are 1, 2ref ₊ and -2ref ₊ are output in the next sample section, respectively. DA converter 815 when both Cout1 and Cout2 are 0
Outputs 0. N1- of the PR-AD converter in this case
In the AD conversion processing over one sample section, the counter 82
The output of is the binary data of N1 + 1 bit complement 2. This data is D1. The output data of the AD converter 83 is D2. The AD converter 83 is a mid-riser type having the quantization characteristic shown in FIG. The riser is a stair riser, and the type name of this AD converter indicates the state of the quantization characteristic at the origin of the stairs. That is, the mid riser type AD converter is an AD converter that does not take a quantized value of 0 when the input is 0. Like D1, D2 is complemented 2 data. As a result, the adder 84 can perform addition processing on negative data without distinguishing it from positive data. A straightforward and simple method of a specific weighted addition method in the adder 84 will be described. First, the output data D1 of the counter 82 is shifted to the left by N2 bits, that is, D1 × 2 ^N2 is calculated. Then, the output data D2 of the AD converter 83 is sign-extended to (N1 + 1) + N2 bits (the lower N2 bits remain D2 and all the upper N1 bits become the same as the most significant bit of D2), and the adder 8
4 calculates (D1 × 2 ^N2 ) + (sign-extended D2), and this PR-AD converter can have an accuracy of (N1 + 1) + N2 bits. A / D converter 83 has a quantization characteristic shown in FIG. 10B.
In the case of the type (tread means the tread of the stairs), the counter 82 is added in the addition process in the mid riser type.
Output data D1 of N is shifted by N2-1 bits, that is, D
The place where 1 × 2 ^N2 −1 is calculated is different from the place where the number of code extension bits of D2 is N1 + N2. As a result, the PR-AD converter having the midtread type AD converter is N1.
It has + N2 bit precision.

Japanese Patent Publication No. 10-508167 discloses that this PR-AD converter has a period integration function. That is, the PR-AD converter performs periodic integration by periodically performing AD conversion of a result of integration over a certain section after reset, that is, constant integration. The above-mentioned publication describes an embodiment in which the PR-AD converter simultaneously performs averaging processing by integration of the weak output signal of the infrared image sensor and AD conversion.

[0006]

Even in a PR-AD converter which originally has a small circuit scale, there is a problem that the circuit scale of the adder 84 becomes large as the number of bits to be handled increases.

In some cases, like the correlator used in the spread spectrum receiver, the periodic integration must be performed without interruption. Therefore, if the PR-AD converter is used as it is, the PR-AD converter is reset,
There is a problem that it is not possible to have time to perform AD conversion on the residual voltage. Naturally, since the integral calculation must always be performed, the operation of the AD converter 83 cannot be performed by the delta-sigma modulator 81. That is, the AD converter 8
Be sure to prepare another AD converter for 3.
Further, a delay locked loop (DLL) synchronization tracking circuit and a matched filter using a large number of correlators (Japanese Patent Application No. 10-2
No. 39864) and a circuit using a plurality of correlators.
When the R-AD converter is used, the delta-sigma modulator 81 of each correlator always operates, while the AD converter 83 operates only for a temporary period, which causes a problem of inefficiency. In the matched filter of Japanese Patent Application No. 10-239864, it is stated that the number of correlators is increased from the desired number by several so that the correlators can be dumped (reset). In the matched filter, when a PR-AD converter is used, the addition of several correlators for resetting and AD conversion of the residual voltage is originally about a few hundred desired correlators. Therefore, although the increase of several pieces per se is not so problematic, it is very problematic in terms of circuit scale to have the AD converters 83 in all the correlators. On the other hand, since the number of correlators is originally several in the DLL synchronization tracking circuit having a small circuit scale, adding several more correlators for resetting and AD conversion of the residual voltage is itself a problem in terms of circuit scale. Become.

[0008]

According to a first aspect of the present invention, a 2-bit first-order delta-sigma modulator having a dump function of an internal integrating circuit and an input signal by up-down counting by the output of the delta-sigma modulator are provided. The up-down counter that performs rough AD (analog-digital) conversion of the integrated value of the above, and the above-mentioned integrator circuit performs integration of 0 input after completion of the integration to quantize the residual voltage of the integrator circuit caused by the coarse AD conversion. In the AD converter with an integration function, which operates so as to generate an error and further includes an AD converter for AD-converting the quantization error, the up / down counter is the maximum output of the AD converter for AD-converting the residual voltage. Performing a down-count process when the upper bit is 1, and an AD converter for AD-converting the contents of the up-down counter and the residual voltage An integral function AD converter, characterized in that to obtain a high conversion data accuracy coarser AD conversion data of the integral value of the input signal by outputting the bit coupling the output data.

With this configuration, the output of this AD converter with an integration function is binary data of complement 2,
When the residual voltage is negative, the most significant bit of this AD conversion value is 1.
Therefore, the contents of the up-down counter can be decremented by 1 by down-counting the up-down counter by this most significant bit. As a result, since the conversion data of the integrated value of the input signal with high accuracy can be obtained by simply bit-combining the contents of the up-down counter and the AD conversion value of the residual voltage as they are, the contents of the up-down counter which have been conventionally required. And an adder for weighted addition of the AD conversion value of the residual voltage becomes unnecessary.

According to a second aspect of the present invention, there is provided a first-order delta-sigma modulator having a dump function of an internal integrating circuit, and a counter for performing coarse AD conversion of an integrated value of an input signal by counting by the output of the delta-sigma modulator. , The integration circuit operates so that the residual voltage of the integration circuit becomes a quantization error caused by coarse AD conversion by performing integration of 0 input after the integration is completed, and further, this quantization error is AD-converted. An AD converter having an integration function including an AD converter and an adder for weighting and adding the contents of the counter and the output of the AD converter to obtain conversion data with higher accuracy than AD conversion having a coarse integral value of the input signal. , The number of delta sigma modulators and counters for AD conversion of a plurality of analog input signals is the same as the number of input signals, and each delta sigma modulation There is a sample and hold circuit group for storing a plurality of residual voltages of the integrating circuit and a register group for storing a plurality of contents of each counter, and there are one to several AD converters for AD converting the residual voltage. The AD converter AD-converts each of the residual voltages stored in the sample-hold circuit group, and stores it in a register group having a correspondence relationship with the output of the AD converter and the converted residual voltage. The contents of the counter are weighted and added by the adder described above.
It is a D converter.

AD with integration function having a plurality of input signals
With the above configuration, the converter can share a minimum of one AD converter that AD-converts the residual voltage of the integration result of each signal, and therefore the circuit scale can be reduced.

According to a third aspect of the present invention, a 2-bit first-order delta sigma modulator having a dump function of an internal integrating circuit and a coarse AD conversion of an integrated value of an input signal are performed by counting by the output of the delta sigma modulator. The up-down counter and the integrator circuit operate so that the residual voltage of the integrator circuit becomes a quantization error caused by coarse AD conversion by performing integration of 0 input after the integration is finished. In an AD converter having an integration function, which includes an AD converter for AD converting, a plurality of delta sigma modulators and counters are present for AD converting a plurality of analog input signals, and each delta sigma modulator There is a sample hold circuit group that stores the same number of residual voltages as the number of input signals of the integrating circuit of, and an AD converter that performs AD conversion of the residual voltage is There are one to several smaller than the number of force signals, and this AD converter AD-converts each of the residual voltages stored in the sample and hold circuit group and determines whether the residual voltage before storage is positive or negative. If the result of the comparing means is negative after the integration of the integrator is completed, the comparing means for judging and the counter perform down-counting processing, and further, after the counting processing is completed, the contents of the respective counters are There is a register group to save, and this AD
It is characterized in that the contents of the counter stored in the register group corresponding to the output of the converter and the converted residual voltage are bit-combined to obtain conversion data with higher accuracy than the AD conversion having a coarse integral value of the input signal. AD with integration function
It is a converter.

This AD converter with an integration function for a plurality of signals is configured as described above, and when the residual voltage of the integration result of each signal is negative, the corresponding up / down counter down-counts the contents of the up / down counter. Can be reduced by one. As a result, the conversion data of the integrated value of the input signal with high accuracy can be obtained by simply bit-combining the contents of the up / down counter and the AD conversion value of the residual voltage as they are. The adder for weighted addition of the contents of the counter and the AD conversion value of the residual voltage becomes unnecessary.

According to a fourth aspect of the present invention, the residual voltages of the plurality of delta-sigma modulators have the same output cycle and are output with being shifted from each other, and the AD converter for AD-converting the residual voltage is a pipeline type. For example, the sample-hold circuit group can be omitted, and the AD converter with an integration function according to claim 2 or claim 3 is characterized.

With this configuration, the sample-and-hold circuit group can be omitted in this AD converter with an integration function, so that the circuit scale can be reduced.

According to a fifth aspect of the present invention, in a C-tap matched filter for performing despreading in a spread spectrum receiver, the matched filter calculates a product of an analog received signal and a spread signal, and a multiplication means for calculating the product. A plurality of correlating means for obtaining cross-correlation consisting of integrating means for performing cyclic integration and a spread signal delay means for outputting each of the spread signals for a certain section by sequentially delaying each of the correlating means by a chip cycle, and outputting the plurality of integrating means. The means is the AD converter with integration function according to claim 2, claim 3 or claim 4, the number of the integration means is the number of taps C, and the number of chip sections D according to the dump time of one integration means. Then, the residual voltage is obtained by integrating the 0 input after the integrating means has finished the integration, and the residual voltage is stored in the sample hold circuit group, and the counter contents are stored in the register group. A matched filter, which is a sum of the chip section number E corresponding to the processing time that exists (C + D + E).

With this configuration, the matched filter has the addition of the integration means including the delta sigma modulator corresponding to the integration of 0 input, so that an AD converter with an integration function having a small circuit scale can be used. Therefore, the circuit scale of the matched filter itself can be reduced.

According to a sixth aspect of the present invention, in the AD converter with an integration function corresponding to a plurality of inputs, the residual voltage is AD-converted in a state in which each integration means does not perform 0-input integration after completing integration in a certain section. It is characterized by the above-mentioned.
It is an AD converter with an integration function as described in any one of items .

This AD converter with an integration function does not need to perform 0-input integration due to the above configuration, so that the AD converter with an integration function with a small circuit scale can be used for periodic integration without interruption.

According to a seventh aspect of the present invention, the DLL synchronization of the spread spectrum receiver has a multiplication means for calculating the product of the analog reception signal and the spread signals of several different phases and a plurality of integration means for periodically integrating the product. In the tracking circuit, the plurality of integrating means are AD converters with an integrating function according to claim 6, which is a DLL synchronization tracking circuit.

With this configuration, this DLL synchronization tracking circuit does not need to be provided with a separate integrating means for zero-input integration and dump, so that a DLL synchronization tracking circuit with a small circuit scale can be realized.

In the matched filter, the AD converter with an integration function may be the AD converter with an integration function according to claim 6.

With this configuration, this matched filter does not need to be provided with a separate integrating means for zero-input integration and dump, so that a matched filter with a small circuit scale can be realized.

According to an eighth aspect of the present invention, in the AD converter with an integration function for a plurality of inputs, each counter is an up / down counter, and the up / down counter is composed of two asynchronous one-way counters. The AD converter with an integral function according to claim 2, claim 4 or claim 6, wherein the adder for performing the weighted addition performs the calculation for obtaining the up / down count result from the content.

The AD converter with the integration function, which has the above-described configuration, does not require an adder for separately obtaining the up / down result, and can reduce the circuit scale.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a P for implementing the present invention.
It is a block diagram which shows the structure of an R-AD converter. 1 is 2
A bit output first-order delta-sigma modulator, in which 11 is a subtractor, 12 is an integrator, 13 is a comparator having the configuration of FIG. 9, 14 is a delay device, and 15 is a DA converter. 2 is an N1 + 1 bit up / down counter that counts up / down according to the output of the comparator 13, and 3 is an integrator 12.
It is an AD converter that AD converts the residual voltage of. Here again, the relationship between the positive and negative reference voltages in FIG. 9 is ref ₊ = −ref ₋ . The comparator 13 outputs 2-bit data Cout1 and Cout2. If the input is higher than the positive reference voltage ref _{+, the} output is Co.
When ut1 = 1 and Cout2 = 0, when the input of the comparator 13 is smaller than the negative reference voltage ref _{−, the} output is Cout1 = 0 and Cout2 = 1.
If the input of the comparator 13 is between the positive reference voltage ref ₊ and the negative reference voltage ref ₋ , the output is Cout1 = 0 and Cout2 = 0. The output of the AD converter 3 is assumed to output complemented binary data. These components are PR-s having the 2-bit output first-order delta-sigma modulator described in the above-mentioned prior art.
It is functionally the same as the component of the AD converter. In addition,
As in the prior art, the up-down counter 2 operates when the first-order delta-sigma modulator 1 is operating normally, and when the output Cout1 of the comparator 13 is 1, the up-down counter 2 counts up, and the comparator 13 When the output Cout2 of 1 is down-counted, the AD converter 3 performs AD conversion, and if the most significant bit MSB of the converted data is 1, down-counting is performed. After that, the data of the up / down counter 2 and the data of the AD converter 3 are bit-combined. The operation of the PR-AD converter of FIG. 1 will be described below. Voltage of the input analog signal is 2ref _- intended to fall within the range from 2ref _+. First, before starting AD conversion, the integrator 1
2. Reset the delay device 14 and the up / down counter 2. That is, the residual voltage of the integrator 12 is set to 0, and the delay unit 1
4. Set the contents of the up / down counter 2 to 0. When the analog signal is input, the first-order delta-sigma modulator 81 operates as a normal delta-sigma modulator over the 2 ^N1 −1 sample period. That is, in a certain sample section n, the difference between the input signal and the output of the DA converter 15 is calculated by the subtractor 11, and the result is integrated by the integrator 12. The output of the integrator is compared with the positive reference voltage ref ₊ and the negative reference voltage ref ₋ by the comparator 13, and the result is 2-bit data (Cout1 (n), Cout2 (n)).
Is output as. The data Cout1 (n) and Cout2 (n) are delayed by one delay period in the delay unit 14. Therefore, the DA converter 15 outputs the signal Cout one sample period before.
1 (n-1) and Cout2 (n-1) are input. And Cout1 (n-1)
Is 1, the DA converter 15 outputs 2ref ₊ and Cout2 (n
When -1) is 1 2ref _- a, except they outputs 0.
By subtracting the output of the DA converter 15 by the subtractor 11, the integrated voltage (residual voltage) of the integrator 12 must be 3r.
It falls within the range of ef _- to 3ref ₊ . During this period, the up / down counter 2 performs counting operation according to the output of the comparator 13. As a result, the up / down counter 2 stores the complemented 2 N1 + 1-bit binary data D1 as a result of integration and AD conversion of the input signal. Next, the analog input is set to 0 and the delta sigma modulator 81 is moved to reflect the result of comparison by the comparator 13 performed at the 2 ^N1 −1th sample in the residual voltage of the integrator 12. Possible range of the residual voltage ref _- a ~ref _+. And
The AD converter 3 AD-converts the residual voltage into N2-bit complement 2 binary data D2. After the conversion is completed, the most significant bit (MSB) of the output data D2 of the AD converter 3 is 1
When, it means that the AD conversion value is a negative value. Therefore, the up / down counter 2 performs "D1-1" by counting down. This is nothing but the calculation of the result of sign extension of the output data D2 of the AD converter 3 described in the prior art within the digit of the data D1 of the up / down counter 2. If the MSB of D2 is 0, the up / down counter 2 does nothing. The data resulting from the processing of the up / down counter 2 by the MSB of the output data D2 of the AD converter 3 is defined as D1 ′, and if the AD converter 3 is a mid riser type, D1 ′ and D2 are bit-coupled, that is, D1 ′. The least significant bit (LSB) of the D2 is simply 1 bit higher than the MSB of D2 and is (N1 + 1) + N2.
It becomes the output of the PR-AD converter by converting it to bit data. If the AD converter 3 is a mid-tread type, the LSB of the data D1 and the MSB of the data D2 correspond to the same digit,
Since the calculation of the MSB of the data D2 and the data D1 has already been reflected in D1 ′, the data obtained by removing one bit of the MSB from the data D2 is set as D2 ′, and D1 ′ and D2 ′ are bit-combined to perform PR-AD. It is the output of the converter. In this case, it becomes N1 + N2 bit data. As described above, since the weighted addition of the counter output data and the AD converter output data can be performed by the counting process of the counter, the adder which has been conventionally required is not required.

Next, an embodiment of the present invention which is effective when a plurality of PR-AD converters are required is shown. FIG. 2 shows the structure of a PR-AD converter having a plurality of analog inputs according to the present invention. The blocks 21-1 to 21-M each include one primary delta sigma modulator 211-1 to 211-M and one counter 212-1 to 212-M. The counters 212-1 to 212-M are N1 bit counters in the case of an up counter and N1 + 1 bit counters in the case of an up / down counter. First-order delta-sigma modulator 211-
1-211-M have the same function as the delta-sigma modulator used in the conventional PR-AD converter, and have a reset function. 22 is an N1 or (N1 + 1) bit × L word register bank, which is composed of L N1 or (N1 + 1) bit registers, and each counter 212-1 to 212-M.
Among them, L pieces of N1 or (N1 + 1) bit data are stored via the digital bus 27. 23 is a sample and hold bank 23 composed of N sample and hold circuits
Then, N residual voltages of the respective integrators in the delta-sigma modulators 211-1 to 211-M are stored via the analog bus 26. Reference numeral 24 denotes an N2 bit AD converter, which is a delta sigma modulator 21 stored in the sample hold bank 23.
The residual voltage of each integrator in 1-1 to 211-M is AD-converted. Reference numeral 25 denotes an adder, which is data of the counters 212-1 to 212-M stored in the register bank 27 and delta-sigma modulators 211-1 to 211-2 corresponding to the data.
The residual voltage of each integrator in 11-M is weighted and added with the AD-converted data. Since the analog bus 26 and the digital bus 27 can be regarded as performing an operation of selecting one signal from a plurality of signals, a multiplexer may be used for them.

The operation of the PR-AD converter shown in FIG. 2 will be described below. Blocks 21-1 to 21-M, which are composed of delta sigma modulators and counters, operate with the delta sigma modulators and counters of a normal PR-AD converter by inputting different analog signals. That is, each of the blocks 21-1 to 21-1
21-M resets the internal integrator and the counter respectively, integrates the analog input signal over 2 ^N1 −1 sample intervals, and N1 bits (N1 + 1 if the counter is an up / down counter if the AD conversion value of the integration is stored in the counter.
Bit) data is obtained. The sigma-delta modulator 21 of the block (21-m) where this integration is completed
The residual voltage Vm of the integrator in 1-m is stored in one sample and hold circuit in the sample and hold bank 23 through the analog bus 26. Also, block 21-
The data D1m of the m counter 212-m is transferred to the N1 of the register bank 27 through the digital bus 27.
Alternatively, it is stored in the (N1 + 1) bit register. In this way, the sample-hold bank 23 sequentially stores the residual voltage of the integrator in the sigma-delta modulator of the block in which the integration is completed among the blocks 21-1 to 21-M, and the register bank 27 Counter data is sequentially saved. The N2 bit AD converter 24 AD-converts the residual voltage stored in the sample hold bank 23 one after another. For example, the residual voltage Vm of the integrator in the sigma-delta modulator 211-m is AD-converted by the AD converter 24. Then, in the adder 25, the AD-converted integral residual voltage data D2m is weighted and added to the integral data D1m stored in the register bank 27. As a result, the (N1 + N2) or (N1 + N2 + 1) -bit digital signal of the analog signal integrated in the block 21-m is obtained. Then, since the residual voltage Vm stored in the sample hold bank 23 and the integral data D1m stored in the register bank 27 are no longer necessary, the sample hold circuit and the register in which they are stored are the residual voltage of other blocks, Can be used to store integral data.

The number N of residual voltages stored in the sample-hold bank 23 and the number L of integrated data stored in the register bank 27 are the timing at which the residual voltages of the blocks 21-1 to 21-M are determined and the AD converter 24. Related to the conversion time of. That is, when the residual voltage of each of the blocks 21-1 to 21-M is concentrated at a certain time, the AD converter 24 performs AD conversion of one residual voltage to some extent, if the conversion time is long. Since the residual voltage that cannot be stored is accumulated, the number N of sample hold circuits that store the residual voltage and the number L of the registers that store the integrated data corresponding to these residual voltages increase. If the number N of sample-hold circuits or the number L of registers is equal to the number M of blocks of the delta-sigma modulator and the counter, the sample-hold bank 23 and the register bank 27 are not provided and the delta-sigma modulation is performed as shown in FIG. In each of the blocks 31-1 to 31-M composed of a counter and a counter, sample hold circuits 313-1 to 313-M for storing the residual voltage and registers 314-1 to 314-M for storing the integrated data may be provided. . In this case, the analog bus 34 connects the outputs of the sample hold circuits 313-1 to 313-M and the input of the AD converter 32, and the digital bus 35 connects one of the registers 314-1 to 314-M and the adder 33. Connect the inputs. In FIG. 3, both the sample hold circuit and the register are placed in each block 31-1 to 31-M, but only one may enter each block and the other may be outside the block as a bank. Further, in FIG. 2, when the blocks 21-1 to 21-M in which the residual voltage is determined have the same cycle and are always deviated from each other, if a pipeline type AD converter is used as the AD converter 24, a sample hold bank is used. 23 can be eliminated. That is, since each residual voltage input to the AD converter 24 is input at a constant interval, the AD converter 24 stores the residual voltage by inputting the residual voltage at that interval and performing pipeline AD conversion processing. There is no need. In this case, the number of registers L of the register bank 27 is the actual A of one data in the AD converter 24.
This corresponds to the number of pieces of data taken into the AD converter 24 during the D conversion period.

When the 2-bit output delta-sigma modulator is applied to the PR-AD converter shown in FIG. 2, the adder 25 can be omitted as shown in FIG. This is shown in FIG. 41
Each of the blocks -1 to 41-M includes one 2-bit delta sigma modulator 411-1 to 411-M and one up / down counter 412-1 to 412-M,
Reference numerals 42, 43, 44, 46 and 47 have the same functions as the register bank 22, the sample hold bank 23, the AD converter 24, the analog bus 26 and the digital bus 27 of FIG. 2, respectively. Reference numeral 45 is a comparator, and 48 is a digital bus. In FIG. 1, the sign of the residual voltage of the integrator 12 is AD.
It was understood by looking at the MSB of the converter 3. When there are many residual voltages as shown in FIG. 4, since there is no time to operate the counters 412-1 to 412-M after seeing the output result of the AD converter 44, the comparator 45 indicates the residual voltage. We will decide whether the sign is positive or negative. That is, blocks 41-1 to 41
When the integration of one block (-41-m) of -M is completed, the residual voltage of the block 41-m is stored in the sample hold bank 43, and at the same time, the comparator 45 determines whether the residual voltage is positive or negative. judge. Then, the determination result is input to the up / down counter 412-m of the block 41-m in which the residual voltage is stored, through the digital bus 48. If the residual voltage is negative, the up / down counter 412-m counts down by one. If the residual voltage is positive, the up / down counter 412-m does nothing. And this up-down counter 412
The contents of -m are saved in register bank 42. If the residual voltage of the block 41-m is converted by the AD converter 44, this data is set to the lower order, and the contents of the up / down counter 412-m stored in the register bank 42 is set to the higher order, and the result is combined. It becomes digital data of complement 2. Since the circuit scale of the comparator 45 is not so large, the effect of reducing the circuit scale by omitting the adder 25 of FIG. 2 is great when the number of bits to be handled is large, as shown in FIG. Needless to say, the digital buses 47 and 48 can be integrated as long as there is no conflict between the determination result of the residual voltage and the output of the up / down counter.

In the PR-AD converter shown in FIGS. 2 to 4,
Although only one AD converter 24, 32, 44 for AD-converting the residual voltage is used, if the number of input signals is very large or the integration period is short, one AD converter is used. There are cases where we cannot handle it. In this case, A above
It is sufficient to provide several D converters. However, since the number of input signals can be reduced, the circuit scale can be reduced as compared with the conventional method of providing the same number of AD converters as the number of input signals.

If the PR-AD converter shown in FIGS. 2 to 4 is applied to a matched filter (Japanese Patent Application No. 10-239864) using a large number of correlators described in the problem to be solved by the invention. , The problem (there are many AD converters for residual voltage) when the conventional PR-AD converter is used for the matched filter can be solved. In order to explain this, first, how to apply the PR-AD converter of FIG. 2 to a matched filter will be described. FIG. 5 shows PR- of FIG.
It is a block diagram of a matched filter using an AD converter. Reference numeral 51 denotes a delay device in which a spread signal and a dump (reset) signal of integration are continuously stored, and a spread signal stored in internal registers 511-1 to 511-M for each chip interval Next register 511-2
Move to 511-1. Then, the spread signal is multiplied by the analog reception signal by the multipliers 52-1 to 52-M, and becomes the input group of the PR-AD converter 53 in FIG. 5
31-1 to 531-M, 532, 533, 534, 53
5, 536 are blocks 21-1 to 21- of FIG.
M, register bank 22, AD converter 24, adder 2
5, has the same function as the analog bus 26 and the digital bus 27. As a result, the integrator in each delta-sigma modulator despreads the spread signal and the analog received signal, which are offset by one chip interval, and integrates the despread value over one symbol interval. The number M of blocks and the like is obtained by converting the number C of chip sections in one symbol section (that is, the number of taps of the matched filter is C) and the dump time of the integrator in the PR-AD converter 53 into the number of chip sections. A value (M = C + D + 1) is obtained by adding the value D and 1. This plus 1
Is necessary for operating the delta-sigma modulator in one chip section with the input being 0 after integration in order to obtain an accurate residual voltage of the integrator. It should be noted that the delta-sigma modulator with 0 input has only the integration operation, and the subsequent comparison processing of the integration result is unnecessary. Instead, the residual voltage as the integration result is input to the AD converter 533 through the analog bus 535, while the counter output is stored in one register in the register bank 532 through the digital bus 536. This series of processing with 0 input is also treated as a dump section. Therefore, the number of dump signals is also incremented by 1. If the integration process with 0 inputs and the storage process of the residual voltage and the counter output cannot be processed in one chip section, the number of blocks M is not plus 1, but the actual number of chip sections must be added. I have to. In the block consisting of the sigma-delta modulator and the counter, which receive the output of the register in which the integrated dump signal is stored in the registers 511-1 to 511-M, first, the input is set to 0 and the delta-sigma modulator is set to 1 chip. After the section operation, the internal reset is performed in the D chip section. That is,
At a certain point in time, among the M sigma-delta modulators, C performs integration processing, one performs residual voltage calculation processing, and the remaining D performs dump processing. In addition, each sigma-delta modulator calculates the correlation between the analog received signal and the spread signal over the C-chip period, then performs the process of obtaining the residual voltage in the 1-chip period, and further performs the dump process over the D-chip period in total M. The processing of the chip section is continuously repeated. The AD converter 533 of the PR-AD converter 53 is a product having a conversion time within one chip section or a pipeline AD converter. By doing so, the sample and hold bank 23 of FIG. 2 becomes unnecessary, so it is omitted in FIG. The block that has performed the process of obtaining the residual voltage outputs the integration result (digital integration data and residual voltage of integration). AD
The converter 533 receives the residual voltage for each chip, and AD
The conversion is performed and the conversion result is output for each chip. In the case of the pipeline type AD converter, several chip intervals are required until the AD conversion is actually completed. During that time, the integration data corresponding to the residual voltage is stored in the register bank 532, and the AD of the residual voltage is added by the adder 534. The conversion result is weighted and added. In this way, the data added for each chip is output from the adder 534, and this becomes the matched filter output. That is, each block can output the integrated data without interruption from the matched filter output while performing the processing for obtaining the accurate residual voltage and the dump processing by the integration operation with 0 input. According to this, only one AD converter for the residual voltage is required in the PR-AD converter 53, and the AD converter 533 continues to operate efficiently (continuously). That is, as compared with the case where the conventional PR-AD converter is applied to the matched filter, the AD converter for the residual voltage can be largely removed, so that the circuit scale can be reduced. When the PR-AD converter is applied to the complex matched filter, it is necessary to handle the two-component data of I and Q within one chip section, so the conversion time of the AD converter 533 is apparently 1 As the / 2 chip section, the sample hold bank 23 of FIG. 2 is also required for simultaneously storing the residual voltages of the I and Q2 components. In this matched filter, when a 2-bit output delta sigma modulator is used, PR- of FIG.
The PR-AD converter of FIG. 4 can be applied instead of the AD converter. Thereby, the adder 534 can be omitted.

Next, the DLL synchronization tracking circuit is provided with the PR of the present invention.
Consider applying an AD converter. This is shown in FIG. A spread signal generator 61 outputs a spread signal earlier than the reference synchronization by a 1/2 chip period. This spread signal is further delayed by the 1/2 chip delay registers 62 and 63, the output of the register 62 is the same as the reference synchronization, and the output of the register 63 is the spread signal sent in the 1/2 chip section of the reference synchronization. Is output. The spread signals having these three types of delays are respectively multiplied by the multipliers 64-1 to 64-3 to obtain the product of the analog received signal, and become the input group of the PR-AD converter 65 of FIG. The PR-AD converter 65 has 3
Block 6 consisting of delta sigma modulators and counters
There are 51-1 to 651-3. Block 651-1
The product of the spread signal and the received signal, which is 1/2 faster than the reference synchronization, is input to. This block 651-1 is called an Early section. The product of the reference synchronization spread signal and the received signal is input to the block 651-2. This block 651-2
Is called a Punctual part. The product of the spread signal and the received signal which is ½ slower than the reference synchronization is input to the block 651-3. This block 651-3 is called a Late section. Reference numeral 66 denotes a loop filter, which receives the AD result of the Early block 651-1 and the AD result of the Late block 651-3 among the outputs of the PR-AD converter 65 and smoothes the difference between the absolute values of these inputs. The synchronization tracking is performed by adjusting the clock of the spread signal generator 61 in accordance with the size. Punctual block 651
The AD result of -2 is sent to a data demodulation unit (not shown). 652, 653, 654, 655, 656, 65
Reference numerals 7 and 7 respectively have the same functions as the shift register bank 22, the sample hold bank 23, the AD converter 24, the adder 25, the analog bus 26, and the digital bus 27 of the PR-AD converter of FIG. However, the AD converter 654 is different in the input range of the AD converter 24 in FIG. This will be described later.

A problem with this synchronization tracking circuit is that each block 651-1 to 651-3 must perform the dump of the integrator and an accurate residual voltage while performing periodic integration without interruption. That is not the case. Since the number of integrators is originally small, it is impossible to add a delta-sigma modulator like the matched filter. Therefore, the AD converter 654 for the residual voltage will deal with it. A specific description will be given with reference to FIG. 7. FIG. 7 shows the processing state in the delta sigma modulator of each of the blocks 651-1 to 651-3 with the horizontal axis representing time. "Integral"
Indicates that the integrator in the delta-sigma modulator is performing the integration calculation, and "comparison" indicates that the comparison process by the comparator and the counting process of the counter receiving the comparison result are performed. “Dump” indicates that the residual voltage of the integrator is stored in the sample hold bank 653, the integral data in the counter is stored in the register bank 652, and further, each unit in the delta sigma modulator and the counter are reset. . Let C be the number of chip sections in one symbol section. Then, "integration" and "comparison" or "integration" and "dump" are performed within one chip section. Since the dump processing cannot be performed over a few chip sections like the matched filter described above, the integrator must have a configuration capable of high-speed dump. Although “integration”, “comparison”, and “dump” have the same processing time (½ chip section) in the figure for convenience, they are not limited. At time t0, the Early block 651-1 starts integration. Then, from the time t1 when the 1/2 chip section has been sent, Punct
From the time t2 when the ual block 651-2 is further sent to the 1/2 chip section, the Late block 651-3 starts integration. Then, at time t3, which is a C-1 chip section from time t0, the Early block 651-1 performs integration of the C sample. Then, the "dump" process is performed at time t4 when a 1/2 chip section has passed. At this time, since the comparison process for the integration of the C sample is not performed, the counter content is the integration data of C-1 sample, and the 2-bit delta sigma modulator of FIG. 1 is applied to the delta sigma modulator of FIG. If the input of this modulator is 2ref
_- When ~2ref _+, residual voltage of the integrator at time t4,
It is in the range of 3ref _-to 3ref ₊ . Therefore, the AD converter 654
Input conversion range in the 3Ref _- a ~3ref _+, ref conventional AD converter 24 _- Use those expanded 3 times than ~ref _+.
As a result, the counter data corresponding to the comparison result of the C sample and the residual voltage of the integrator subtracting the comparison result appear as digital values at the output of the AD converter 654. This digital data is added by the adder 655 with the integrated data of C-1 samples to obtain the AD of the integration of C samples.
The converted value is obtained. In order for the AD converter 654 to maintain the conventional bit precision (N2), the conventional bit precision is set to 1
It is necessary to increase the bits, that is, N2 + 1.
Even when a 1-bit delta sigma modulator is used as the AD converter 654, like the 2-bit delta sigma modulator,
The range in which the residual voltage of the integrator after 0 input can be obtained, not the range in which the residual voltage of the integrator can be obtained without 0 input is set as the input range of the AD converter 654.

At time t5, the Early block 651-1 again integrates a new symbol section. Also, the Punctual block 651-2, L
Also in the ate block 651-3, times t4 and t
5 at time t3 in the Early block 651-1.
In the same manner as in the case of, the C-th sample integration and the dump processing are performed subsequently. The AD converter 654 is provided in each block 651-
The residual voltages of 1 to 651-3 are AD-converted, but since the three residual voltages are AD-converted within one symbol period, the AD converter 654 can use an object having a slow conversion speed. Can be reduced. Also,
In FIG. 6, the thing of FIG. 2 was applied as the PR-AD converter, but since the three residual voltages are continuously output during the 1.5 chip section, the conversion time of the AD converter 654 can be delayed, The PR-AD converter of FIG. 3 having a structure having a sample hold circuit and a counter output register inside a block composed of a sigma delta modulator and a counter is also applicable. The PR-AD converter 65 used in FIG. 6 is used.
Can also be used in the matched filter of FIG.
In this case, each block does not require a process for obtaining an accurate residual voltage due to the integration operation with 0 input, and therefore the number M of blocks used for the matched filter may be C + D and can be reduced by 1. Further, if the dump processing and the integration processing can be combined within one chip interval, M = C can be set. The PR-AD converter 6 used in FIG.
In the matched filter using 5, the sample hold bank 653 can be omitted like the PR-AD converter 53 in FIG.

Counters 212-1 to 212-M in FIG.
When the up-down counter is used as the counters 312-1 to 312-M in FIG. 3, the counters in the blocks 531-1 to 531-M in FIG. 5, and the counters in the blocks 651-1 to 651-3 in FIG. If a synchronous counter is used as this counter, an adder / subtractor must be provided inside the counter, so that the circuit scale becomes large if the number of counters is large. Therefore, there is a method in which two asynchronous one-way counters are used as one up / down counter, each counter performs up-counting and down-counting, and the count content is subtracted by a subtractor or an adder. The difference between subtractor and adder depends on the directionality of the two counters. That is, if the two counters are both up counters or down counters, a subtracter is used, and if one of the two counters is an up counter and the other is a down counter, an adder is used. If this subtractor or adder is used in common for multiple up / down counters,
The circuit scale can be reduced. If the function of this subtracter or adder is performed by the adder 25 of FIG. 2, the adder 33 of FIG. 3, the adder 534 of FIG. 5, and the adder 655 of FIG. 6, the circuit scale can be further reduced.

[0037]

As described above, in the PR-AD converter which is the AD converter with the integration function according to the present invention,
A / D conversion data of rough integration of counter output and its rough A
A of the residual voltage of the integrator showing the quantization error of D conversion data
Since the counter itself performs weighted addition with the D-converted data, it is not necessary to have an additional adder, and the circuit scale can be reduced.

Further, P corresponding to a plurality of input signals according to the present invention
In the R-AD converter, since the number of AD converters for the residual voltage corresponding to each signal is at least one, the conventional PR-AD converter can be used.
Unlike the converter, it is not necessary to provide an AD converter for each residual voltage, and the circuit scale can be greatly reduced.

Further, by adding the PR-AD converter of the present invention having a small circuit scale corresponding to a plurality of input signals by the time of 0 input integration processing and dump processing time, it can be applied to a matched filter. It can contribute to the reduction of the circuit scale of the filter itself and the output of accurate data.

Further, in the PR-AD converter of the present invention having a small circuit scale corresponding to a plurality of input signals, by performing AD conversion of the residual voltage without performing 0-input integration, the PR-
The integrator in the AD converter can perform periodic integration without interruption. Therefore, since this can be applied to the DLL synchronization tracking circuit and the integrator in the matched filter, it is possible to contribute to the reduction of the circuit scale of the DLL synchronization tracking circuit and the matched filter and the output of accurate data.

In the PR-AD converter for a plurality of input signals, the internal counter has an up / down counter of 2
In the case of one asynchronous one-way counter, the weighted adder can obtain the up / down count result from the contents of the two counters, so that an adder for separately obtaining the up / down result is not required and the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of an AD converter with an integration function according to claim 1 of the present invention.

FIG. 2 is a schematic configuration diagram showing an embodiment of an AD converter with an integration function for multiple input signals according to claim 2 of the present invention.

FIG. 3 is a schematic configuration showing an embodiment in which the number of data in the delta sigma modulator, the sample hold bank and the register bank of the AD converter with an integration function corresponding to a plurality of input signals according to claim 2 of the present invention is equal. It is a figure.

FIG. 4 is a schematic configuration diagram showing an embodiment of an AD converter with an integration function for multiple input signals according to claim 3 of the present invention.

FIG. 5 is a schematic configuration diagram showing an embodiment of an AD converter with an integration function for a plurality of input signals and a matched filter according to claim 5 of the invention.

FIG. 6 is a schematic configuration diagram showing an embodiment of an AD converter with an integration function for a plurality of input signals according to claim 7 of the present invention and a DLL synchronization tracking circuit of claim 7;

7 is a diagram showing the processing contents of the AD converter with an integration function of FIG. 6 in time series.

FIG. 8 is a schematic configuration diagram showing a conventional AD converter with an integration function.

FIG. 9 is a schematic configuration diagram of a comparator of a 2-bit delta sigma modulator.

FIG. 10 is a diagram showing a quantization characteristic of an AD converter.

[Explanation of symbols]

1, 211-1 to M, 311-1 to M, 411-1 to M
Delta sigma modulator 2, 412-1 to M up / down counter 3, 24, 32, 44, 533, 654 AD converter 11 subtractor 12 integrator 13, 91, 911, 912 comparator 14, 51 delay device 15 DA converter

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03M 3/00-11/00 H03M 1/14

Claims (8)

(57) [Claims] 1. A delta-sigma modulator that outputs a bit stream and a residual value after the end of the periodic integration from a result of periodic integration of an analog input signal, a counter that counts when the bit stream has a predetermined condition, and the bit stream. And an AD converter that AD-converts the residual value as a quantization error generated by outputting the counter. The counter changes the counter operation direction according to the output result of the AD converter, and the counter An AD converter with an integration function, wherein the digital output from the AD converter and the digital output from the AD converter are combined and output. 2. A block comprising a delta-sigma modulator which outputs a bit stream and a residual value after the end of the periodic integration from a result of the periodic integration of an analog input signal, and a counter which counts when the bit stream meets a predetermined condition. A plurality of sample hold groups for holding the residual value from each block, a register group for holding the count result from each block, an AD converter for AD converting the residual value of the sample and hold group, and the register An AD converter with an integration function, comprising: an adder for performing weighted addition of the digital output from the group and the corresponding digital output from the AD converter. 3. A block comprising a delta-sigma modulator for outputting a bit stream and a residual value after the end of the periodic integration from a result of the periodic integration of an analog input signal, and a counter for counting when the bit stream has a predetermined condition. A plurality of sample hold groups for holding the residual value from each block, a register group for holding the count result from each block, an AD converter for AD converting the residual value of the sample hold group, and each block And a comparator that determines the polarity of the residual value from the counter. The counter changes the operating direction of the counter according to the output result of the comparator, and the AD conversion corresponding to the digital output from the register group. An AD converter with an integration function, characterized in that the digital output from the converter is combined and output. 4. The AD converter with integral function according to claim 2 or 3, wherein the AD converter is a pipeline type. 5. The AD converter with an integration function according to claim 2, which is used for a matched filter for performing despreading in a spread spectrum receiver, wherein the analog input signal is a spectrum. An AD converter with an integration function, which is a product of a spread reception signal and a spread signal. Wherein said AD converter, the residual value of the status of not integrating the periodic integration end after 0 input of any one of claims 2-5, characterized in that the AD conversion AD converter with integration function. 7. The AD converter with an integrating function according to claim 6, which is used in a delay locked loop synchronization tracking circuit of a spread spectrum receiver, wherein the analog input signal is different from the spread spectrum received signal in several types. An AD converter with an integration function, which is a product of a phase spread signal. 8. The AD converter with an integration function according to claim 2, wherein the counter is an up-down counter including two asynchronous one-way counters.