JP3517839B2 - Programmable cell array circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable LSI whose processing contents can be changed by a program,
The present invention relates to a programmable cell array circuit that uses a lookup table as a constituent element of calculation and wiring.

[0002]

2. Description of the Related Art A field programmable gate array (FPGA) has been put into practical use as a technique for providing high-speed hardware with programmability equivalent to software processing. Most commercially available FPGAs use an SRAM for the part that performs logical operations. This is because, when an address line of a small-sized memory is used as an input signal, the data stored in the corresponding memory cell is directly output as a calculation result, and this small-sized memory is called a lookup table (LUT).

A commercially available FPGA includes the LUT as a constituent element of a logical operation, and other dedicated registers, a LUT and a programmable wiring element for connecting the input / output of the register and propagating a signal. As described above, the conventional FPGA is composed of a combination of various individual constituent elements, and in terms of the degree of integration of the LSI, the packaging density is inferior to that of the normal SRAM even though the memory technology is used. .

On the other hand, a technique for realizing all the constituent elements of a programmable logic circuit by using an LUT has been proposed, paying attention to increasing the density of the memory technology. For example, JP 2000-
In the rewritable logic circuit technology proposed in 49591, all components are realized by LUT.

FIG. 3 is a block diagram of a logic cell, which is the basic configuration described in the above publication, that is, a programmable cell. The programmable cell 11 shown in the figure has w, n, e,
It has a total of four adjacent cells, one for each of the four directions named s. For example, cell 11A in FIG.
It has four adjacent cells 1B, 11C, 11D and 11E.

The cell 11 has input signal lines Pwi ', Pni', for inputting signals from four adjacent cells.
Pei, 'Psi' and output signal lines Pwo ', Pno', Peo ', P for outputting signals to four adjacent cells.
has so '. Further, the cell 11 has four input signal lines P
LUT Mw ', Mn', Me ', M readdressed by the values of wi', Pni ', Pei', Psi '.
s ', of which the output of LUT Mw' is output signal line Pwo 'and the output of LUT Mn' is output signal line Pwo.
The output of LUT Me 'is the output signal line Peo'
Further, the output of the LUT Ms 'is output to the output signal line Pso'.

The input signal lines Pwi ', Pni', P
Any value can be stored in advance in the storage element of the address commonly addressed by ei 'and Psi', so that each LUT Mw ', Mn', Me ', Ms' inputs the same address value, It is possible to perform different operations. Each LUT Mw ', Mn', Me ', Ms'
Has 16 memory cells each, and one of the 16 memory cells is specified by the values of the input signal lines Pwi ', Pni', Pei ', and Psi' and stored in the corresponding memory cell. The output 0 or 1 data is converted into the output signal lines Pwo ′, Pno ′, Peo ′, Pso ′.
Output to.

[0008]

However, there is a problem in directly connecting to the adjacent logic cell as shown in FIG. 4 by the above-mentioned method. The problems will be described below. Generally, in SRAM, a value of 0 or 1 is stored in each memory cell immediately after the power of the LSI is turned on, but it is difficult to predict the value before the power is turned on. When the cells of FIG. 3 are connected as shown in FIG. 4 in such a state, a ring transmitter may be formed between adjacent cells depending on the value of the memory cell.

FIG. 5 shows an example in which two cells 11 of FIG. 3 are connected. Now, in the cell connection of FIG. 5 (a), the contents of each memory cell immediately after the power is turned on are the contents of the L cells of the first cell 11A.
FIG. 5 shows 16 memory cells of UT Me ′ 1.
(B) It is assumed that the 16 memory cells of the LUT Mw ′ 2 in the second cell 11B are as shown in FIG. 5 (c). In this case, Me ′ 1 is the input signal Pei of the cell 11A.
It functions as a connection from '1 to the output signal Peo' 1, while Mw'2 inverts the polarity of the input signal Pwi '2 of the cell 11B and outputs it as the output signal Pwo' 2. When the value is stored in the memory cell in this way, the two cells 11
The direct connection between A and 11B is logically as shown in FIG. 5 (d), and the ring transmitter is constructed at this point.

If the ring oscillator is configured when the power is turned on as described above, an oscillation phenomenon occurs at a high frequency, an excessive current flows through the LSI, which makes normal operation of the LSI difficult, or even destroys the LSI in some cases. There is a possibility. Also LU
There is a similar possibility even while the contents are sequentially written in each memory cell of T. In addition, an ordinary S for the purpose of storing and reading some data other than the circuit configuration information in each LUT of the above-described rewritable logic circuit.
Considering the use as a RAM, it is necessary to pay attention to the content of the data to be written so as not to configure the ring transmitter, and it is generally not possible to write arbitrary data.

The present invention has been made in view of the above circumstances, and prevents an oscillating operation during power-on and during writing to a memory cell, and allows the LSI to operate normally without flowing an excessive current. And at the same time S
An object of the present invention is to provide a programmable cell array circuit capable of storing arbitrary data in each LUT as a RAM.

[0012]

To achieve the above object, in a programmable cell array circuit according to the present invention,
Oscillation is prevented by controlling the connection or disconnection of each cell with a signal as appropriate without directly connecting the adjacent cells. In other words, the invention of claim 1 has a plurality of input lines and one
Built-in multiple lookup tables with output lines
Programmer that arranges and configures multiple programmable cells
A programmable cell in a bull cell array circuit
Between the output line of this programmable cell and the
Connection with a plurality of input lines of the programmable cell in contact
And an adjacent cell connection control circuit for disconnecting the
Write the data to the look-up table of the programmable cell
Disconnect the connection between the programmable cells while setting
Output an instruction signal to the adjacent cell connection control circuit and write
After completing the steps, the finger that connects the programmable cells
A memory control that outputs an indication signal to this adjacent cell connection control circuit.
And a control circuit. Invention of Claim 2
Is a lookup with multiple input lines and one output line
Multiple programmable cells with multiple built-in tables
In the programmable cell array circuit configured as
This programmer is provided between the programmable cells.
The output line of the bull cell and the adjacent programmable cell
Adjacent cells that connect to and disconnect from multiple input lines in
Connection control circuit and the programmable cell when power is turned on
The instruction signal for disconnecting the connection between
And a memory control circuit for outputting to a path
It

[0013]

In order to solve the above problems, a programmable cell array circuit according to the present invention is provided with a plurality of input lines and one input line.
In a programmable cell array circuit configured by arranging a plurality of programmable cells having a plurality of LUTs each having an output line, an adjacent cell connection control circuit for connecting / disconnecting connection lines of adjacent programmable cells adjacent to each other is provided between the programmable cells. The feature is that it is provided.

Further, the programmable cell array circuit of the present invention is provided with a memory control circuit for controlling adjacent programmable cells adjacent to each other, and this memory control circuit instructs the adjacent cell connection control circuit to perform connection / disconnection control. It is characterized by outputting a signal.

Further, in the programmable cell array circuit of the present invention, the memory control circuit is a programmable cell L
An instruction signal for disconnecting the connection line between the programmable cells is output to the adjacent cell connection control circuit while writing data to the UT, and an instruction signal for connecting the connection line between the programmable cells is output to the adjacent cell connection control circuit when writing is completed. It is characterized by

Further, the programmable cell array circuit of the present invention is characterized in that the memory control circuit always outputs an instruction signal for disconnecting the connection line between the programmable cells to the adjacent cell connection control circuit.

Further, in the programmable cell array circuit of the present invention, the memory control circuit issues an instruction signal for disconnecting the connection line between the programmable cells while the data is being written to the LUT of the programmable cell, depending on the use state of the programmable cell array. Outputs to the connection control circuit, outputs the instruction signal to connect the connection line between programmable cells to the adjacent cell connection control circuit when writing is completed, and always outputs the instruction signal to disconnect the connection line between programmable cells to the adjacent cell connection control It is characterized by outputting to the circuit.

Further, the programmable cell array circuit of the present invention is characterized in that the memory control circuit outputs an instruction signal for disconnecting the connection line between the programmable cells to the adjacent cell connection control circuit when the power is turned on.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a basic configuration of a programmable cell array circuit according to an embodiment of the present invention, and FIG. 2 is a diagram arranging a plurality of programmable cells in a two-dimensional array. FIG. 1 shows the structure of two adjacent programmable cells 1A and 1B and a memory control circuit 3 for controlling the programmable cells 1A and 1B. The programmable cells 1A and 1B have the same structure, and the internal structure of the programmable cell 1A will be described below.

The programmable cell 1A shown in FIG.
It has a total of four adjacent cells, one for each of the four directions labeled w, n, e, and s. For example, the programmable cell 1A in FIG. 2 has four adjacent cells, cells 1B, 1C, 1D and 1E. And the programmable cell 1A
Are four 4-input 1-output LUTs Mw1, Mn1, M
e1 and Ms1. Each LUT Mw1, Mn1, Me
1 and Ms1 each consist of 16 1-bit memory cells. For each of these memory cells, there are circuits for one system of write control and two systems of read control. That is, the read circuit used differs depending on whether each memory cell is used as a logic circuit formed of a LUT network or as a normal SRAM.

First, the control of writing data to each memory cell will be described. In this case, the memory write line 5A is output to the memory cell at the address specified by the SRAM address line 7A which is the output signal from the memory control circuit 3.
And the contents are written from the memory control circuit 3 to each cell.

Next, read control when each memory cell is used as a logic circuit composed of an LUT network will be described. As a circuit inside the programmable cell 1A used at this time, input signal lines Pwi1, Pni1, and Pei for inputting signals from four adjacent cells are used.
1, Psi1 and output signal lines Pwo1, Pno1, Peo1, Pso1 for outputting signals to four adjacent cells. Each LUT Mw1, Mn1, Me1, Ms1 is 4
Two input signal lines Pwi1, Pni1, Pei1, Psi
The values commonly addressed by a value of 1 and stored in corresponding memory cells within each LUT are read in parallel. The output of the LUT Mw1 is the output signal line Pw.
The output of the LUT Mn1 is the output signal line Pno1
The output of the LUT Me1 is output to the output signal line Peo1 at L level.
The output of the UT Ms1 is output to the output signal line Pso1.

Any value can be stored in advance in the memory cell inside each LUT by the write function described above.
Therefore, each LUT Mw1, Mn1, Me1, Ms1 can perform different operations while inputting the same address value. Each LUT Mw1, Mn1, Me1, M
The combinations of logical operations that can be executed by s1 are all arbitrary combinational logical operations of 4 inputs or less, and the number of them is 2 16 powers, that is, 65536 ways.

Next, the read control when each memory cell is used as a normal SRAM will be described. In this case, the data 0 or 1 stored in the memory cell at the address designated by the SRAM address line 7A, which is the output signal from the memory control circuit 3, is the memory read line 6A.
Is transmitted and the contents are read out to the memory control circuit 3.

Next, the two programmable cells 1A shown in FIG.
The connection between the and 1B will be described. The output signal Peo1 from the programmable cell 1A in the e direction is not directly input to the programmable cell 1B but is input to the adjacent cell connection control circuit 2A. This adjacent cell connection control circuit 2A
Then, depending on the content of the adjacent cell connection control signal 4 output from the memory control circuit 3, Peo1 is directly propagated to the input signal Pwi2 in the w direction of the programmable cell 1B, or the connection is disconnected and Pwi2 is fixed to 0. Whether to do is selected.

Similarly, the output signal Pwo2 from the programmable cell 1B in the w direction is directly fed to the programmable cell 1
It is not input to A but is input to the adjacent cell connection control circuit 2B. In the adjacent cell connection control circuit 2B, depending on the content of the adjacent cell connection control signal 4 output from the memory control circuit 3, Pwo2 is propagated as it is to the input signal Pei1 in the e direction of the programmable cell 1A, or the connection is made. It is selected whether to separate and fix Pei1 to 0.
To realize the adjacent cell connection control circuits 2A and 2B,
For example, by using one AND gate, the above operation can be performed.

Next, in the memory control circuit 3, each memory cell inside each programmable cell is used as a logic circuit composed of an LUT network, or a normal SR is used.
Whether to use as an AM is set from the outside in advance, and the state is always held internally. Further, the timing of writing the memory data to each programmable cell is managed, and when the memory data is written, the adjacent cell connection control signal 4 is set to 0 to disconnect each programmable cell. Note that the disconnection at the time of writing may be performed only between cells adjacent to the cell to be written or between all cells. Similarly, the connection control signal 4 is set to 0 when the power is turned on. Furthermore, the connection control signal 4 is set to 0 when each LUT is used as a normal SRAM.

On the other hand, after the memory data is written in each programmable cell, when each programmable cell is used as a logic circuit, the connection control signal 4 is set to 1,
Connect between adjacent programmable cells. In this way, by inserting a simple logic circuit such as an AND gate between adjacent programmable cells, each programmable cell can be replaced by another programmable cell when the operation of the LSI is unstable, such as when the power is turned on. Therefore, no oscillation phenomenon occurs even if any value is assigned to each memory cell.

[0029]

As described above, in the programmable cell array circuit according to the present invention, the memory cells are protected against the memory cells at the time of power-on of the system without degrading various advantages of the circuit composed of the programmable cell array characterized by the uniform structure. It is possible to prevent the ring transmitter from being generated in a state such as at the time of writing and to guarantee a stable operation, and it is also possible to use each LUT as a normal SRAM for storing arbitrary data.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of a programmable cell array circuit according to an embodiment of the present invention.

FIG. 2 is a diagram in which a plurality of programmable cells in FIG. 1 are arranged in a two-dimensional form.

FIG. 3 is a block diagram of a programmable cell in a conventional example.

FIG. 4 is a diagram in which a plurality of programmable cells in FIG. 3 are arranged in a two-dimensional form.

5 (a) to 5 (d) are diagrams showing an example of cell contents and a logic circuit to be realized in connection of a conventional programmable cell.

[Explanation of symbols]

1,1A-E Programmable cell 2A, B Adjacent cell connection control circuit 3 Memory control circuit 4 Connection control signal 5A, B memory write line 6A, B memory read line 7A, B SRAM address line 11, 11A-E programmable cell

   ─────────────────────────────────────────────────── ─── Continued front page       (56) References Japanese Patent Laid-Open No. 10-4345 (JP, A)                 JP 2000-49591 (JP, A)                 JP-A-2000-232162 (JP, A)                 JP 2000-36738 (JP, A)

Claims (2)

(57) [Claims] 1. A programmable cell array circuit configured by arranging a plurality of programmable cells having a plurality of look-up tables each having a plurality of input lines and one output line, the programmable cell array circuit being provided between the programmable cells.
The output line of the bull cell and the adjacent programmable cell
Adjacent cells that connect to and disconnect from multiple input lines in
Data is stored in the connection control circuit and the look-up table of the programmable cell.
Disconnect the connection between the programmable cells while writing
Output a separation instruction signal to the adjacent cell connection control circuit,
When programming is completed, connect the programmable cells
Output to the adjacent cell connection control circuit.
And a memory control circuit . 2. A rule having a plurality of input lines and one output line.
Programmable cell with multiple built-in backup tables
Programmable cell array circuit configured by arranging a plurality of cells
In this programmer, which is provided between the programmable cells,
The output line of the bull cell and the adjacent programmable cell
Adjacent cells that connect to and disconnect from multiple input lines in
Disconnect the connection between the connection control circuit and the programmable cell when the power is turned on.
To output an instruction signal to the adjacent cell connection control circuit
And a re-control circuit .