JP3520175B2 - Analog multiplier - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog multiplier, which is a base for performing analog signal processing in a MOS semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, with the increase in digital equipment and the progress of digital signal processing technology, C suitable for digital signal processing has been developed.
MOS integrated circuits are occupying most of the semiconductor market. However, since the input and output signals of video and audio are analog, it is easier to process them in analog, and even in the case of digital processing, A / D, D / A conversion, filter processing before and after that, and clock generation are performed. An analog circuit is required for the oscillator.

Bipolar is suitable for analog circuits, and CMOS has been unsuitable except for some circuits such as analog switches and sample hold. However, the cost of bipolar and BiCMOS processes is rather high, and CMOS-based digital / analog mixed mounting
There is a strong demand for chipping, and circuit development for performing analog signal processing in CMOS has become active.

There is an "analog multiplier" as an important function which is frequently used in analog signal processing and has a great influence on the total performance. In bipolar, there is a convenient combinational transistor circuit called "double balance circuit". In many cases, this is used to configure an analog multiplier, which is used in a mixer circuit and a phase detector. However, when an analog multiplier is made of CMOS, there is a problem that a circuit in which bipolar is simply replaced by CMOS or a modified circuit thereof always causes large harmonic distortion and intermodulation distortion. This is because the CMOS device has essentially square characteristics in the saturation region (pinch-off region) normally used in analog circuits, and the transconductance (Gm) of the device is much lower than that of the bipolar device. This is because "linearization by resistance" is difficult.

Therefore, a circuit configuration shown in FIG. 13 is known as a method of constructing an analog multiplier in CMOS. This circuit consists of MOS transistors M1, M2, M3,
This is a combinational transistor circuit composed of four M4 CMOS elements, and the source of each transistor is a constant voltage point V
connected to s. The sum signal "Vx + Vy" of the two inputs is input to the transistor M2, and the inverted signal "-Vx-Vy" of the sum of the two inputs is input to the transistor M3. Connect the drains of these transistors to the first
Output current Io1. The difference signal "Vx-Vy" between the two inputs is input to the transistor M4, and the inverted signal "-Vx + Vy" between the two inputs is input to the MOS transistor M1.
Respectively. The drains of these transistors are connected to produce a second output current Io2.

In calculating the circuit operation, it is assumed that all MOS transistors are operating in the saturation region (pinch-off region), and the short channel effect is not considered for simplicity. It is also assumed that the four inputs to each MOS transistor have the same DC voltage VB. At this time, the characteristics of each MOS transistor can be expressed as I = (k / 2) (VGS-Vth) ² using k and Vth which are main parameters. Where k is W, gate length is L, gate capacitance is Cox, and channel carrier mobility is μ.
Cox W / L ”is a constant. According to this descriptive formula, the operation of each MOS transistor of M1 to M4 can be expressed as follows.

M1: I11 = (k / 2) (− Vx + Vy + VB−Vs−Vth) ² (1) M2: I12 = (k / 2) (Vx + Vy + VB−Vs−Vth) ² (2) M3: I21 = (k / 2) (-Vx-Vy + VB-Vs-Vth) ² ... (3) M4: I22 = (k / 2) (Vx-Vy + VB-Vs-Vth) ² ... (4) Here Then, when the output current Io1-Io2 is calculated, Io1-Io2 = (I12 + I21)-(I11 + I22) = (I12-I22)-(I11-I21) = 2 kVy (Vx + VB-Vs-Vth) -2kVy (-Vx + VB −Vs−Vth) = 4 kVx Vy (5) As is clear from the equation (5), when the difference current Io1−Io2 is output, this current is proportional to the product of the two input signals Vx and Vy, and the analog output is obtained. Become. If a resistor is connected between each output terminal of FIG. 13 and, for example, Vcc, a voltage output proportional to the product of two input signals Vx and Vy can be obtained between the output terminals. Thus, the circuit of FIG. 13 operates as an analog operation cell by the four CMOS elements.

However, in practice, the input of this circuit requires an adder circuit which is a combination of two input signals and its inverted signal. Actually, it is difficult to realize such an adder circuit in CMOS. For example, an adding circuit by resistance division as shown in FIG. 14 is conceivable. However, this adds a second-order distortion to the addition output due to the square characteristic of the elements of the CMOS transistors M5 to M8 themselves. This is because, as described above, the transconductance (Gm) of the element is much lower than that of the bipolar device, which makes it difficult to perform the "linearization by resistance" which is popular in the bipolar device.

The CMOS transistors M5 to M8 shown in FIG.
There is also a method of using a circuit in which a CMOS operational amplifier is connected as a voltage follower instead of, but this can be used only at a low frequency due to the limitation of the frequency band of the CMOS operational amplifier, and in a video band or an intermediate frequency (IF) band. After all, it is not practical because it is accompanied by problems such as strain generation and amplitude reduction. Another problem is that the use of operational amplifiers increases the number of elements and increases the circuit scale.

[0010]

As described above, conventionally, if an analog multiplier is realized only by CMOS, a large distortion or intermodulation distortion is always generated, and the signal quality is remarkably deteriorated. It was inevitable.

An object of the present invention is to provide a wideband analog multiplier suitable for a mixer in a video band or an intermediate frequency band, phase detection, etc. without causing distortion or intermodulation distortion, and to provide a small scale CMO.
It is to provide in S circuit.

[0012]

According to the present invention, in order to solve the above-mentioned problems, the first and second inputs are differential signals composed of a positive electrode signal and a negative electrode signal having mutually inverted phases. , A first field-effect transistor connected to the source ground and a second field-effect transistor connected to the drain ground. The drain current of the first field-effect transistor is supplied to the source of the second field-effect transistor. A gate of the first field effect transistor is used as a first input terminal, and a gate of the second field effect transistor is used as a second input terminal. A first input terminal of the first adder circuit and a first input of the third adder circuit. Enter a positive signal of the first input to the child, the first of said input terminal 4 of the second adder circuit
The negative signal of the first input is input to the first input terminal of the adder circuit, and the second input terminal of the first adder circuit and the second input terminal of the second adder circuit are connected to the second input terminal of the second adder circuit. The positive signal of the input is input, the negative signal of the second input is input to the second input terminal of the third adding circuit and the second input terminal of the fourth adding circuit, and the first adding signal is input. The output signal of the circuit is applied between the gate and the source of the third field effect transistor, the output signal of the second addition circuit is applied between the gate and the source of the fourth field effect transistor, and the output signal of the third addition circuit is applied. The output signal is applied between the gate and the source of the fifth field effect transistor, and the output signal of the fourth adding circuit is applied between the gate and the source of the sixth field effect transistor, and as a result, the output signal of the third field effect transistor is applied. Drain current and sixth field effect transistor Of the drain current of the fourth field effect transistor and the sum of the drain current of the fourth field effect transistor and the drain current of the fifth field effect transistor, or a differential voltage proportional to this difference current is output. And

Further, the first and second inputs are differential signals composed of a positive electrode signal and a negative electrode signal having mutually inverted phases, and a first input terminal and a second input terminal are provided. A fourth addition circuit is provided, and the positive signal of the first input is input to the first input terminal of the first addition circuit and the first input terminal of the third addition circuit, The negative signal of the first input is input to the first input terminal of the second adder circuit and the first input terminal of the fourth adder circuit, and the second input signal of the first adder circuit is input. The positive signal of the second input is input to the input terminal and the second input terminal of the second adder circuit, and the second signal of the third adder circuit is input.
Input terminal and the second input terminal of the fourth adding circuit, the negative signal of the second input is input, and the output signal of the first adding circuit is input to the gate source of the third field effect transistor. And an output signal of the second adder circuit is applied between the gate and source of the fourth field effect transistor, and an output signal of the third adder circuit is applied between the gate and source of the fifth field effect transistor. And the output signal of the fourth adder circuit is applied between the gate and source of the sixth field effect transistor, and from the sum of the drain currents of the third and sixth field effect transistors, A current obtained by subtracting twice the average current of the drain currents of the third to sixth field effect transistors is taken as the first current output, and the current of the fourth and fifth field effect transistors is The current obtained by subtracting twice the current average current of each of the drain current of the field effect transistor from the sum of the drain currents of respectively up to the third to sixth second
Of the first and second current outputs or a difference voltage proportional to this difference current is output.

Further, the first input is a differential signal composed of a positive electrode signal and a negative electrode signal whose phases are inverse to each other, and the second input is a positive signal and a negative electrode signal whose phases are inverse to each other. The first and second adder circuits having a first input terminal and a second input terminal, and the first input terminal of the first adder circuit has the first and second adder circuits. The positive signal of the input is input, the negative signal of the first input is input to the first input terminal of the second adding circuit, and the second input terminal of the first adding circuit and the second input terminal of the first adding circuit are input. The positive signal or the negative signal of the second input is input to the second input terminal of the second adder circuit, and the negative signal of the first input is applied between the gate and source of the third field effect transistor, The positive signal of the first input is applied to the gate of the fourth field effect transistor. Applied between sources, the output signal of the first addition circuit is applied between the gate and source of the fifth field effect transistor, and the output signal of the second addition circuit is applied between gate and source of the sixth field effect transistor. A current obtained by subtracting twice the average current of the drain currents of the third to sixth field effect transistors from the sum of the drain currents of the third and sixth field effect transistors. As the first current output, and subtracting twice the average current of the drain currents of the third to sixth field effect transistors from the sum of the drain currents of the fourth and fifth field effect transistors. The second current output as the second current output and a means for outputting the difference current between the first current output and the second current output or the difference voltage proportional to the difference current. The features.

By using the above-mentioned four sets or two sets of adder circuits, it is possible to obtain four addition / subtraction signals without distortion by a combination of two input signals necessary for analog multiplication using CMOS and its inverted signal. You can This constitutes a source-grounded amplifier for the first input signal by the first field effect transistor forming the adder circuit, and the squared current converted by the squared characteristic of the MOS element is
This is because when the source terminal of the second field-effect transistor on the load side receives the voltage, the first input signal is extracted in a route-compressed form as a voltage due to the square characteristic of the MOS element. Since the second field effect transistor is drain-grounded here, the second input signal applied to its gate is directly output to the source terminal.

Therefore, as a result, the difference between the first input signal and the second input signal can be taken out without distortion at the source terminal of the second field effect transistor. Four or two such adder circuits are prepared, four adder / subtractor signals are created by combining two input signals and their inverted signals, and the four adder / subtractor signals are input to the conventional combinational circuit of four MOS transistors. An ideal analog multiplication result can be output from the drain end.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. Before describing the embodiments of the present invention, an adder circuit 11 of an analog multiplier according to the present invention will be described with reference to FIG. This circuit is composed of four sets of identical circuits having different inputs, and each circuit performs addition of two inputs. Each unit circuit is composed of the same conductive first and second MOS transistors. Here, an example constituted by NMOS type transistors is shown. The diagram on the right side shows the circuit diagram on the left side as a block diagram.

The source of the first MOS transistor is connected to the ground GND, the drain of the second MOS transistor is connected to the power source Vcc, the drain of the first MOS transistor is connected to the source of the second MOS transistor, This terminal is used as an addition output, and the addition input is input to the gate of each MOS transistor. The first of these unit circuits
The output signal is calculated for the first adder circuit having the MOS transistor M5 and the second MOS transistor M9.

As a precondition for calculating the circuit operation, it is assumed that the MOS transistors M5 and M9 have the same shape and that they all operate in the saturation region (pinch-off region). For simplicity, the short channel effect is not considered. The input signals are a pair of differential signals having mutually opposite phases, and the two input signal components (AC components) are represented as (Vx, -Vx) and (Vy, -Vy), respectively. The DC components of the input signal are VBx and V, respectively
Suppose By. The characteristics of the MOS transistor can be expressed as I = (k / 2) (VGS-Vth) ² by using the values of k and Vth which are main parameters. Here, k is a constant represented by “μCoxW / L” where W is the gate width, L is the gate length, Cox is the gate capacitance, and μ is the carrier mobility of the channel. Using this description formula, the operation of each MOS transistor of M5 and M9 can be described as follows.

M5: I5 = (k / 2) (Vx + VBx-Vth) ² ... (6) M9: I9 = (k / 2) (Vy + VBy-Vout-Vth) ² ... (7) Here, obviously Since I5 = I9, from (6) and (7), (Vx + VBx-Vth) = (Vy + VBy-Vout-Vth) Vout = -Vx + Vy + (VBy-VBx) (8). Since the parentheses in the equation (8) are the DC term, the output signal component is "-Vx + Vy". This is the reverse of the input of the MOS transistor M5 and the MOS transistor M9.
The result is that the input of and is added. As is clear from this equation, no distortion occurs in this adder circuit. It should be noted that this circuit is strictly "subtracting" two signals, but in the sense that the two signals are added together, they will be hereinafter collectively referred to as "adding circuit" for the sake of convenience. It is meant to include "subtraction" as an actual operation.

Similarly, the first MO of each unit circuit is
The S transistor is M6, and the second MOS transistor is M
In the second adding circuit composed of 10, the output signal component is "Vx
+ Vy ", the first MOS transistor is M7, the second M is
In the third addition circuit in which the OS transistor is composed of M11, the output signal is "-Vx-Vy", and in the fourth addition circuit where the first MOS transistor is composed of M8 and the second MOS transistor is composed of M12. Signal is "Vx-Vy"
Becomes As described above, by using the circuit including the four sets of unit adders shown in FIG. 1, the four addition / subtraction signals obtained by combining the two input signals necessary for analog multiplication using CMOS and the inverted signals thereof are undistorted. Can be obtained at

FIG. 2 shows the addition circuit 11 described in FIG.
FIG. 14 is a circuit diagram for explaining a first embodiment of the present invention in which an analog multiplier is configured by applying the basic circuit of FIG. 13.

In this embodiment, four addition / subtraction signals based on two input differential signals necessary as inputs to the basic circuit of FIG. 13 are generated by the adder circuit 11 of FIG. It is designed to be input. As described above, the adder circuit 11 can generate the addition / subtraction signals necessary for the basic circuit of FIG.
Equations (1) to (4) hold for the MOS transistor of 4, and the current output proportional to the product of two input signal voltages is obtained as Io1-Io2 of the output current is expressed by Equation (5). Become.

FIG. 3 is a circuit diagram for explaining the second embodiment of the present invention. In the embodiment of FIG. 2, the basic differential transistor is composed of an NMOS, but in this embodiment, the power supply Vcc is replaced with ground GND, GND is replaced with Vcc, and NMOS is replaced with PMOS in this embodiment. Is. In this way, it is possible to configure an analog multiplier that operates exactly the same even when replaced. The operation is exactly the same as in FIG.

Next, a third embodiment of the present invention will be described with reference to FIG. In the embodiment of FIG. 2, the addition / subtraction signal of the two input differential signals, which is the output of the adder circuit 11, is added to the gates of the four MOS transistors M1 to M4 which are the center of the arithmetic operation. By the way, as is apparent from the equations (1) to (4), the addition / subtraction signal is added so as to change the gate-source voltages of the four MOS transistors, thereby performing the operation of analog multiplication. In the example of FIG. 2, since the sources of these MOS transistors are connected to the ground GND, analog multiplication is realized by adding them to the gate.

In this embodiment, the gates of four MOS transistors are connected to a common reference potential, and each addition / subtraction output is supplied to the source of each MOS transistor to realize the function of analog multiplication. It can be easily understood that the operation of this embodiment is completely the same as that of the embodiment of FIG.

FIG. 5 shows a fourth embodiment of the present invention in which the analog multiplier shown in FIG. 2 is used as a phase detector. In phase detection, it is usual to take the difference between the current outputs of the analog multipliers of FIG. 2 and make a single output. For this purpose, one of the current outputs (Io2 in this example) is folded back by the current mirror and added to the other current output (Io1 in this example) to obtain the difference current Iout.

FIG. 6 shows a fifth embodiment in which the analog multiplier of FIG. 2 is used as a mixer or a frequency converter. In these applications, since the output is taken out as a voltage, load resistances R1 and R2 are attached to the output end of the circuit of FIG.

Although the above description is based on the assumption that the four outputs from each adder circuit have the same amplitude, the output from each adder circuit may actually have slightly different amplitudes. I don't care. Strictly speaking, if the amplitudes of Vy are all equal at the outputs of the four adder circuits, the amplitudes of Vx are equal at the first adder circuit and the third adder circuit, and equal at the second adder circuit and the fourth adder circuit, , Vx has different amplitudes in the former and the latter, the output amplitude after multiplication changes, but non-ideal components (distortion or intermodulation) do not occur in the multiplication result.

Similarly, if the amplitudes of Vx are all the same, the amplitudes of Vy are the same in the first adder circuit and the second adder circuit, and are the same in the third adder circuit and the fourth adder circuit, the amplitude of Vy is the same as the former. Even if the latter is different, the output amplitude after multiplication changes, but the non-ideal component (distortion or intermodulation) does not occur in the multiplication result. This can be easily proved by calculating Vx or Vy by multiplying the coefficient according to the above condition in the calculation using the above equations (1) to (4).

Therefore, when the amplitudes of Vy are all equal, Vx
The output amplitude is halved even if the amplitude of is either 0 in the first adder circuit and the third adder circuit or 0 in the second adder circuit and the fourth adder circuit. Therefore, there is no problem in the analog multiplication operation. Similarly, when the amplitudes of Vx are all equal, the amplitude of Vy is 0 in the first adder circuit and the second adder circuit.
Even if the third adder circuit and the fourth adder circuit are in the state of 0, the output amplitude is halved and the analog multiplication operation is not hindered. If only the bias voltage can be set to the same value, Vx, -Vx, Vy -Vy
Means that any one of the inputs can be zero. The present invention also includes such a configuration.

FIG. 7 showing such a circuit example is the sixth embodiment of the present invention. The adder circuit 111 of this embodiment has only two outputs of "-Vx + Vy" and "Vx + Vy". One of the input signals "Vx" and "V" is used as the remaining two inputs of the MOS transistor for performing the multiplication operation.
y ”is used as it is. Under such conditions, the above (1)-
When the calculation using the equation (4) is performed, the equation (5) becomes 2 kVx Vy
And the amplitude is halved, but analog multiplication of two inputs can be executed. The adder circuit in this case is composed of MOS transistors M5, M9, MO in the right half of the adder circuit of FIG.
It is composed of only two adders of S-transistors M6 and M10. Alternatively, the exact same result can be obtained by using the adder circuit of FIG. 1 as it is and applying only the DC bias to the input terminal of -Vy.

The seventh embodiment of the present invention will be described with reference to the circuit diagram of FIG. This embodiment is based on MO
Source-grounded first composed of S-transistors M1 and M2
Circuit and a second differential pair formed by MOS transistors M3 and M4. The first differential input signal is applied to the second differential pair in the same manner as the first differential pair, and at the same time, the first differential input signal is applied between the inputs of the first differential pair and the second differential pair. The two differential input signals are input with a relative voltage difference. That is, as in the embodiment of FIG.
For the MOS transistor M1, "-Vx + Vy", MOS
Transistor M2 has "Vx + Vy", MOS transistor M3 has "-Vx-Vy", MOS transistor M
4 is supplied with four addition / subtraction signals by a combination of two input signals and its inverted signal, such as "Vx-Vy".

This is supplied by the adder circuit 11 shown in FIG. 1 as in the embodiment of FIG. The drain terminal connects the drain of the MOS transistor M1 and the drain of the MOS transistor M4, and the drain of the MOS transistor M2 and the drain of the MOS transistor M3, which have outputs of opposite polarities with respect to the input, to generate respective added currents. Further, an average current detection circuit 12 for the drain addition currents of the MOS transistors M1 and M4 and the MOS transistors M2 and M3 is provided, and a current equal to this average current is added to the addition current from Vcc. In this case, the MOS transistors M1 and M4, the MOS transistor M
Since the average values of the drain addition currents of 2 and M3 are equal, this current value is equal to that of the MOS transistors M1 to M3.
The total added current of the four drain currents of 4 is halved. In this way, at the output end, the difference currents Io1 and Io between the respective drain addition currents and the average currents of both drains are added.
2 is output.

This circuit shows an example in which the basic differential transistor is composed of NMOS, but it is inverted upside down to turn the power supply Vcc to ground GND, GND to Vcc, and NMOS to PM.
The same operation can be performed even if the OS is replaced. In this circuit, the source connection point of the differential transistor is fixed to a constant potential (GND in FIG. 8) as in the previous circuit examples, so the input signal voltage is between the gate and source of each element of the NMOS differential pair. As described above, it is possible to suppress the occurrence of distortion and intermodulation.

Output currents Io1 and Io2 of the differential circuit of FIG. 8 are calculated. However, various conditions are the same as before. Since each input signal is assumed to be a fully differential signal, the DC voltage VB at each output of the adder circuit is all equal. MO
The input voltage supplied to the gate terminals of the S transistors M1 to M4 is VGS = VB ± Vx ± Vy. Therefore, in this case, the MOS transistors M1 ...
The descriptive expression of the operation of M4 can be expressed as follows.

M1: I11 = (k / 2) (VB-Vx + Vy-Vth) ² ... (9) M2: I12 = (k / 2) (VB + Vx + Vy-Vth) ² ... (10) M3: I21 = (K / 2) (VB-Vx-Vy-Vth) ² ... (11) M4: I22 = (k / 2) (VB + Vx-Vy-Vth) ² ... (12) Average current detection is (I11 + I12 + I21 + I22) / 2. The output currents Io1 and Io2 can be expressed as follows, respectively.

Io1 = (I11 + I12 + I21 + I22) / 2- (I12 + I21) = {(I11-I12)-(I21-I22)} / 2 = (k / 2) {-2 (VB + Vy-Vth) Vx + 2 (VB- Vy-Vth) Vx} =-2 kVx Vy (13) Io2 = (I11 + I12 + I21 + I22) / 2- (I11 + I22) = {(I21-I22)-(I11-I12)} / 2 = (k / 2) {-2 (VB-Vy-Vth) Vx + 2 (VB + Vy-Vth) Vx} = 2kVxVy (14) As can be seen from these equations, the output currents Io1 and Io2.
Is a constant k that depends on the shape of the MOS element and two input signals V
It is determined only by a simple product of x and Vy. Therefore, an ideal analog multiplication output can be obtained already with only one output. Since the other output is the opposite phase output, both are differential outputs. Since the DC component is zero in any current output, the bias voltage can be freely set and the voltage output can be taken out by using a resistive load.

As described above, in the embodiment shown in FIG. 8, not only the differential output but also the single output can be used as an ideal analog multiplication output, and a completely symmetrical multiplication output can be obtained. In addition, since the calculation result is expressed in a very simple form of a product of k and only two input signals, it does not include element parameters other than k such as Vth, so that the variation sensitivity to the variation of the process parameter is low and the precision is high. An analog multiplication circuit can be constructed. The feature that it is suitable for lowering the voltage and that it is not affected by the substrate effect is similar to that of the embodiment shown in FIG.

FIG. 9 shows the average current detection circuit 12 of FIG. 8 replaced with a concrete circuit. The average current detection circuit 12 is, as shown in the figure, a current copy circuit of MOS transistors M1 and M2 composed of MOS transistors M1 'and M2' and a MOS composed of MOS transistors M3 'and M4'.
It is composed of a current copy circuit of transistors M3 and M4, and a current mirror which adds up all of the copy currents and folds them back. MOS transistors M1 'to M4'
Have the same gate and source as the MOS transistors M1 to M4 respectively, the MOS transistors M1 'to
The drain current of M4 'is the MOS transistor M1
A current equal to the drain current of ~ M4 is generated. MOS
By connecting the drain terminals of the transistors M1 to M4 to the input of the current mirror, the drain currents of these transistors are fully added and folded back at a mirror ratio of 1/2 to form a MOS.
The sum of the drain currents of the transistors M1 and M4, MO
The average current of the sum of drain currents of the S transistors M2 and M3 is output. By preparing a pair of these and sending them to the output terminal, the current subtraction in the above equations (13) and (14) is executed, and only the term of the product of Vx and Vy is taken out.

In FIG. 9, even if any one of the four inputs of Vx, -Vx, Vy, and -Vy is set to 0, the amplitude of the output is halved and the basic analog multiplication operation does not change. Is similar to the case of the embodiment of FIG. 7 described above.
Therefore, a circuit configured with the input "-Vy" set to 0 is
FIG. 10 shows an embodiment of the above. In the case of this embodiment as well, the operation is exactly the same as that of the embodiment of FIG. 9 except that the output amplitude is halved as compared with the embodiment of FIG.

Similarly, in the embodiment shown in FIG. 8, first, the input "V
If "y" is set to 0, each adder for generating a signal to be input to the gates of the MOS transistors M1 and M2 becomes unnecessary, and the number of adders is reduced to two. Further, the input "-Vy" is transferred to the source terminals of the MOS transistors M3 and M4 in exactly the same way as the embodiment of FIG. In this way, the remaining two adders are unnecessary, and the same function as that in FIG. 8 can be realized by a circuit without an adder circuit as shown in FIG. 11 as the tenth embodiment. That is, the multiplication operation of the circuit of FIG. 8 achieves this function by allowing the gate and source of the two differential pair MOS transistors that supply one input signal to have a relative signal voltage difference between the other. .

Therefore, the embodiment of FIG. 8 in which this voltage difference is applied to the gate voltage and the embodiment of FIG. 11 in which this voltage difference is applied to the source voltage are the first differential pair and the second differential pair. Since the relative relationship between the gate and the source of the differential pair is exactly the same, the operation is exactly the same. However, in the circuit of FIG. 11, since the signal Vy added to the input of the first differential pair is 0, the output amplitude is 1/2 that of the circuit of FIG.

An example of a circuit in which the average current detecting circuit 12 of FIG. 11 is replaced with a concrete circuit is shown in FIG. 12 as an eleventh embodiment. The average current detection circuit 12 is exactly the same as in the case of FIG. 9 and has MOS transistors M1 'and M2'.
Current copy circuit of MOS transistors M1 and M2, and current copy circuit of transistors M3 and M4 consisting of MOS transistors M3 'and M4', and these two copy currents are added together and folded back in half. It is composed of a current mirror, which are sent to the output terminals respectively, and the current subtraction in the above equations (13) and (14) is executed to extract only the term of the product of Vx and Vy.

As a common advantage to the above circuit examples,
These are different from the method of biasing with a current source
Since the sources of the S transistors M1 to M4 are used by dropping the voltage to ground GND or a voltage very close to GND, a wide dynamic range can be secured on the drain side.
Therefore, it is also suitable for lowering the voltage. Furthermore, even if it is configured mainly with an NMOS, the source is connected to the ground GND, so even if it is made by a normal P substrate process, it has the characteristic that it is not affected by the substrate effect, and it has high precision and low distortion. You can build an analog circuit.

[0046]

As described above, since the analog multiplier composed of the CMOS according to the present invention is provided with the adder circuit that supplies the addition / subtraction signal necessary for the multiplication operation without distortion, it is unnecessary for the output. It is possible to suppress the occurrence of intermodulation distortion caused by the harmonic distortion and the distortion of the input signal, and it is possible to realize an ideal analog multiplication operation. It is also suitable for low voltage. Because of these advantages, it can be widely used in mixers, frequency converters, phase detectors, etc., and is extremely useful.

[Brief description of drawings]

FIG. 1 is a circuit diagram for explaining an adding circuit section of an analog multiplier according to the present invention.

FIG. 2 is a circuit diagram for explaining the first embodiment of the present invention.

FIG. 3 is a circuit diagram for explaining a second embodiment of the present invention.

FIG. 4 is a circuit diagram for explaining a third embodiment of the present invention.

FIG. 5 is a circuit diagram for explaining a fourth embodiment of the present invention applied to a phase detector.

FIG. 6 is a circuit diagram for explaining a fifth embodiment of the present invention applied to a mixer circuit.

FIG. 7 is a circuit diagram for explaining a sixth embodiment of the present invention.

FIG. 8 is a circuit diagram for explaining a seventh embodiment of the present invention.

FIG. 9 is a circuit diagram for explaining an eighth embodiment of the present invention.

FIG. 10 is a circuit diagram for explaining a ninth embodiment of the present invention.

FIG. 11 is a circuit diagram for explaining a tenth embodiment of the present invention.

FIG. 12 is a circuit diagram for explaining an eleventh embodiment of the invention.

FIG. 13 is a circuit diagram for explaining the basic principle of a conventional CMOS analog multiplier.

FIG. 14 is a circuit diagram for explaining an adding circuit of a conventional analog multiplier.

[Explanation of symbols]

11, 111 ... Adder circuit, 12 ... Average current circuit, M1 ...
M12, M1 'to M4' ... MOS transistors.

Front page continued (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06G 7/163 H03G 3/10

Claims (15)

(57) [Claims] 1. The first and second inputs are differential signals composed of a positive electrode signal and a negative electrode signal having mutually inverted phases, and a first field effect transistor connected to the source ground and a drain grounded respectively. A second field effect transistor connected to the first field effect transistor, wherein the drain current of the first field effect transistor is configured to be input to the source terminal of the second field effect transistor. A first input terminal, a gate of the second field effect transistor as a second input terminal, and a source of the second field effect transistor as an output terminal. The positive electrode signal of the first input is input to the first input terminal of the first adder circuit and the first input terminal of the third adder circuit, and The first input terminal and the first input terminal of said fourth adder circuit to enter a negative signal of the first input, wherein the first and second input terminals of the adder second
The positive signal of the second input is input to the second input terminal of the adder circuit, and the second input terminal of the third adder circuit and the second input terminal of the fourth adder circuit receive the second input signal. An input negative signal is input, the output signal of the first adder circuit is applied between the gate and source of the third field effect transistor, and the output signal of the second adder circuit is applied to the gate of the fourth field effect transistor. Applied between sources, the output signal of the third adding circuit is applied between the gate and source of the fifth field effect transistor, and the output signal of the fourth adding circuit is applied between the gate and source of the sixth field effect transistor. And as a result, the sum of the drain current of the third field effect transistor and the drain current of the sixth field effect transistor, and the drain current of the fourth field effect transistor and the drain of the fifth field effect transistor. An analog multiplier which outputs a difference current with respect to the sum of currents or a difference voltage proportional to the difference current. 2. In the adder circuit, both the first field effect transistor and the second field effect transistor are N-type MO transistors.
An S-transistor, wherein the source of the first field-effect transistor is connected to either the negative power supply terminal or GND, and the drain of the second field-effect transistor is connected to the positive power supply terminal. 1. The analog multiplier according to 1. 3. In the adder circuit, the first and second field effect transistors are both P-type MOS transistors, the source of the first field effect transistor is connected to a positive power supply terminal, and the second field effect transistor is connected. 2. The analog multiplier according to claim 1, wherein the drain of the effect transistor is connected to either the negative power supply terminal or GND. 4. The third to sixth field effect transistors are all N-type MOS transistors, and their sources are all connected in common and are connected to either a negative power supply terminal or GND. The output of the first adder circuit is connected to the gate of the third field effect transistor, the output of the second adder circuit is connected to the gate of the fourth field effect transistor, and the output of the third adder circuit is connected. 2. The analog multiplier according to claim 1, wherein the analog multiplier is connected to the gate of the fifth field effect transistor, and the output of the fourth adding circuit is connected to the gate of the sixth field effect transistor. 5. The third to sixth field effect transistors are all P-type MOS transistors, and their sources are all connected in common and are connected to a positive power supply terminal. The output is connected to the gate of the third field effect transistor, the output of the second adder circuit is connected to the gate of the fourth field effect transistor, and the output of the third adder circuit is connected to the fifth. The analog multiplier according to claim 1, wherein the analog multiplier is connected to the gate of the field effect transistor, and the output of the fourth adding circuit is connected to the gate of the sixth field effect transistor. 6. The gates of the third to sixth field effect transistors are all connected in common and connected to a constant voltage point, and the output of the first adding circuit is the source of the third field effect transistor. The output of the second adder circuit is applied to the source of the fourth field effect transistor, the output of the third adder circuit is applied to the source of the fifth field effect transistor, and 4. The analog multiplier according to claim 1, wherein the output of the adder circuit of No. 4 is applied to the source of the sixth field effect transistor. 7. A sum current of drain currents of the third and sixth field effect transistors is folded back by a current mirror and added to a sum current of drain currents of the fourth and fifth field effect transistors. The analog multiplier according to claim 1, wherein the analog multiplier is an output. 8. At least one of a DC potential of a differential signal composed of a positive electrode signal and a negative electrode signal which is the first input or a DC potential of a differential signal composed of a positive electrode signal and a negative electrode signal which is the second input is changed. The analog multiplier according to claim 4, 5 or 6, wherein the gain of the output signal is controlled by controlling the gain. 9. A positive signal, a negative signal, of the first input,
2. The analog multiplier according to claim 1, wherein either one of the positive polarity signal and the negative polarity signal of the second input is only a DC voltage input. 10. The first and second inputs are differential signals composed of a positive electrode signal and a negative electrode signal having mutually inverted phases, and a first input terminal and a second input terminal are provided. A fourth addition circuit is provided, and the positive signal of the first input is input to the first input terminal of the first addition circuit and the first input terminal of the third addition circuit, The negative signal of the first input is input to the first input terminal of the second adder circuit and the first input terminal of the fourth adder circuit, and the second input signal of the first adder circuit is input. The positive signal of the second input is input to the input terminal and the second input terminal of the second adding circuit, and the second input terminal of the third adding circuit and the fourth adding circuit of the third adding circuit are input. The negative signal of the second input is input to the second input terminal, and the output signal of the first adder circuit is input. A third field effect transistor is applied between the gate and source, an output signal of the second adding circuit is applied between the gate and source of the fourth field effect transistor, and an output signal of the third adding circuit is applied. The fifth field effect transistor is applied between the gate and the source, the output signal of the fourth adder circuit is applied between the gate and the source of the sixth field effect transistor, and the third and sixth field effect transistors A current obtained by subtracting twice the average current of the drain currents of the third to sixth field effect transistors from the sum of the respective drain currents is taken as the first current output, and the fourth and fifth currents are output. From the sum of the drain currents of the respective field-effect transistors, the average current of the drain currents of the third to sixth field-effect transistors is 2
A current obtained by subtracting the doubled current is used as a second current output, and a means for outputting a difference current between the first and second current outputs or a difference voltage proportional to this difference current is output. Analog multiplier. 11. A first input is a differential signal composed of a positive electrode signal and a negative electrode signal whose phases are inverse to each other, and a second input is a positive signal and a negative electrode signal whose phases are inverse to each other. And a first and a second adder circuit having a first input terminal and a second input terminal, wherein the first input terminal of the first adder circuit is the first input terminal. The positive signal of the input is input, the negative signal of the first input is input to the first input terminal of the second adding circuit, and the second input terminal of the first adding circuit and the second input terminal of the first adding circuit are input. The positive signal or the negative signal of the second input is input to the second input terminal of the second adder circuit, and the negative signal of the first input is applied between the gate and source of the third field effect transistor, The positive signal of the first input is applied to the gate signal of the fourth field effect transistor. Between the gate and source of the fifth field effect transistor, the output signal of the first adding circuit is applied between the gate and source of the fifth field effect transistor, and the output signal of the second adding circuit is applied between the gate and source of the sixth field effect transistor. And a current obtained by subtracting twice the average current of the drain currents of the third to sixth field effect transistors from the sum of the drain currents of the third and sixth field effect transistors. As the first current output, and subtracting twice the average current of the drain currents of the third to sixth field effect transistors from the sum of the drain currents of the fourth and fifth field effect transistors. A second current output, and a means for outputting a difference current between the first current output and the second current output or a difference voltage proportional to the difference current as an output. Analog multiplier, wherein. 12. As a means for obtaining the first and second current outputs, the third to sixth field effect transistors and another field effect transistor group having a common gate and source are used. The copy current of the drain current of the field effect transistor of 6 is made, and the sum of these copy currents is folded back by the current mirror to make half the current of the total added current. The current obtained in addition to the summing point of the drain currents of the sixth field effect transistor is taken as the first current output, and one is added to the summing point of the drain currents of the fourth and fifth field effect transistors. Second obtained current
12. The analog multiplier according to claim 10 or 11, characterized in that the current output of 13. The adder circuit comprises a first field effect transistor connected to the source grounded and a second field effect transistor connected to the drain grounded, and the drain current of the first field effect transistor is converted to the second field effect transistor. Configured to input to the source terminal of the field effect transistor of
The gate of the first field effect transistor is used as a first input terminal, the gate of the second field effect transistor is used as a second input terminal, and the source of the second field effect transistor is used as an output terminal. 11. The method according to claim 10,
Alternatively, the analog multiplier according to claim 11. 14. The source terminals of the third to sixth field effect transistors are all connected to a common constant voltage point, and the output signals of the adder circuit or the gates of the third to sixth field effect transistors are connected to each other. 12. The analog multiplier according to claim 10 or 11, wherein either the positive signal or the negative signal of the input is directly applied. 15. The gate terminals of the third to sixth field effect transistors are all connected to a common constant voltage point, and the output signals of the adder circuit are connected to the sources of the third to sixth field effect transistors. 12. The analog multiplier according to claim 10 or 11, wherein either the positive signal or the negative signal of the input is applied.