JP3521628B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and is suitable for use as a single unit or as an IC incorporating a semiconductor device.

[0002]

2. Description of the Related Art Vertical power MOSFETs have been used in many industrial fields in recent years because they have many characteristics such as excellent frequency characteristics, fast switching speed, and low power consumption. As a conventional vertical power MOSFET, as disclosed in, for example, International Publication WO93 / 03502 and Japanese Patent Laid-Open No. 62-12167,
A structure is known in which a groove is formed on the element surface and a channel portion is formed on the side surface of the groove.

However, the above international publication WO93 / 0
The vertical power MOSFETs disclosed in Japanese Patent No. 3502 and Japanese Patent Application Laid-Open No. 62-12167 use wet etching or dry etching in which ions are physically made to collide with each other to form an initial groove. Therefore, a lattice defect remains on the surface of the initial groove, and the lattice defect remains due to the subsequent LOCOS oxidation, which lowers the mobility of the region serving as the channel surface, resulting in an increase in on-resistance. there were.

Therefore, in forming the above-mentioned initial groove, the applicant of the present application first employs chemical dry etching in which the semiconductor substrate is ablated only by gas erosion to eliminate lattice defects in the initial groove, and by subsequent LOCOS oxidation. No. 6,606,931 discloses a semiconductor device capable of eliminating the lattice defect, resulting in a dramatic reduction in on-resistance.
Proposed as an issue.

[0005]

However, in the semiconductor device proposed in Japanese Patent Application No. 6-60693 mentioned above, the semiconductor device shown in FIG.
As shown in Fig. 4, a square pattern cell is adopted, and the shape of the semiconductor region (for example, silicon) at the corner portion of the groove is a right angle pattern in plan view, and the groove is formed in the depth direction. Therefore, the three-dimensional structure has a sharp corner. Further, the gate insulating film (for example, silicon dioxide) is arranged above the semiconductor region, and the gate electrode (for example, low resistance polysilicon) is further arranged thereon. With such a structure, when a voltage is applied between the gate electrode and the source electrode, an electric field is likely to be concentrated in the three-dimensionally sharpened structure portion, and the breakdown voltage between the gate electrode and the source electrode is lowered. There is a concern that it will be easier.
Also, when a voltage is applied between the drain and the source, there is a possibility that electric field concentration is likely to occur in the above-mentioned three-dimensionally sharpened structure portion and a drain-source breakdown voltage defect is likely to occur.

Therefore, an object of the present invention is to obtain a semiconductor device in which the breakdown voltage between the gate electrode and the source electrode does not decrease and a semiconductor device in which the breakdown voltage between the drain and source does not decrease.

[0007]

According to the invention of claim 1 configured as described above, since the groove portion is used as the channel region, the on-resistance is extremely low. further,
By adding curvature to the corners of the grid pattern,
The tip of the three-dimensional protruding portion of the semiconductor region, which is determined by the angle of the corner portion of the lattice pattern and the inclination angle of the groove, is rounded. As a result, when a voltage is applied between the gate electrode and the source electrode in a structure in which the gate insulating film (for example, silicon dioxide) is further arranged on the semiconductor region and the gate electrode (for example, low resistance polysilicon) is further arranged thereon. The concentration of the electric field in the three-dimensionally pointed structure portion is reduced, and the occurrence of defects in the dielectric strength characteristics between the gate electrode and the source electrode is suppressed.

In the conventional orthogonal grid pattern, electric field concentration is likely to occur in a region where the groove width of the corner portion of the grid pattern is large. However, claim 2 configured as described above
According to the invention, the linear groove pattern is opposed to the corner groove of the grid pattern where the electric field is easily concentrated (the region surrounded by the grid pattern is moved in a predetermined direction) to form a staggered grid pattern, In addition to the effect of the invention of claim 1, the maximum groove width can be made smaller than that of the conventional orthogonal lattice groove pattern. As a result, when a voltage is applied between the drain and the source, the electric field relaxation of the corner protrusions of the lattice groove pattern, which is a three-dimensionally sharp structure, can be achieved, thereby suppressing the occurrence of the drain-source breakdown voltage failure. it can.

According to the third aspect of the invention, when the radius of curvature at the corner is Y and the depth of the groove is X, Y
Since it is set so as to satisfy the relationship of ≧ 1.67X−1.17, it becomes stable at a high breakdown voltage between the gate and the source. Further, according to the invention of claim 4, an initial groove is formed by chemical dry etching, the initial groove is selectively oxidized to form a selective oxide film, and then the selective oxide film is removed to form a groove portion. The planar shape of the base layer formed by using the selective oxide film as a mask is determined according to the pattern of the selective oxide film, that is, the pattern of the groove formed after removing the selective oxide film, and the base Although a factor that facilitates electric field concentration in the planar corner portion of the layer is created, providing the curvature in the corner portion of the groove pattern has the effect of reducing the electric field concentration as described above.

[0010]

DETAILED DESCRIPTION OF THE INVENTION

(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.
The embodiment will be described. FIG. 1A is a plan view of a vertical power MOSFET composed of a square unit cell according to the first embodiment of the present invention, and FIG. 1B is a sectional view taken along line AA in FIG. . 2 to 21 are explanatory views of each stage in manufacturing the vertical power MOSFET.

Vertical power MOSFET of this embodiment
1 has a main portion, that is, a unit cell portion, as shown in FIG. 1, and a large number of the unit cells 15 are regularly arranged in a vertical and horizontal plane with a pitch width (unit cell size) a. In FIG. 1, the wafer 21 has an impurity concentration of about 10 ¹⁹ cm ⁻³ and a thickness of 100 to 3
On a semiconductor substrate 1 made of n + type silicon having a thickness of 00 μm, an impurity density of about 10 ¹⁶ cm ^{−3 and} a thickness of 5 μm to 20 μm.
The front and rear n − type epitaxial layers 2 are formed, and the unit cell 15 is formed on the main surface of the wafer 21. In order to form the U groove 50 with a unit cell size a of about 12 μm on the main surface of the wafer 21, a LOCOS oxide film with a thickness of about 1 μm is formed and bonded by self-aligned double diffusion using this oxide film as a mask. A p-type base layer 16 having a depth of about 2 μm and an n having a junction depth of about 0.5 μm.
+ Type source layer 4 is formed, and thereby the U groove 5 is formed.
Channel 5 is set on the side wall portion 51 of 0. Further, after the double diffusion, the diffusion mask and the LOCOS oxide film used for forming the U groove 50 are removed, and the gate oxide film 8 having a thickness of about 60 nm is formed on the inner wall of the U groove 50. A gate electrode 9 made of polysilicon having a thickness of about 400 nm and an interlayer insulating film 18 made of BPSG having a thickness of about 1 μm are formed on the top. Further, the p + type base contact layer 17 having a junction depth of about 0.5 μm is formed on the surface of the central portion of the p type base layer 16, and the source electrode 19 and the n + type source layer 4 formed on the interlayer insulating film 18 are formed. And the p + type base contact layer 17 is in ohmic contact through the contact hole. In addition, the semiconductor substrate 1
The drain electrode 20 is formed so as to make ohmic contact with the back surface of the.

Next, a method of manufacturing the embodiment of the present invention will be described. First, as shown in FIGS. 2 and 3, a wafer 21 is prepared in which an n− type epitaxial layer 2 is grown on a main surface of a semiconductor substrate 1 made of n + type silicon and having a plane orientation of {100}. This semiconductor substrate 1 has an impurity concentration of 10 ¹⁹
It is about cm ^-3 . The epitaxial layer 2 has a thickness of about 6 to 20 μm and an impurity concentration of 10 μm.
It is about ¹⁵ to 10 ¹⁶ cm ^-3 . Next, as shown in FIG. 4, the main surface of the wafer 21 is thermally oxidized to a thickness of 5
A field oxide film 60 having a thickness of about 00 nm is formed, a resist film 61 is then deposited, and the resist film 61 is patterned by a known photolithography process into a pattern having an opening at the center of a cell formation planned position. Then, this resist film 6
Boron (B +) is ion-implanted using 1 as a mask.

After stripping the resist, a p-type diffusion layer 62 having a junction depth of about 3 μm is formed by thermal diffusion as shown in FIG. The p-type diffusion layer 62 finally becomes a part of the P-type base layer 16 described later. Next, as shown in FIG. 5, a silicon nitride film 63 is deposited to a thickness of about 200 nm on the main surface of the wafer 21, and the silicon nitride film 63 is vertically and parallel to the <011> direction as shown in FIG. 6A. The patterning is performed so as to form a lattice-shaped opening pattern having openings with a pitch width (size of the unit cell 15) a. In this opening pattern, the corner portion 63A has a curvature.

Next, the field oxide film 60 is etched by using the silicon nitride film 63 as a mask, and subsequently, FIG.
As shown in, the discharge chamber 7 containing carbon tetrafluoride and oxygen gas
02 to generate plasma to create chemically active species,
This active species is transported to the reaction chamber 703, where it is n
The groove 64 is formed by isotropically chemical dry etching the − type epitaxial layer 2.

Next, as shown in FIG. 8, the groove 64 is thermally oxidized using the silicon nitride film 63 as a mask. This is an oxidation method well known as a LOCOS (Local Oxidation of Silicon) method. This oxidation forms a LOCOS oxide film 65, and at the same time, a U Groove 5
0 is formed and the shape of the groove 50 is determined.

At this time, the angle between the side surface of the groove and the surface of the substrate is controlled by θ in FIG. 8 so that the side surface of the groove has a plane orientation {111}.
The chemical dry etching conditions and the LOCOS oxidation conditions are selected so that the surface becomes closer to the surface. ISPSD '93, pp
135-140 show the calculation result of the relationship between the etching depth and the angle between the groove side surface after LOCOS oxidation and the substrate surface. By changing the etching depth and the LOCOS oxidation time, the relationship between the groove side surface and the substrate surface is shown. The angle can be controlled.

The inner wall surface of the U groove 50 thus formed by the LOCOS oxidation is flat and has few defects, and the surface has a surface condition as good as the initial main surface of the wafer 21 shown in FIG. Next, as shown in FIG.
Boron for forming the p-type base layer 16 is ion-implanted through the thin field oxide film 60 using the OS oxide film 65 as a mask. At this time, the LOCOS oxide film 6
The boundary portion between 5 and the field oxide film 60 becomes a self-aligned position, and the region for ion implantation is accurately defined.

Next, as shown in FIG. 10, the junction depth is 3 μm.
Heat is diffused to about m. Due to this thermal diffusion, the p-type diffusion layer 62 previously formed in the step shown in FIG.
In the step shown in (1), the diffusion layers of boron implanted are integrated to form one p-type base layer 16. Further, both end faces of the region of the p-type base layer 16 are defined by the positions of the side walls of the U groove 50 in a self-aligned manner.

Next, as shown in FIG. 11, patterning is performed with a pattern left in the central portion of the surface of the p-type base layer 16 surrounded by the LOCOS oxide film 65 formed on the surface of the wafer 21 in a grid pattern. Using both the resist film 66 and the LOCOS oxide film 65 as a mask, phosphorus is ion-implanted through the thin field oxide film 60 to form the n + type source layer 4. Also in this case, as in the case of implanting boron ions in the step shown in FIG.
The boundary portion between the OCOS oxide film 65 and the field oxide film 60 becomes a self-aligned position, and the region where ions are implanted is accurately defined.

Next, as shown in FIG.
The n + type source layer 4 is formed by thermal diffusion of 5 to 1 μm, and at the same time, the channel 5 is set. In this thermal diffusion, the end surface in contact with the U groove 50 in the region of the n + type source layer 4 is formed into the U groove 50.
Is defined in a self-aligned manner at the position of the side wall. Above, FIG. 9-
The junction depth of the p-type base layer 16 and its shape are determined by the process of FIG. What is important in the shape of the p-type base layer 16 is that the position of the side surface of the p-type base layer 16 is the U groove 5.
Since it is defined by the side surface of 0, is self-aligned and thermally diffuses, the shape of the p-type base layer 16 is completely symmetrical with respect to the U groove 50.

Next, as shown in FIG. 13, the LOCOS oxide film 65 is terminated with hydrogen in the aqueous solution 700 containing hydrofluoric acid while the pH is adjusted to about 5 by ammonium fluoride. Meanwhile, the oxide film is removed to expose the inner wall 51 of the U groove 50. After this, it is taken out of the aqueous solution and dried in clean air.

Next, as shown in FIG. 15, an oxide film is formed on the side surface 5 of the U groove of the p-type base layer 16 where the channel is to be formed. By this thermal oxidation step, the flatness on the atomic order of the surface on which the channel is to be formed is increased. As shown in FIG. 14, this thermal oxidation step is performed by gradually inserting the wafer 21 into the oxidation furnace 601 kept in an oxygen atmosphere and kept at about 1000 ° C. Next, FIG.
As shown in 6, the oxide film 600 is removed. Similar to the removal of the selective oxide film, the removal of the oxide film 600 is performed in an aqueous solution containing hydrofluoric acid while the pH of the exposed silicon is adjusted to about 5 by terminating the exposed silicon surface with hydrogen. To do. U formed by such a method
The inner wall 51 of the groove 50 is a good silicon surface having high flatness and few defects.

Subsequently, as shown in FIG. 17, a gate oxide film 8 having a thickness of about 60 nm is formed on the side surface and the bottom surface of the U groove 50 by thermal oxidation. Next, as shown in FIG. 18, a polysilicon film having a thickness of about 400 nm is deposited on the main surface of the wafer 21 and is separated by a distance c which is 2β shorter than the distance b between the upper ends of two adjacent U grooves 50. Thus, the gate electrode 9 is formed by patterning. Next, the end portion of the gate electrode 9 is oxidized so that the gate oxide film 8 becomes thick. At this time, as shown in FIG. 19, if the length of the portion where the gate oxide film becomes thicker at the gate end is X, then β> X
To set.

As described above, the steps shown in FIGS. 9 to 18 are the most important manufacturing steps in this embodiment.
The OS oxide film 65 is used as a self-aligned double diffusion mask to form the p-type base layer 16, the n + -type source layer 4 and the channel 5, and then the LOCOS oxide film 65 is removed, after which the gate oxide film is formed. 8 and the gate electrode 9 are formed. next,
As shown in FIG. 20, a patterned resist film 6
Using mask 8 as a mask, boron is ion-implanted through the oxide film 67 to form the p + type base contact layer 17.

Next, as shown in FIG. 21, a junction depth of 0.
The p + type base contact layer 17 is formed by thermal diffusion of about 5 μm. Then, as shown in FIG.
An interlayer insulating film 18 made of BPSG is formed on the main surface of No. 1, and contact holes are formed in a part of the interlayer insulating film 18 to expose the p + type base contact layer 17 and the n + type source layer 4. Further, a source electrode 19 made of an aluminum film is formed,
P + type base contact layer 1 through the contact hole
7 and n + type source layer 4 are brought into ohmic contact. Further, a passivation film (not shown) made of silicon nitride or the like is formed by a plasma CVD method or the like for protecting the aluminum film, and Ti / Ni is formed on the back surface of the wafer 21.
Forming a drain electrode 20 composed of a three-layer film of / Au,
An ohmic contact is made with the + type semiconductor substrate 1.

The effects of the embodiment of the present invention will be described below. As shown in FIG. 6A, the patterning of the silicon nitride film 63 deposited on the main surface of the wafer 21 is performed by using the corner portion 63A with a curved pattern as a mask in the etching region 64 of FIG. Becomes a pattern,
It is reflected in the corner pattern of the square cell in the final process. As a result, in FIG. 1A showing the final structure, the corner portion 80 of the square cell becomes a pattern with a curvature, and the angle of the corner portion of the lattice pattern and the inclination angle of the groove 3 of the semiconductor region (14, 16) are determined. Add a rounded shape to the tip of the three-dimensional protrusion. As a result, the semiconductor regions (14, 16) are further added.
On top of the gate insulating film 5 (eg silicon dioxide),
Further, when a voltage is applied between the gate electrode and the source electrode in the configuration diagram in which the gate electrode 9 (for example, low resistance polysilicon) is arranged on the upper portion thereof, the concentration of the electric field in the three-dimensionally sharpened structure portion is reduced. The occurrence of defects in the dielectric strength characteristics between the gate electrode and the source electrode is suppressed.

Further, in the present embodiment, the initial groove is formed by chemical dry etching, the initial groove is expanded by LOCOS oxidation, and then the LOCOS.
A thin portion is formed by removing the oxide film. Since this thin portion is used as the channel region, the on-resistance becomes very low. Here, regarding the curvature as described above,
From the depth of the U groove 50, that is, the bottom view of the gate oxide film 8, n
It has been known that the deeper the distance to the surface of the − type epitaxial layer 2, the larger the radius of curvature, which will be described with reference to FIGS. 24 and 25.

FIG. 24 is a graph showing the relationship between the radius of curvature of the corner groove 80 and the gate-source breakdown voltage (TZDB). The circle plot () in the drawing shows a groove depth of 1.6.
Data when μm, triangular plot (▲) shows groove depth 1.
The data is for 0 μm. As can be seen from the figure, in any case, the breakdown voltage becomes smaller as the radius of curvature becomes smaller. Also, when the groove depth is 1.6 μm, the radius of curvature is 1.5 μm or more, and when the groove depth is 1.0 μm, the radius of curvature is 0.5 μm or more, the pressure resistance is stable in a high place. effective.

FIG. 25 shows this relationship. FIG. 25 shows the relationship between the groove depth and the radius of curvature (critical radius of curvature) that begins to stabilize when the pressure resistance is high. From this figure, when the groove depth is X and the radius of curvature is Y, Y ≧ 1. .6
It can be seen that if the relationship of 7X-1.17 is satisfied, the breakdown voltage becomes high and stable. (Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

In the present embodiment, as shown in FIG. 6 (b), the patterning of the silicon nitride film 63 deposited on the main surface of the wafer 21 is made into a pattern in which the corner portion 63B has a curvature, and at the same time, The checkerboard pattern is a zigzag checkerboard pattern. Here, the zigzag lattice pattern means that a straight groove pattern is opposed to a corner groove of a lattice pattern in which an electric field is easily concentrated (a region surrounded by the lattice pattern is moved in a predetermined direction). As a result, the etching region 64 of FIG.
And is reflected in the square cell pattern in the final process. (FIG. 23) In the conventional lattice pattern (FIG. 22) and the orthogonal lattice groove pattern shown in FIG. 1, the electric field is likely to concentrate in the region 81 where the groove width is the maximum, but as shown in FIG.
By making the pattern to face the linear groove pattern portion 82, the maximum groove width can be made smaller than that of the pattern (FIG. 1A) in which the corner portions of the orthogonal lattice groove pattern face each other, and between the drain and the source. When a voltage is applied, it is possible to achieve electric field relaxation of the protrusions of the corner groove of the lattice pattern, which is a three-dimensionally sharpened structure, and thereby suppress the occurrence of drain-source breakdown voltage failure.

The first and second embodiments described above apply the present invention to the vertical MOSFET described in International Publication WO93 / 03502 or the vertical MOSFET described in Japanese Patent Application No. 6-60693. However, the present invention is not limited to a vertical MOSFET in which a p-type base layer and an n + -type source layer are ion-implanted in a self-aligned manner using a LOCOS oxide film as a mask,
For example, a vertical MOSFET in which a P-type base layer and an n + -type source layer are ion-implanted and diffused as a resist mask.
Can also be applied to.

In the above-described embodiments, the present invention has been described only in the case where the vertical type MOSFET is applied. However, the present invention is not limited thereto and is applied to a power MOSIC incorporating such a vertical power MOSFET. Alternatively, it may be applied to the gate structure of an insulated gate bipolar transistor (IGBT). Furthermore, it can also be applied to lateral power MOSFETs and IGBTs.

Further, in the embodiments, only the n-channel type has been described, but it goes without saying that the same effect can be obtained also with the p-channel type in which the n-type and p-type semiconductor types are exchanged.

[Brief description of drawings]

FIG. 1A is a plan view showing a part of a vertical power MOSFET according to a first embodiment of the present invention, and FIG.
FIG. 7A is a sectional view taken along line AA of FIG.

FIG. 2 is a vertical power M according to the first embodiment of the present invention.
FIG. 7 is a diagram which is used for describing a manufacturing process of the OSFET.

FIG. 3 is a vertical power M according to the first embodiment of the present invention.
FIG. 7 is a cross-sectional view provided for explaining the manufacturing process of the OSFET.

FIG. 4 is a vertical power M according to the first embodiment of the present invention.
FIG. 7 is a main-portion cross-sectional view which is provided for describing a manufacturing process of an OSFET.

FIG. 5 is a vertical power M according to the first embodiment of the present invention.
FIG. 7 is a main-portion cross-sectional view which is provided for describing a manufacturing process of an OSFET.

FIGS. 6 (a) and 6 (b) are plan views of relevant parts for explaining the manufacturing process of the vertical power MOSFET according to the first and second embodiments of the present invention, respectively.

FIG. 7 is a vertical power M according to the first embodiment of the present invention.
FIG. 7 is a diagram which is used for describing a manufacturing process of the OSFET.

FIG. 8 is a vertical power M according to the first embodiment of the present invention.
FIG. 7 is a main-portion cross-sectional view which is provided for describing a manufacturing process of an OSFET.

FIG. 9 is a vertical power MO according to the first embodiment of the present invention.
FIG. 7 is a main-portion cross-sectional view which is provided for describing a manufacturing process of an SFET.

FIG. 10 is a main-portion cross-sectional view provided for explaining the manufacturing process of the vertical power MOSFET according to the first embodiment of the invention.

FIG. 11 is a main-portion cross-sectional view provided for explaining the manufacturing process of the vertical power MOSFET according to the first embodiment of the invention.

FIG. 12 is a main-portion cross-sectional view provided for explaining the manufacturing process of the vertical power MOSFET according to the first embodiment of the invention.

FIG. 13 is a diagram for explaining a manufacturing process of the vertical power MOSFET according to the first embodiment of the present invention.

FIG. 14 is a diagram which is used for describing a manufacturing step of the vertical power MOSFET according to the first embodiment of the present invention.

FIG. 15 is a main-portion cross-sectional view for explaining the manufacturing process of the vertical power MOSFET according to the first embodiment of the invention.

FIG. 16 is a diagram which is used for describing a manufacturing step of the vertical power MOSFET according to the first embodiment of the present invention.

FIG. 17 is a diagram to be used for closing the manufacturing process of the vertical power MOSFET according to the first embodiment of the invention.

FIG. 18 is a main-portion cross-sectional view provided for explaining the manufacturing process of the vertical power MOSFET according to the first embodiment of the invention.

FIG. 19 is a main-portion cross-sectional view for explaining the manufacturing process of the vertical power MOSFET according to the first embodiment of the invention.

FIG. 20 is a main-portion cross-sectional view provided for explaining the manufacturing process of the vertical power MOSFET according to the first embodiment of the invention.

FIG. 21 is a main-portion cross-sectional view provided for explaining the manufacturing process of the vertical power MOSFET according to the first embodiment of the invention.

22A is a plan view showing a part of a conventional vertical power MOSFET, and FIG. 22B is a sectional view taken along line AA of FIG.

FIG. 23 (a) is a plan view showing a part of a vertical power MOSFET according to a second embodiment of the present invention,
(B) is an AA sectional view of (a).

FIG. 24 is a graph showing the relationship between the radius of curvature in the corner groove and the breakdown voltage between the gate and the source.

FIG. 25 is a graph showing the relationship between groove depth and critical radius of curvature.

[Explanation of symbols]

1 n + type semiconductor substrate 2 n-type epitaxial layer 4 n + type source layer 5 channels 6 n-type drain layer 7 JFET section 8 Gate oxide film 9 Gate electrode 16 p-type base layer 19 Source electrode 20 drain electrode 50 U groove 51 U-groove inner wall 65 LOCOS oxide film 80 corners 601 Oxidation furnace 603 wafer boat 700 aqueous solution 702 discharge chamber 703 Reaction chamber 704 Shading cloth

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-90595 (JP, A) JP-A-4-273167 (JP, A) JP-A-2-202064 (JP, A) International Publication 93/003502 (WO, A1) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/316 H01L 21/336

Claims (4)

(57) [Claims] 1. A semiconductor substrate having two opposing main surfaces, a first conductivity type semiconductor layer formed on one main surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate, and the low impurity. A groove portion formed in a predetermined region with the surface of the semiconductor layer having a high concentration as a main surface, and a second conductivity type base layer disposed so as to terminate a joint portion with the semiconductor layer at or near a side surface of the groove portion. A source layer of the first conductivity type, which is formed in the base layer and is disposed so that a junction with the base layer terminates at or near the side surface of the groove, and the side surface of the groove or its side A gate insulating film that is disposed in the vicinity and that has the base layer sandwiched between the semiconductor layer and the source layer as a channel region and covers at least the channel region, and a gate that is disposed on the gate insulating film. An electrode, a source electrode that is in electrical contact with both the source layer and the base layer, and a drain electrode that is in electrical contact with the other main surface side of the semiconductor substrate. The groove pattern is a grid pattern. There is a curvature in the corner portion of the area surrounded by the grid pattern, the angle of the corner portion of the grid pattern and the groove portion
Three-dimensional protrusion of the semiconductor region determined by the inclination angle of the side surface
A semiconductor device having a rounded tip shape . 2. The semiconductor device according to claim 1, wherein the grid pattern of the groove is a zigzag grid pattern in which a region surrounded by the grid pattern is moved in a predetermined direction. 3. When the radius of curvature at the corner portion is Y and the depth of the groove portion is X, Y ≧ 1.67X-1.
The semiconductor device according to claim 1, wherein the relationship of 17 is satisfied. 4. An initial groove is formed in the groove portion by chemical dry etching, and the initial groove is selectively oxidized to form a selective oxide film having a predetermined depth from the main surface in the semiconductor layer in the predetermined region. However, it is formed by removing the selective oxide film after that, and the base layer and the source layer are formed by diffusing impurities by using the selective oxide film as a mask. Item 4. The semiconductor device according to any one of Items 1 to 3.