JP3522567B2 - Video output processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video output processing device, and more particularly, to a main video including information such as moving images and still images, a sub-image including information such as subtitles, and information such as menus and title screens. OSD (On Screen Disp included)
lay) is intended to improve the controllability of real-time processing of data output.

[0002]

2. Description of the Related Art In recent years, with the progress of multimedia,
In the video field as well, various types of playback devices have been proposed in consideration of digital broadcasting. Then, it is considered that more information will be output from the broadcasting station in the future, and a situation may arise in which a processing exceeding the reproduction processing capability is required depending on the reproducing apparatus. If a process that exceeds such specifications is requested, it will be perceived by the viewer as a phenomenon such as image distortion, which may give a sense of discomfort or discomfort. Therefore, conventionally, when displaying moving image data on a personal computer, etc., the number of images (frame number) displayed per unit time is reduced in order to reduce the discomfort and manage the playback to match the specifications of the playback device. It is possible to apply so-called frame dropping, but in high-definition broadcasting that provides high-quality video, it is thought that such processing will still give viewers an unpleasant feeling. .

Therefore, it is conceivable to realize the above-mentioned reproduction processing capacity by using a control device having an ability to satisfy the processing with reference to the worst value of the processing cycle required for the output processing. The configuration unnecessarily complicates the configuration of the control device and operates at a high frequency, which may cause an environmental problem.

[0004]

The conventional video output processing apparatus is configured as described above, and when a load exceeding the processing capacity is required for the apparatus, the viewer is not made uncomfortable and the like. No effective method for processing data in real time has been proposed, and video output processing that can deal with this in case future mass communication is required due to progress of multimedia. Equipment was needed. The present invention has been made in view of the above situation. In real-time video output processing, even if the reproduction processing capacity is exceeded, the viewer is uncomfortable without causing image distortion. It is an object of the present invention to provide a video output processing device capable of performing video output without any need.

[0005]

According to the video output processing device of the first aspect of the present invention, the video data processing execution means for processing a plurality of different types of video data and outputting them to the monitor, and the video data processing. The processing of the plurality of video data by the execution means detects whether or not the processing is completed in real time at the monitor output time, and the processing delay is detected by the video processing delay detection means. In the case of
Video data processing control means for controlling the video data processing execution means so as to reduce the processing assigned to the line period.

According to a second aspect of the present invention, there is provided the video output processing apparatus according to the first aspect, wherein the video data processing control means controls the video data for reducing the processing. Is set to control the video data processing execution means.

According to a third aspect of the present invention, in the image output processing apparatus according to the second aspect, the priorities are set from the viewpoint of the viewer to the display screen on the monitor. The decision is made based on the distance.

According to a fourth aspect of the present invention, in the image output processing apparatus according to the second aspect, the priority order is determined based on the display information set in the image data. It is something that is done.

According to a fifth aspect of the present invention, there is provided the video output processing apparatus according to the first aspect, wherein each of the plurality of different types of video data is processed in the one line period. The processing of at least one video data item is divided into a plurality of processes.

According to a sixth aspect of the present invention, in the image output processing apparatus according to the fifth aspect, the stopped image data is the main image.

According to claim 7 of the present invention, in the video output processing device according to claim 1, the video processing delay detecting means detects the delay by a predetermined number of fields. Alternatively, it is performed at frame intervals.

According to a seventh aspect of the present invention, in the image output processing apparatus according to the first aspect, the image processing delay detecting means detects the delay by a predetermined number of lines. It should be done at intervals.

According to an eighth aspect of the present invention, there is provided the image output processing apparatus according to the first or fifth aspect, wherein the image data processing control means comprises a plurality of image data of different types. The processing is reduced by stopping at least a part of the processing of the video data.

According to a ninth aspect of the present invention, there is provided a video output processing apparatus according to the fifth aspect, wherein the data to be processed in the one line period has at least three different types. 2 out of 1 video data
One or more are included.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION This embodiment of a video output processing apparatus of the present invention will be described below with reference to the drawings. Embodiment 1. 1 is a diagram showing a configuration of a video output processing device according to a first embodiment of the present invention. In FIG.
Reference numeral 101 denotes an external storage unit that stores main video data to be displayed and output, sub video data, and OSD data. Reference numeral 102 denotes a buffer for the main video, sub video, and OSD data to be displayed and output, which is stored in the external storage unit 101. An internal storage unit 103 sequentially retrieves these data by ringing, and a transfer control unit 103 controls transfer between the external storage unit 101 and the internal storage unit 102. Further, 108 is a first for connecting the transfer control unit 103 and the internal storage unit 102 to each other.
It is an internal bus. Reference numeral 104a denotes a main video output unit that inputs the main video data from the internal storage unit 102 and outputs the main video data, and 104b denotes a sub video output that inputs the sub video data from the internal storage unit 102 and outputs the sub video data. Section 104c is the OS from the internal storage section 102.
The OSD output unit outputs the OSD data by inputting the D data.

Reference numeral 109 is a second internal bus for connecting the internal storage unit 102, the main video output unit 104a, the sub video output unit 104b, and the OSD output unit 104c to each other. A monitor 105 receives data from the main video output unit 104a, the sub video output unit 104b, and the OSD output unit 104c as input, and mixes the data (video).
A video output unit for outputting. 106 receives the control signal 110 from the video output unit 105 as its input, and uses an internal program to input the main video output unit 104a, the sub video output unit 104b, the OSD output unit 104c, and the transfer processing unit 103.
It is a central processing control unit for controlling the. The control regarding these outputs is performed in order of the control signals 107a, 107b, 107.
c, 107d. The control signal 110 is a signal for transmitting the start time of one line in video output.

FIG. 2 shows the central processing control unit 10 shown in FIG.
6 shows an example of a detailed configuration of No. 6. As shown in the figure, the central processing control unit 106 includes a central processing unit 201 and an instruction memory 2
02, working memory 203, I / O memory 204a-2
04e, the internal bus 205 is included.

The instruction memory 202 includes a central processing unit 20.
The instruction (program) to be executed in 1 is stored. The central processing unit 201 executes the program stored in the instruction memory 202. The work memory 203 stores a processing result in the middle of the central processing unit 201. I / O memory 204
Reference numeral a denotes a control memory for the main video output unit 104a, which has a configuration called memory-mapped I / O. Similarly, the I / O memory 204b, the I / O memory 204c, and the I / O memory 204d are memories for controlling the sub-picture output unit 104b, the OSD output unit 104c, and the transfer control unit 103, respectively. . Central processing unit 201, instruction memory 202, working memory 203, I / O
The O memories 204a to 204e are connected to each other by an internal bus 205.

Reference numeral 204e is an I / O memory for inputting a control signal from the video output unit 105. Since the information from the control signal 110 is written in the I / O memory 204e, the detection of the start time of one line can be realized by reading the I / O memory 204e in the central processing unit 201.

Here, the I / O memory 204e is "0".
In this case, it means that the opening of one line, that is, the next line has started when viewed from the immediately preceding display line. The central processing unit 201 writes "1" at the start point of one line, and the I / O memory 2
When 04e is "0", it means that the next display line is started. In addition, the I / O memory 20
If 4e is "1", it means that the next display line has not been opened yet.

In the above structure, the video data processing execution means is realized by means other than the monitor 111, and the video output delay detection means is realized by the video output section 105.
The central processing control unit 106 realizes video data processing control means.

Next, the central processing control unit 1 shown in FIG.
The video output process performed in 06 will be described with reference to the flowchart of FIG. In the processing of FIG. 3, when all the video output processing cannot be performed in real time, the video output processing is stopped in real time by stopping the processing of the sub video and not performing the display output processing of the sub video. It realizes to be processed by. The video output processing is performed in each field unit or each frame unit in the video output.

A buffer provided inside the main video output unit 104a, the sub video output unit 104b, and the OSD output unit 104c for allocating the main video, sub-video, and OSD processing for performing each video output process to the internal storage unit 102. The intervals at which the processes are executed differ depending on the memory capacity. These buffer memories are used for buffering each video data stored in the external storage unit 101. For example, the buffer capacity unit 1 assigned to the main video output
If the buffer 04a is larger than the display field image, the main video output process may be performed once per field. Similarly, if the interval between the sub-picture and OSD output processing is once in one field, the main-picture output processing is performed in a plurality of display line periods, and the sub-picture output processing is performed in another plurality of display line periods. In addition, the OSD output process can be performed in another plurality of display line periods.

However, the increase in the capacity of these buffer memories, that is, the memory of the internal storage unit 102, increases the circuit scale of the entire apparatus. In order to reduce the circuit scale of the entire device, it is necessary to reduce the capacity of these buffer memories. However, at this time, the intervals of the output processing of the main video, the sub video, and the OSD are shortened. In the present embodiment, the intervals of the output processing of the main video, the sub video, and the OSD are
The display is performed twice in one line period. In addition,
The process of allocating to one line period described below refers to each video output process that needs to be performed in the display one line period in each video output process.

Here, 301a and 301b indicate main video processing A and B, and 302a and 302b indicate sub video processing A and B.
And 303a and 303b indicate OSD processes A and B, and thus, these processes are divided into two here. In each process, transfer control of video data from the external storage unit 101 to the internal storage unit 102, the main video output unit 104a, and the sub video output unit 104 are performed.
b, it controls the OSD output unit 104c.

The main video processing 302a and 302b and the sub video processing 303a and 303b are processings to be assigned to one line period. Further, here, each output process is performed twice in one line period, but the number of processes performed in one line is not limited to two. 304a,
304b is a process for determining whether or not the process has been delayed. Based on the results of these determination processes 304a and 304b, 302
The sub-picture output processes A and B of a and 302b are bypassed. That is, the processing amount is reduced here as the video output processing.

Reference numeral 305 denotes a process for judging whether or not the one-line process at the monitor 111 output is in time. Also, 30
6 is the determination processing 304a, 3
This is a process of substituting "1" when the process is delayed with respect to the flag (flag) used for the determination in 04b. 307
Is the processing to determine whether the number of display lines in one field or frame is exceeded, and if the number of display lines is not exceeded,
The processing is repeated from the processing 301a.

Reference numeral 308 is for initial setting.
This is a process of substituting "0" for g. FIG. 4 shows a state where a processing delay occurs in the processing shown in FIG. Again, main video processing, sub-video processing, OSD
It is assumed that all the processing is completed in one line. In FIG. 4, reference numeral 400 represents an H-SYNC (horizontal synchronization signal) signal. 400a is a point indicating the start of processing for one line. 400b is a point indicating the start of processing of the next line. Reference numeral 401 denotes a line on which video output is performed, 402 denotes a line next to the line 401, and 403
Represents the lines next to the line 402, which are line A, line B, and line C, respectively. Therefore, originally, the start point 40 of the next line (line B) in the line A 401 is
0b is the start point 40 of the line in the line B402.
It is the same as 0a. Similarly, for the start point 400b of the next line on the line B402, the line C4
This is the same point as the start point 400a of the line at 03.

Reference numeral 410 denotes a process which needs to be performed on the line A 401, and includes a main video process A 411 a and a main video process B 41.
1b, sub-picture processing A412a, sub-picture processing B412
b, OSD processing A 413a, and OSD processing B 413b
And 410x represents the point in line A401 where the determination process 305 for determining the delay of the video output process is performed. Reference numeral 420 denotes a process that needs to be performed on the line B402. The main video process A421a, the main video process B421b, the OSD process A423a, and the OSD process B.
423b.

Similarly, reference numeral 430 denotes a process that needs to be performed on the line C 403 and includes a main video processing A 431a, a main video processing B 431b, an OSD processing A 433a, and an OSD processing B 433b. The order of execution in the video output process 410 is the main video process A411a, the sub video process A412a,
The OSD processing A 413a, the main video processing B 411b, the sub video processing B 412b, the OSD processing B 413b, and the determination processing 305 at the point 410x are performed in this order.

The order of execution in the video output processing 420 is main video processing A 421a, OSD processing A 423a, main video processing B 421b, OSD processing B 423b, and the order of execution in the video output processing 430 is main video. Process A431a, OSD process A433a, main video process B43
1b and OSD processing B433b are performed in this order.

Further, 403a indicates a processing margin in the line C 403. In these video output processes 410, 420, 430, the determination processes 304a, 304b, 305, 307 and the substitution processes 306, 308 shown in FIG. 3 are omitted unless otherwise noted.

At this time, consider a case where the video output processing 410 performed on the line A 401 exceeds the processing performance of the central processing control unit 106 and exceeds the start position 400a of the line B 402. That is, in this case, all of the video output processing could not be completed within one line and could not be processed. Here, the determination process 305 is executed at the point 410x, which is beyond the start of the next line.

In this case, the result of the judgment processing 305 is "Y", and "1" is substituted into the flag in the substitution processing 306. In the video output process 420 performed on the subsequent line B402, the results of the determination processes 304a and 304b are both "Y", and the sub video process A302a and the sub video process B302b are not executed. That is, the video output process 420 includes the main video process A421a and the OSD process A423.
a, main video processing B421b, and OSD processing B423b are performed in this order.

As a result, the video output process 420 is contained in the line B402 to be executed. Further, in the video output processing 430 on the line C 403, similar to the video output processing 420, the main video processing A 431 a, the OSD processing A 433 a, the main video processing B 431 b, the OSD processing B 43.
Each process is performed in the order of 3b. Further, the video output processing 430 has a processing margin 403a. Then, there is a processing margin in the subsequent lines, and it becomes possible to realize the video output processing in real time.

Further, in the present embodiment, the output processing of the main video, the sub video, and the OSD is realized by the processing in which each is two (A, B). This is because by dividing each process, a part of each process can be executed at least once. This allows
It can be expected to avoid that each video output process is not reflected.

As described above, according to the first embodiment, the determination processing 305, the substitution processing 306, and the determination processing 304a, 3
04b is provided, and in one line, main video, sub video, O
When it is detected that the SD video output processing cannot be performed in real time, the sub video processing (302a, 3)
02b) is not executed in the next line, so that the processing amount of the entire video output processing is reduced, and therefore,
Guaranteeing the real-time processing of the video output processing can be realized.

Further, these judgment processing and substitution processing are
The program code size is also small. Further, it is not necessary to complicate the control device for processing these and to operate at high frequency.

In the first embodiment, the video output processing is executed in the order of the main video processing, the sub video processing, and the OSD processing. However, the order of execution of these is not limited, and they may be different. The same effect can be achieved by executing in. In the first embodiment, the main video, the sub video,
The output processing of OSD is divided into two, and both the sub-picture processing A 302a and the sub-picture processing B 302b are not performed by executing both the determination processing units 304a and 304b shown in FIG. 3, thereby reducing the processing. However, at least one of the sub-picture processing A3 is performed by not performing the determination processing of either one of the determination processing units 304a and 304b.
It is also possible to reduce processing by performing 02a or sub-picture processing B302b. As a result, it is possible to set the processing to be excluded stepwise in stages, that is, the processing to be reduced.

Further, the output processing of the main image, the clothing image, and the OSD is divided into two, but it is also possible to divide these output processing into three or more. As a result, it is possible to finely set the processing to be excluded from the processing target, and it is possible to process more processing in one line period.

In addition, in the first embodiment, both of the two sub-picture processes are stopped, but either one of the sub-picture processes may be stopped. Specifically, even if any one of the determination processes 304a and 304b is omitted, the same effect can be realized. Further, although the sub-picture processing is stopped in the first embodiment, the same effect can be realized even if the main picture processing or the OSD processing is stopped.

Furthermore, in this case, even if either one of the two main video processings is stopped or one of the two OSD processings is stopped, the same effect is realized. can do.

Further, in the first embodiment, the initialization of the flag used for determining the processing delay is performed for each field or for each frame. At this time, the substitution process 308, which is the initialization of the flag used for determining the processing delay, is performed for each predetermined field and each predetermined frame. In other words, when a processing delay occurs, by reducing the processing during the field or during the frame, it is possible to reduce the amount of lost information. Even if the initialization of the flags to be used is carried out in units of a plurality of fields or units of a plurality of frames, the information to be lost increases a little, but the processing can be simplified.

On the contrary, when the initialization of the flag used for determining the processing delay is performed for each predetermined line unit, the substitution process 308 is performed for each predetermined line, so that the processing delay determination is performed for each predetermined line unit. be able to. That is, FIG. 18 shows a situation where a processing delay occurs in the case of determining the processing delay in units of one line. In the figure, 1801 represents a line D on which video output is performed. 1
Reference numeral 801 denotes a process assigned to the line D, which includes the main video processing A1811a, the main video processing B1811b, the sub video processing A1812a, the sub video processing B1812b, and the OSD.
The process A 1813a and the OSD process 1813b are included. Further, in the line D1801, the number of display pixels of the OSD image is smaller than that in the lines A401 and B402, and the processing content is changed.
The processing cycle of the SD processing A 1813a and the OSD processing B 1813b is shortened.

The OSD image can be displayed at any position on the screen with any display width and display height, and the contents displayed on the line B and the line D are different. 1800x is main video processing A431a
, OSD processing A433a, and main video processing B431b
And a determination process 305 performed after the video output process assigned to the line B402 formed by the OSD process B433b.
Is the execution position at the display time of the line B402.
The determination processes 304a, 304b, 30 shown in FIG.
5, 307 and the substitution processes 306, 308 are omitted unless otherwise specified. Further, the same reference numerals as those in FIG. 4 indicate the same or corresponding portions.

Here, there is a delay in the processing of the line A401, and the sub-video processing A412a and the sub-video processing B412b are not performed in the line B402 and the line C403. Stated. In the subsequent determination processing at the point 1800x, the processing assigned to one line in one line period is included, and the determination processing 305 is “N”. Therefore, the determination process 304 in the next line D1801
a and 304b are “N”. This is different from the execution position of the substitution process 308 in FIG.
This is to execute 08. Therefore, line D180
In 1, the main video processing, the sub video processing, and the OSD processing can be executed respectively.

That is, the flag reflected by the determination process 305 is initialized (substituted by 0) for each line in the substitution process 308, so that the period for reducing the sub-picture output process can be reduced to one line. it can. The non-display period of the sub-picture can be set to only one line B402, and the lines other than the line B402 are not significantly different from the main picture, the sub-picture, and the picture in which all the OSDs are displayed.

As described above, by determining the processing delay for each line and adjusting the processing reduction for each line, it is possible to display a large amount of each video output and obtain a further effect. You can It should be noted that here, although the processing reduction is performed by the processing of the sub-picture,
The same effect can be obtained when processing is reduced by SD.

Embodiment 2. A video output processing apparatus according to Embodiment 2 of the present invention will be described below with reference to the drawings. The configuration of the video output processing device according to the second embodiment is almost the same as that shown in the first embodiment, but is characterized in that the flow of the video processing output is different.

FIG. 5 shows a processing flow of the video output processing apparatus according to the second embodiment. Regarding the video output processing, the difference from the first embodiment is that the determination processing 304a, 304b
, There is no determination processing 501a, 501b, 502a, 50
2b, 503a, 503b are respectively provided,
Other than this, the processing flow is the same as in the first embodiment.

The determination processing 501a, 501b, 502
Reference characters a, 502b, 503a, and 503b are determination processes of whether or not the process has been delayed, and are performed according to the priority of the process bypass set. Priority is used as a flag indicating this priority. Judgment processing 501
a, 501b, depending on the result, main video processing A301
a, bypasses the main video processing B301b. In addition, the determination processing 502a and 502b determines that the sub-picture processing A
302a and sub-picture processing B302b are bypassed. Similarly, the determination processes 503a and 503b determine whether the OSD
It bypasses the process A 303a and the OSD process B 303b.

Here, when the priority to be set is determined for this video output device and the output processing priority of the main video is the lowest, "1" is set to the priority indicating the priority. As a result, when all video output processing exceeds the performance of the central processing control unit 106, that is,
When the processing of the central processing control unit 106 is delayed, the main video processing A301a and the main video processing B301b, which are video output processing, are performed.
Will be bypassed.

As the above-mentioned priority, if the sub-picture output process has the lowest priority, Prior
Set "2" to the "ity". As a result, the sub-picture processing B
It bypasses 302a and sub-picture processing B302b. Similarly, if the OSD output process has the lowest priority as the above priority, Priority is set.
By setting "3" to the central processing control unit 106,
When the process of 1 is delayed, the processes of the OSD process A 303a and the OSD process B 303b are bypassed. That is, as in Embodiment 1 described above, when it becomes impossible to perform all the video output processing in real time, the processing amount of the video output processing can be reduced, and the video in real time can be reduced. Output processing can be realized. The setting of the priority at this time can dynamically set the priority displayed as the system.

Here, a method of setting the priority according to the display order of the output displays will be described. Figure 6
9 illustrates a display result by a process using the video output processing device according to the second embodiment. In FIG. 6A, a screen 610 is a display result before the processing is reduced. In FIGS. 6B and 6C, 611 and 612
The processing of the central processing control unit 106 is delayed because the worst states of the respective video output processing cycles are overlapped or the video output processing waits for processing, so that all video output processing is performed in real time. Is impossible, and the screen of the display result after the processing is reduced.

Reference numeral 610a represents the display of the main image, and 61
Reference numeral 0b represents a sub-picture display, and reference numeral 610c represents an OSD display. The respective image displays are OSD display 610c and sub-image display 610 from the front side of the viewpoint.
b, the main image display 610a is displayed in this order.

From this display order, it is assumed that the object of processing reduction is the main image and the priority indicating priority is set to "1". This is because it can be determined that the information about the display image in the back is not necessarily important from the viewpoint. Here, when it is impossible to perform all the video output processing in real time, the main video processing A30 is processing relating to the display video 610a of the main video displayed deepest from the viewpoint.
By bypassing 1a and the main video processing B301b, as shown in FIGS. 6A and 6B, the video output processing is reduced. As a result, the display result becomes the display result 611 from the display image 610.

In some cases, it may be determined that the information regarding the image displayed in the middle of the display image in the display order from the viewpoint is not important. In this case, Priorit
If it is impossible to perform all video output processing in real time by setting y to “2”, the sub video 61
By bypassing the sub-picture processing A 302a and the sub-picture processing B 302b, which are the processing relating to 0b, the display results are as shown in FIGS. 6A to 6C, and the display result is the display image 6
From 10, the display result 612 is obtained.

The display from the viewpoint indicates this priority, p
Setting the priority will dynamically change the detouring output process when the video output process is delayed. That is, at least the most important video information can be displayed for each output and displayed scene.

As described above, according to the second embodiment,
Judgment processing 501a, 501b and judgment processing 502a, 5b
02b and the determination processes 503a and 503b, when it becomes impossible to output all of the main video, sub-video, and OSD in real time, the main video is output according to the set priority. Processing 301a, 301
b or sub-picture processing 302a, 302b,
Alternatively, by bypassing the processes 303a and 303b of the OSD, it is possible to realize the real-time processing of the entire video output processing, as in the first embodiment, and increase the program code size and the apparatus. The complexity of
In addition to the fact that there is no need for high frequency operation, this priority set here has the least amount of information regarding video information,
By selecting the one that is least affected by the non-display, it is possible to perform control oriented to the user.

In the second embodiment, the main video processing, the sub video processing, and the OSD processing are prioritized in the order of display from the viewpoint, but the priorities presented by the user are set. Well, it has the same effect. By doing so, it is possible to freely set the user's will according to which image display the user is interested in.
User-oriented control can be performed as compared with the case where the information to be automatically displayed is deleted as in the first embodiment.

In the second embodiment, the video output processing is prioritized in the order of display from the viewpoint. However, prioritization of which processing is to be prioritized according to the preset display state. You can also do For example,
Regarding OSD, when OSD display used for setting a menu screen for controlling the apparatus is performed, OSD display is given priority. As for the sub-picture, the DVD standard (DVD Specification for Read-Only Disc, Part3 VIDEO
F which is one of the commands included in SP_DCSQ in SPECIFICATIONS Version1.0 August 1996)
There is a command such as forcibly displaying the sub-picture output by the STA_DSP, and the sub-picture is preferentially displayed by this command.

Embodiment 3. A video output processing apparatus according to Embodiment 3 of the present invention will be described below with reference to the drawings. The configuration of the video output processing device according to the third embodiment is almost the same as that shown in the first embodiment, but is characterized in that the flow of the video processing output, particularly the OSD output process is different. is there.

FIG. 7 is a flow chart showing the processing flow of the video output processing apparatus according to the third embodiment. Regarding the video output process, the difference from the first embodiment is that there is no determination process 304a, 304b, and the OSD process A303.
a, OSD process B303b, OSD process A701a,
This is a point changed to the OSD processing 701b. In the third embodiment, when the image output process cannot be executed in real time, the processing amount of the OSD process is reduced, and other than that, the process of the first embodiment is not performed. The same processing as the flow is performed.

The flow of the OSD processing A 701a is shown in FIG. 8 and the flow of the OSD processing B 701b is shown in FIG. The OSD process A 701 a illustrated in FIG. 8 includes a determination process 801, an address calculation process A 802 a, an address calculation process B 802 b, and a transfer control process 803 for the transfer control unit 103.

The address calculation processing A 802a and the address calculation processing B 802b are executed in the external storage unit 101 of the transfer source.
The address of the SD image and the address of the internal storage unit 102 of the transfer destination are calculated. Here, if all the video output processing can be executed in real time, the address calculation processing A 802 a is executed. If all the video output processing cannot be executed in real time, the address calculation processing A 802 a is executed. The process B802b is executed. The difference between these two address calculations will be described later. Reference numeral 801 determines whether or not all video output processing cannot be executed in real time. If execution is possible, control is transferred to address calculation processing A 802a. If execution is not possible, address calculation processing is performed. B8
It is configured to transfer control to 02b. Next, the transfer control process 803 starts the transfer process between the external storage unit 101 and the internal storage unit 102.

As shown in FIG. 9, the OSD process B701b includes a determination process 901, an address calculation process C902, and
The transfer control unit 103 includes a transfer control process 803 for the transfer control unit 103. The address calculation process C902 calculates the address of the OSD image in the external storage unit 101 of the transfer source and the address of the internal storage unit 102 of the transfer destination.

Reference numeral 901 is for determining whether or not all video output processing cannot be executed in real time, and if it is executable, address calculation processing C902 and control processing 80
Execute 3. When the execution is impossible, the address calculation process C902 and the control process 803 are bypassed.

In the processing of the third embodiment, if all the video output processing can be executed in real time, the OS
The output process of D executes the address calculation process A 802 a and the transfer control process 803, and the address calculation process A 902 and the transfer control process 803.

However, when all the video output processing cannot be executed in real time, the OSD output processing is the address calculation processing A by the determination processing similar to the first and second embodiments.
802b and the transfer control process 803 following it are executed.

Regarding processing in this way, 8 bi
OSD of t / pixel (O with 1 pixel consisting of 8 bits
The case of outputting 720 pixels in the horizontal direction in SD) will be described as an example.

At this time, the transfer amount of the OSD image is 720b.
yte (1 byte = 8 bits). In the transfer by the OSD address calculation processes 802a and 902, which is performed when all the video output processes can be executed in real time, each transfer of 360 bytes is performed.
This is to reduce the capacity of the internal storage unit 102,
This is to reduce the waiting time for access to another external storage unit 101.

Here, if all the video output processes within one line are not in time and cannot be executed in real time, then O
The SD output process is substantially bypassed by the OSD process B701b, which reduces the process. That is, O
Only the SD process A701a will be executed. At this time, if the OSD is output at 8 bits / pixel, only the OSD of 360 pixels can be output in the horizontal direction. However, 720 pixels in the horizontal direction, 4 bit /
If you output a pixel OSD image, 360b
It can be realized with the transfer amount of yte. That is, the OS
The output process of the OSD image can be performed only by executing the D process A701a.

FIG. 10 shows these states. Figure 10
Reference numeral 1001 in (a) is an OSD output image when the video output process can be executed in real time. 100 in FIG. 10B
Reference numeral 2 is an output image of an 8-bit / pixel OSD image when the video output process cannot be executed in real time. Further, 1003 in FIG. 10C indicates a case where the video output process cannot be executed in real time, and is 4 bits / pix.
It is an output image of the OSD image of el. Of these figures, 1003 in FIG. 10C is the O according to the third embodiment.
It becomes the SD output image. As shown in FIG. 10, when the processing amount of the OSD is reduced, the image display effect of the output image 1003 that outputs all the OSD images is extremely large as compared with the output image 1002 in which half the OSD image is not output at all. Although the amount of information regarding the number of colors is reduced to the user, it is possible to convey all the amount of information regarding the OSD image itself.

Each address calculation process realizes the above-described operation. Address calculation processing A80
In 2a, the address of the OSD to be transferred is calculated from the information of the OSD stored in the external storage unit 101 at 8 bits / pixel, and the address calculation processing B802b
Then, the address of the OSD to be transferred is calculated from the information of the OSD stored in the external storage unit 101 by 4 bits / pixel. These address calculation processes are extremely simple and easy to realize.

As described above, according to the third embodiment,
By providing the OSD processes 701a and 701b, even when it becomes impossible to perform the video output process of the main video, the sub video, and the OSD in real time, as in the first embodiment, the entire video output process is performed. It is possible to realize real-time processing of the above, and there is no need to increase the program code size, complexity of the device, and high-frequency operation, and the OSD display is completely reduced due to the reduction of the video output processing. It is possible to avoid the situation where it is not displayed,
It is possible to reduce the discomfort to the user.

In the third embodiment, the transfer amount for one OSD image process is 360 bytes.
The transfer amount here is not limited to this, and it goes without saying that the same effect can be realized even if the transfer amount is another.

In addition, in the third embodiment, the processing of the OSD image is performed from 8 bits / pixel to 4 bits / pixel.
Although the load was reduced by changing to l, for example,
By changing from 8 bit / pixel to 2 bit / pixel, the transfer amount becomes 1/4 and the processing is greatly reduced. For example, from 8 bit / pixel to 6 bit
Transfer rate is 3 / by changing to bit / pixel
However, although the effect of reducing the processing is reduced, the loss of the information amount regarding the number of colors of the OSD image to be displayed is reduced,
A bit that constitutes one pixel of the OSD image before and after the change
With regard to the number, the same or higher effect can be realized without being limited to this.

Fourth Embodiment An image output processing apparatus according to Embodiment 4 of the present invention will be described below with reference to the drawings. The configuration of the video output processing device according to the fourth embodiment is almost the same as that of the first embodiment shown in FIG. 1 and FIG. 2 except that the external storage device 101 has a feature. In the video processing, by stopping the color / contrast change processing, the sub-video output processing in the central processing control unit is reduced, and the video output processing is realized in real time.

Here, FIG. 11 shows an example of the sub-picture data unit stored in the external storage unit 101. The external storage unit 101 stores a sub-picture data unit 1101 and a sub-picture data unit 1102.

The sub-picture data unit 1101 includes unit information (SPUH) 1101a and image data (PPUH).
XDX) 1101b and display control command (SP_DC
SQ) 1101c and 1101d.

Further, the display control command 1101d includes color / contrast change data (CHG_COLCO).
N) 1101e is included.

The sub-picture data unit 1102 is composed of unit information 1102a, image data 1102b, and display control command 1102c.

The unit information 1101a and 1102a
Includes the data size (SPU_-SZ) of the sub-picture data units 1101 and 1102, and the display control command 11
01c and 1102c start addresses (SPU_DCSQ
T_SA) is stored. Image data 1101b,
Image data is stored in 1102b.

Further, the display control command 1101c,
1101d and 1102c, the execution time of the display control command (SP_DCSQ_STM), the start address of the next display control command (SP_NXT_DCSQ_SA),
Display start (FSTA_DSP, STA_DSP), display end (STP_DSP), initial color (SET_COLO)
R), initial contrast (SET_CONTR), display position (SET_DAREA), color / contrast change (CHG_COLCON), and the like are stored.

Next, the video output processing performed by the central processing control unit according to the fourth embodiment will be described with reference to FIG. Figure 1
2, main video processing A301a, main video processing B30
1b, OSD processing A 303a, OSD processing B 303b,
Judgment processing 304b, 305, 307 and substitution processing 30
The configurations of 6, 308 are almost the same as those shown in FIG. 3 is different from FIG. 3 in that the determination processing 304a is eliminated, and in the sub-picture processing 302a, as sub-picture processing A302a, data transfer control from the external storage unit 101 to the internal storage unit 102, sub-picture data unit analysis processing, and display control. This is the point that the command analysis processing is performed, and the sub-picture processing B302b performs the color / contrast change data analysis processing.

In the sub-picture processing A 302a, the external storage unit 1
01 to the internal storage unit 102, and further the sub-picture output unit 10
Sub-picture data is transferred to 4b. Further, the sub-picture data unit information 1101a is analyzed, and the display control command 1
101c start address, next sub-picture data unit 1
Get the starting address of 102. Further, the display control commands 1101c and 1101d are sequentially analyzed according to the execution time. In the sub-picture processing B302b, the color / contrast change data 1101e is analyzed, and the sub-picture output unit 104b is controlled using the control signal 107b. Judgment process 305
If it is determined that the 1-line processing is not in time, the central processing control unit 106 detours the sub-picture processing B302b by the judgment processing 304b, and stops the color / contrast change processing, thereby stopping the sub-picture processing. Try to reduce.

As described above, according to the fourth embodiment of the present invention, when the main image, the sub image, and the OSD image output process cannot be performed in real time, only the color / contrast change process is stopped. As a result, the processing amount of the entire video output processing can be reduced without stopping the output of the sub video image. As a result, similar to the first embodiment, even when the video output processing of the main video, the sub video, and the OSD cannot be performed in real time, the real time processing of the entire video output processing is guaranteed. In addition to increasing the program code size, complicating the apparatus, and eliminating the need for high-frequency operation, the sub-picture processing A302a can be realized.
The external storage unit 10 does not bypass the processing in
Data transfer control from 1 to the internal storage unit 102, sub-picture data unit analysis processing, display control command analysis processing,
It is executed every line. As a result, if the video output process can be completed within one line, the sub-video output can be restored in a normal state from the next display control command. That is, it is possible to correctly display all of the main video, the sub video, and the OSD output for each display control command.

Embodiment 5. A video output processing apparatus according to Embodiment 5 of the present invention will be described below with reference to the drawings. In the present embodiment, when the video output processing cannot be performed in real time, an upper limit is set for the color / contrast change processing in the sub video processing according to the increased processing amount, so that the sub video output in the central processing control unit can be performed. The processing is reduced and the video output processing is realized in real time. FIG. 11 shows an example of the sub-picture data unit used in the fifth embodiment, and the sub-picture data unit shown in FIG. 11 is the same as that used in the fourth embodiment. FIG. 13 is a block diagram of a video processing device according to the fifth embodiment, in which 1311 is, for example, 27M.
This is a control signal indicating the number of cycles (Delay) from the start of one line when sampling at Hz, and is output from the video output unit 105 and input to the central processing control unit 106. The other structure is the same as that shown in FIG. 1, and therefore its explanation is omitted here. FIG. 14 shows an example of a detailed configuration of the central processing control unit 106 in FIG. In the figure, 1404f is the video output unit 1.
This is an I / O memory for inputting the control signal 1311 from 05, and since the other configuration is the same as that shown in FIG. 2, its explanation is omitted here.

Control signal 1 is used to detect the start time of one line.
This can be realized by writing the information from 10 into the I / O memory 204e and reading it by the central processing unit 201. Here, when the I / O memory 204e is "0", it indicates that one line has already started. When the central processing unit 201 writes "1" at the start point of one line, and when the I / O memory 204e is "0" after a lapse of time when the determination process 305 is executed, the next display line is started. Means that.

At this time, the central processing unit 201 reads the I / O memory 1404f, so that it is possible to know the number of processes that cannot be completed in one line. Also, I / O
If the storage memory 204e is "1", it means that the next display line has not been started yet.

The central processing control unit 1 shown in FIG. 13 will be described below.
The video output process performed in 06 will be described with reference to FIG.
In FIG. 15, what is different from the one shown in FIG. 3 used in the first embodiment is that the processes 304a and 304b are omitted,
This is the point that the processes 1504, 1510, and 1511 are provided.
Further, in 302a, data transfer control from the external storage unit 101 to the internal storage unit 102, sub-picture data unit analysis processing, and display control command analysis processing is assigned as sub-picture processing A. In 302b, sub-picture processing B is performed. Color / contrast change data analysis processing is performed.

In the sub-picture processing A 302a, the external storage unit 1
01 to internal storage unit 102 and sub-picture output unit 104b
Transfer sub-picture data to. Furthermore, the sub-picture data unit information 1101a is analyzed, and the display control command 11
01c start address, next sub-picture data unit 11
Get the starting address of 02. Further, the display control commands 1101c and 1101d are sequentially analyzed according to the execution time.

In the sub-picture process B302b, the color / contrast change data 1101e is analyzed and the control signal 107b is obtained.
Is used to control the sub-picture output unit 104b. 1504
Is a process of determining whether or not the process is delayed. 1511
Reduces the number of times of color / contrast change processing according to the processing delay when it is determined that the processing is delayed in processing 1504. Here, as an example, the total number of color / contrast change points is set to N, and the processing required for one change is 1
Requires 0 cycles. (Delay / 10) value is 1
It is a value obtained by converting the processing amount delayed with respect to the line output into the number of color / contrast change points. That is, (Delay ÷ 1
0) Unless the processing is reduced by the change point processing, the real time of the video output processing cannot be guaranteed. From the above, sub-picture processing 2
At, the color / contrast change point is (N-De
By reducing the processing to the points of lay / 10), the video output processing can be accommodated in one line. The above (N
In the calculation of −Delay ÷ 10), the result is rounded down to the nearest whole number.

When (N-Delay ÷ 10) ≦ 0, the sub-picture processing B does not perform the color / contrast change processing. Process 1510 is the d used in process 1511.
The I / O memory 1404f is read from the elay.

As described above, according to the fifth embodiment, when it becomes impossible to perform the video output processing of the main video, the sub video, and the OSD in real time, the processing amount over one line period is exceeded. The number of color / contrast changes is reduced in accordance with the above, so the entire process of video output processing can be reduced without stopping all color / contrast change processing while the sub-picture image output is being obtained. In addition, the real time of the video output process can be guaranteed. Further, since the processing in the sub-picture processing A 302a is not bypassed, the data transfer control from the external storage unit 101 to the internal storage unit 102, the sub-picture data unit analysis processing, and the display control command analysis processing are performed for each line. To be executed. As a result, if the video output process can fit in one line,
The sub-picture output can be restored in a normal state from the next display control command. That is, it is possible to correctly display all of the main video, the sub video, and the OSD output for each display control command.

Sixth Embodiment Hereinafter, a video output display device according to a sixth embodiment of the present invention will be described with reference to the drawings. FIG. 13 is a block diagram of a video output processing device used in the sixth embodiment. In the present embodiment, when the video output processing cannot be performed in real time, in the sub-video processing,
By stopping the display control command analysis processing and the color / contrast change processing as shown in the fourth embodiment, the sub-picture output processing in the central processing control unit is reduced,
The video output processing is realized in real time. The schematic configuration of the video output device is the same as in the first embodiment.
Is the same as that described in.

FIG. 16 shows a video output process according to the sixth embodiment, which is performed by the central processing control unit 106. Figure 1
6, main video processing A301a, main video processing B30
1b, OSD process A303a, OSD process B303b
Or determination processing 304a, 304b, 305, 307,
The substitution processes 306 and 308 are the same as those shown in FIG. The difference from that shown in FIG. 3 is that the sub-picture processing A1
602a, B1602b, and C1602c are provided. In the sub-picture processing A1602a, data transfer control from the external storage unit 101 to the internal storage unit 102, sub-picture data unit analysis processing is assigned, and sub-picture processing B1602b.
Then, the display control command analysis processing is assigned, and the sub-picture processing C1602c performs the color / contrast change data analysis processing.

In the sub-picture processing A1602a, the sub-picture output section 104b is transferred from the external storage section 101 to the internal storage section 102.
Transfer sub-picture data to. Furthermore, the sub-picture data unit information 1101a is analyzed, and the display control command 11
01c start address, next sub-picture data unit 11
Get the starting address of 02. In the sub-picture process B1602b, the display control commands 1101c and 1101d are sequentially analyzed according to the execution time. In the sub-picture processing C1602c, the color / contrast change data 1101e is analyzed,
The control signal 107b is used to control the sub-picture output unit 104b.

When it is judged in the judgment processing 305 that the one-line processing is not in time, the central processing control unit 106
Then, the sub-picture processing B 1602b and the sub-picture processing C 1602c are bypassed by the determination processing 304a and 304b.
In this way, the display control command analysis processing and the color / contrast change processing are stopped to reduce the sub-picture processing.

As described above, according to the sixth embodiment, when the video output processing of the main video, the sub video, and the OSD cannot be performed in real time, the display control command analysis processing,
By stopping the color / contrast change processing, it is possible to reduce the processing amount of the entire video output processing while the sub-video image output is being obtained by the display control command when the one-line processing becomes too late. This makes it possible to guarantee the real time of the video output process.

Since the process in the sub-picture process A1602a is not bypassed, the data transfer control from the external storage unit 101 to the internal storage unit 102 and the sub-picture data unit analysis process are executed for each line. As a result, if the video output process can be completed within one line, the sub video output from the next sub video data unit can be restored in a normal state. That is, it is possible to correctly display all of the main video, the sub video, and the OSD output for each sub video data unit.

Seventh Embodiment Hereinafter, a video output processing device according to a seventh embodiment of the present invention will be described with reference to the drawings. FIG. 17 is a diagram showing a flow of main video output processing using the video output device in the seventh embodiment of the present invention. The main video output processing of FIG. 17 includes a main video output processing control unit 1701 that controls the main video output processing method, a main video data transfer processing delay detection unit 1702, and a main video data transfer processing start control unit 1703. It The configuration of the video output device in the seventh embodiment is the same as that shown in FIG.

The operation of the main video output process of the seventh embodiment configured as described above will be described below. First, in the main video output processing control unit 1701, the transfer control unit 103 sets the control information necessary to transfer the main video data from the external storage unit 101 to the internal storage unit 102.
Do to. At this time, f indicating that the processing is delayed
According to the state of lag, the output process of the line to be displayed is selected and the output process is performed.

If flag = 1, it is determined that the one-line processing at the output of the monitor 111 is not in time, and the means for reducing the main video processing is selected. For example, the amount of data to be stored in the internal storage unit 102 during one line period can be adjusted by the method of vertical filtering processing. In this embodiment, the processing time required for the main video output processing is reduced by selecting the filtering processing in which the amount of data to be stored is small.

The above is the method of reducing the main video output processing in the subsequent lines when the processing of the preceding line exceeds the performance. Further, the main video output processing itself impairs the performance of the processing of one line period. In this embodiment, means for detecting such a situation is provided.

For example, when a waiting time occurs before the data transfer process can be activated, a delay in this process is accumulated, which may affect the subsequent sub-picture processing and OSD picture output processing. Main video data transfer processing delay detection unit 1
Reference numeral 702 is for detecting the occurrence of this waiting time, and in the present embodiment, the main video output process is reduced so that this delay does not affect the processes after the main video output.

When the waiting time is detected, the main video data transfer processing start control unit 1703 switches the processing so as to stop the data transfer only on that line. At this time, the video data for one line before, which is already stored in the buffer, is substituted for the main video display in the one-line period, which utilizes the characteristic that the vertical correlation of the video signals is large. By performing such a process, it is possible to suppress the visual image quality deterioration of the main video.

As described above, according to the seventh embodiment, when a waiting time occurs before the data transfer processing can be activated, this is detected, the main video processing is stopped only for the line concerned, and the data is stored in the buffer. By executing the display using the video data of one line before which is already stored in, the time required for the main video output processing is shortened, the accumulation of the processing delay time is suppressed, and the sub video and OSD image output processing is executed. You can
In addition, the deterioration of image quality can be suppressed to be small.

Depending on the amount of processing, the processing by the main video output processing control section 1701 or the main video data transfer processing delay detection section 1702 and the main video data transfer processing start control section 1 is performed.
You may make it use only any one of the process by 703.

It is also possible to use the above embodiments in combination. That is, any one of the third embodiment for reducing the OSD processing, the fourth to sixth embodiments for reducing the sub-picture output processing, and the seventh embodiment for reducing the main-picture output processing is optional. It is possible to use two or more in combination. The combinations of these embodiments can be flexibly combined depending on the presence or absence of encoded data of main video or sub-video of the input stored encoded data and the presence or absence of OSD display. That is, by allocating the unprocessed portion to each video in the combination of the output processing reduction of the main video, the sub-video, and the OSD, it is possible to reduce the portion that cannot be executed in each video output processing. . As a result, the portions that are not executed in the respective image output processes are reduced, and although the respective images are incomplete, it is possible to display a more complete image as a whole.

Further, in each of the embodiments, the description has been given of the format in which the three types of the main image, the sub image, and the OSD alternately appear as the image data, but a single item of these image data is continuous. The same can be applied to the case where two types appear alternately or when two types appear alternately.

[0112]

As described above, according to the video output processing apparatus according to the first aspect of the present invention, the delay of the processing related to the video output is detected, and when the processing delay occurs, the one-line period is set. By reducing the assigned video output processing, it is possible to guarantee real-time video output, and further, the viewer does not feel discomfort. Furthermore, the program code size does not increase much, the control device required for processing does not need to be complicated, and it is not necessary to operate at high frequency.

Further, according to the video output processing apparatus of the second aspect of the present invention, when the delay of the above processing is detected, the priority of which video data processing is reduced is determined according to the situation at that time. Or by setting a priority order in advance, there is an effect that the display at the time of reducing the above processing can be performed by selecting the video data.

According to the video output processing device of claim 3 of the present invention, in the video output processing device of claim 2, the priority is changed from the viewpoint of the viewer to the display screen on the monitor. Since the determination is made based on the distance, there is an effect that the display at the time of reducing the above processing can be performed in accordance with the user orientation.

According to a fourth aspect of the video output processing apparatus of the present invention, in the video output processing apparatus according to the second aspect, the priority is determined based on the display information set in the video data. Since this is done, important information such as the program title is preferentially displayed, and there is an effect that these are not overlooked.

According to a fifth aspect of the present invention, there is provided the video output processing apparatus according to the first aspect, wherein each of the plurality of different types of video data to be performed in the one line period. Since at least one video data process is divided into a plurality of processes, the buffer memory can be reduced.

According to a sixth aspect of the video output processing apparatus of the present invention, in the video output processing apparatus according to the first aspect, the delay is detected at a predetermined number of fields or frame intervals. Therefore, there is an effect that the load on the hardware due to the delay detection can be reduced.

According to the video output processing device of claim 7 of the present invention, in the video output processing device of claim 1, the detection of the delay is performed at a predetermined number of line intervals. This has the effect of enabling highly accurate screen display.

According to the eighth aspect of the present invention, in the image output processing apparatus according to the first or fifth aspect, the reduction of the image output processing is performed by a plurality of different types. Since at least a part of the processing of any one of the video data is stopped, the entire display screen is not disturbed, and the desired video data can be referred to. effective.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a video output processing device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a central control processing unit in the video output processing device according to the first embodiment.

FIG. 3 is a flowchart showing a flow of processing by the video output processing device in the first embodiment.

FIG. 4 is a diagram showing a situation in which a processing delay has occurred in the video output processing according to the first embodiment.

FIG. 5 is a flowchart showing a flow of processing by a video output processing device according to the second embodiment of the present invention.

FIG. 6 is a diagram for explaining a display result by performing video output processing using the video output processing device according to the second embodiment.

FIG. 7 is a flowchart showing a flow of processing by a video output processing device according to the third embodiment of the present invention.

FIG. 8 is a flowchart showing a flow of OSD processing A of the video output processing apparatus in the third embodiment.

FIG. 9 is a flowchart showing a flow of OSD processing B of the video output processing device in the third embodiment.

FIG. 10 is a diagram showing an image of an OSD output image by the OSD processing of the video output processing device according to the third embodiment.

FIG. 11 is a diagram showing a configuration of a sub-picture data unit by a picture output processing device according to the fourth embodiment of the present invention.

FIG. 12 is a flowchart showing the flow of processing by the video output processing device in the fourth embodiment of the present invention.

FIG. 13 is a configuration diagram of a video output processing device according to a fifth embodiment of the present invention.

FIG. 14 is a configuration diagram of a central control processing unit in the video output processing device according to the fifth embodiment.

FIG. 15 is a flowchart showing the flow of processing by the video output processing device in the fifth embodiment of the present invention.

FIG. 16 is a flowchart showing the flow of processing by the video output processing device in the sixth embodiment of the present invention.

FIG. 17 is a flowchart showing the flow of processing by the video output processing device in the seventh embodiment of the present invention.

FIG. 18 is a diagram showing a situation in which a processing delay has occurred in the case of determining the processing delay on a line-by-line basis.

[Description of Reference Signs] 101 external storage unit 102 internal storage unit 103 transfer processing unit 104a main video output unit 104b sub-video output unit 104c OSD output unit 105 video output unit 106 central processing control units 107a to 107d control signal 108 first internal Bus 109 Second internal bus 110 Control signal 111 Monitor 201 Central processing unit 202 Instruction memory 203 Working memory 204a I / O memory (for main video output unit control) 204b I / O memory (for sub video output unit control) 204c I / O memory (for OSD output unit control) 204d I / O memory (for transfer control unit control) 204e I / O memory (for control signal from video output unit) 610 Display image example before processing reduction 610a Main video 610b Sub video 610c OSD video 611 Display image example after processing reduction 612 After processing reduction Shows an example image 1001 8bit / pixel OSD output 1002 0SD treatment reduces after output of (8bit /
OSD of pixel) 1003 0SD Output result after processing reduction (4bit / p
OSD of ixix) 1311 Change point number calculation processing 1404f due to processing time delay I / O memory (for control signal indicating the number of cycles from H-SYNC)

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H04N 5/445 H04N 5/445 Z (56) Reference JP-A-10-293566 (JP, A) JP-A-11-163814 ( JP, A) US Patent 5534942 (US, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 5/00-5/42 H04N 5/265 H04N 5/445

Claims (8)

(57) [Claims] 1. A video data processing execution means for processing a plurality of different types of video data to output to a monitor, and a processing of the plurality of video data by the video data processing execution means within real time at a monitor output time. The video processing delay detecting means for detecting whether or not the processing is completed, and the processing by the video data processing executing means when the processing delay is detected by the video processing delay detecting means,
A video output processing device, comprising: video data processing control means for controlling the video data processing execution means so as to reduce the processing assigned to one line period. 2. The video output processing device according to claim 1, wherein the video data processing control means sets the priority order of the video data when reducing the processing, and controls the video data processing execution means. A video output processing device characterized by being a thing. 3. The video output processing device according to claim 2, wherein the priority order is determined based on a distance from a viewpoint of a viewer to a display screen on the monitor. . 4. The video output processing device according to claim 2, wherein the priority is determined based on display information set in the video data. 5. The video output processing device according to claim 1, wherein at least one video data process of each process of the plurality of video data of different types performed in the one line period is divided into a plurality of processes. Video output processing device. 6. The video output processing apparatus according to claim 1, wherein the video processing delay detecting means detects the delay at a predetermined number of fields or frame intervals. . 7. The video output processing apparatus according to claim 1, wherein the video processing delay detecting means detects the delay at a predetermined number of line intervals. 8. The video output processing device according to claim 1 or 5, wherein the video data processing control means stops at least a part of the processing of any one of the plurality of video data of different types. A video output processing device characterized by reducing processing by doing so.