JP3522900B2 - Video signal processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device for processing a video signal conforming to the NTSC system such as a color television receiver or a VTR between frames.

[0002]

2. Description of the Related Art In a video signal conforming to the NTSC system, the phases of color subcarriers (color subcarriers) are in opposite phase between frames (frame by frame) as shown in the following expression (1). f _SC = 455 × 525 × f _F / 2 Equation (1) where f _F : frame frequency, f _SC : color subcarrier frequency. As a device that processes a video signal even between frames, for example, a three-dimensional YC separation circuit or the like is known. This three-dimensional YC separation circuit utilizes the above properties of the NTSC system video signal to perform addition and subtraction between frames (that is, three-dimensional processing including processing in the time axis direction). The luminance signal and the color signal can be accurately separated.

However, if a video signal other than the NTSC system is processed between frames, the adverse effect will be adversely affected. Therefore, only the video signal conforming to the NTSC system can be processed between frames. Therefore, in an apparatus that processes video signals even between frames, it is necessary to switch to two-dimensional processing (that is, intra-field processing, scanning line processing) when a video signal other than the NTSC system is input. On the other hand, video signals that do not generally comply with the NTSC system include, for example, a playback video signal and a special playback video signal of a home VCR, a special playback video signal of a laser disk, and a video signal of a game machine.

As described above, N is included in a general video signal.
Since there are many video signals that do not conform to the TSC system, in an apparatus that also performs processing between frames, it is automatically detected whether or not the input video signal complies with the NTSC system and the input video is based on the result. Signal is NTSC
A circuit for determining whether or not the system complies is required, and hereinafter such a circuit is referred to as a nonstandard determination circuit.

FIG. 12 is a block diagram showing the configuration of a conventional video signal processing device. 1 is an input end to which a video signal is input, 2 is an output end from which a video signal is output, 3 is a two-dimensional processing circuit for performing two-dimensional processing in the frame on the input video signal, and 4 is time for the input video signal A three-dimensional processing circuit that performs three-dimensional processing between frames including the axial direction, 5 is a switch circuit that switches output signals from the two-dimensional processing circuit 3 and the three-dimensional processing circuit 4, and 6 is a count clock input. Clock input terminal, 8 is a non-standard detection circuit for detecting whether the input video signal conforms to the NTSC system, 4
0 detects whether or not the input video signal complies with the NTSC system, and based on the result, the input video signal is NTS
A non-standard determination circuit for determining whether or not it conforms to the C method, and 41 is an up & down counter. In the following description, for example, an inverted signal of Q (inverted output) is
It is expressed as Q, and in each drawing, the upper part of Q is marked with ￣.

Next, the operation will be described. First, the input video signal from the input terminal 1 is two-dimensionally processed within the frame by the two-dimensional processing circuit 3. Further, the input video signal is subjected to three-dimensional processing by the three-dimensional processing circuit 4 between frames including the time axis direction. The output signals of the two-dimensional processing circuit 3 and the three-dimensional processing circuit 4 are the switches 5
Entered in. On the other hand, the input video signal from the input terminal 1 is
It is input to the non-standard determination circuit 40, and it is determined whether or not the input video signal conforms to the NTSC system, and it is determined whether or not the input video signal conforms to the NTSC system based on the result.

In the non-standard decision circuit 40, first, the non-standard detection circuit 8 detects whether or not the input video signal conforms to the NTSC system. Here, the non-standard detection circuit 8 uses the property that the color subcarriers of the video signal conforming to the NTSC system (standard system) have opposite phases for each frame as described above. Whether or not each frame has a reverse phase is determined by APC (Automatic P) at the frame switching portion.
(hase Control) Detected as disturbance of detection voltage. Then, the standard / non-standard detection signal of "H" (logical) level in the case of the reverse phase and "L" (logical) level in the case of the non-phase is output in frame units.

The standard / non-standard detection signal is input to the U / D terminal of the up & down counter 41. The up & down counter 41 performs a count-up operation when the U / D-terminal is at "H" level, and a count-down operation when the U / D-terminal is at "L" level. On the other hand, the count clock from the count clock input terminal 6 having one frame period of the video signal as one cycle is input to the clock terminal T of the up & down counter 41,
The up & down counter 41 performs counting operation at the rising edge of this clock. Further, an RC signal of "H" level is output to the ripple carry output terminal RC when the count value representing Q4 to Q1 in hexadecimal (H) becomes F (H) or 0 (H). The enable terminal EN is a control signal input terminal for the counting operation, and the counting operation is stopped when the EN signal of "H" level is input. Then, the Q4 output signal of the up & down counter 41 is output from the non-standard determination circuit 40 to the switch circuit 5 as a standard / non-standard determination signal.

Further, the switch circuit 5 is set to 3 when the standard / non-standard decision signal is at "H" level representing the standard signal.
The output signal of the dimensional processing circuit 4 is selected (switched) and output to the output end 2. When the output signal is the "L" level representing a non-standard signal, the output signal of the two-dimensional processing circuit 3 is selected and the output end 2 is output. Output to.

Here, an example of a timing chart of each part signal when the initial count value is 0 (H) and the detection signal from the non-standard detection circuit 8 switches from the non-standard signal to the detection signal of the standard signal is shown in FIG. Shown in. In addition,
(H) represents a hexadecimal number. First,
The standard / non-standard detection signal from the non-standard detection circuit 8 is input to the U / D terminal of the up & down counter 41, but when this input signal is at the "L" level, the count value does not advance, so the initial value. It remains 0 (H) and does not change. Next, when the "H" level standard / non-standard detection signal is input to the U / D terminal, the up & down counter 41 sequentially performs count-up operation at the rising edge of the clock,
At the tenth clock, the count value becomes 8 (H), the Q4 output signal of the up & down counter 41 becomes "H" level, and the standard / non-standard determination result (standard / non-standard) of "H" level representing the standard signal. The standard determination signal) is output from the non-standard determination circuit 40.

Further, the up & down counter 4
1 continues the count-up operation, and its count value becomes C (H) at the 14th clock. Here, for example, when the standard / non-standard detection signal from the non-standard detection circuit 8 to the U / D terminal becomes "L" level, the up & down counter 4
1 switches to the countdown operation, and the count value becomes B (H) at the 15th clock. Further, when the standard / non-standard detection signal to the U / D terminal becomes "H" level, the up & down counter switches to the count up operation again, and the count value becomes F (H) at the 19th clock. After that, the RC output signal becomes "H" level,
Since this RC output signal is input to the enable terminal EN, the count-up operation is stopped.

Contrary to FIG. 13, the initial count value is F (H).
FIG. 1 is an example of a timing chart of signals of respective parts when the standard / non-standard detection signal from the non-standard detection circuit 8 switches from the standard signal to the detection signal of the non-standard signal.
4 shows. "H" level standard / non-standard detection signal is U /
When input to D terminal, up & down counter 41
Performs a countdown operation sequentially at the rising edge of the clock, the count value becomes 7 (H) at the 10th clock, the Q4 output signal of the up & down counter 41 becomes the "L" level, and the "L" level representing the non-standard signal. The standard / non-standard determination result (standard / non-standard determination signal) is output from the non-standard determination circuit 40.

Then, the count value becomes 3 (H) at the 14th clock. Here, for example, the standard / nonstandard detection signal from the nonstandard detection circuit 8 to the U / D terminal is "H".
When it reaches the level, the up & down counter 41 switches to the count up operation, and the count value becomes 4 (H) at the 15th clock. When the standard / non-standard detection signal to the U / D terminal goes to "L" level, it goes up again.
The down counter switches to countdown operation, 1
The count value becomes 0 (H) at the ninth clock. After that, the RC output signal becomes "H" level, and this RC output signal is input to the enable terminal EN, so that the countdown operation is stopped.

In this way, the up & down counter 41
Since the Q4 output signal of is used as the determination signal of the non-standard determination circuit 40, the determination signal becomes “H” level when the count value becomes 8 (H) or more, and the input video signal conforms to the standard signal, that is, the NTSC system. The result of the determination that the signal is a signal is output. On the contrary, when the count value becomes 7 (H) or less, the output signal of the up & down counter 41 becomes "L" level, and it is determined that the input video signal is a non-standard signal, that is, a signal that does not comply with the NTSC system. The result is output. That is, the count threshold when the determination result changes from non-standard to standard is 8 (H), and the count threshold when the determination result changes from standard to non-standard is 7 (H).

Further, during the period when the count value of the up & down counter 41 is close to the threshold value, the standard / non-standard of the input video signal is frequently switched, or the S of the input video signal is changed.
The operation when the detection signal from the non-standard detection circuit 8 becomes unstable due to deterioration of / N or the like will be described. FIG. 15 shows an example of the operation in such a case. When the detection signal of the non-standard detection circuit 8 becomes the “H” level and is input to the U / D terminal at the rising edge of the 11th clock during the countdown of the up & down counter 41, the count value 6 ( The operation is switched from H) to the count-up operation. Then, at the rising edge of the 13th clock, the count value becomes its threshold value of 8 (H), and the determination signal becomes the "H" level. Further, when the detection signal becomes “L” level again at the rising edge of the 13th clock and is input to the U / D terminal, the countdown operation is started, and the count value becomes 8 (H) at the rising edge of the 14th clock. To 7 (H), and the determination signal also becomes "L" level. Similarly, when the detection signal becomes "H" level at the rising edge of the 14th to 15th clocks and is input to the U / D terminal, the count threshold value is also increased to 8 (H). After that, since the countdown is performed again, the determination signal also becomes the "H" level when the count value is 8 (H), and then returns to the "L" level again.

In this way, the up & down counter 41
When the detection signal from the non-standard detection circuit 8 becomes unstable in the period in which the count value of is close to the threshold value, the standard / non-standard determination result output from the non-standard determination circuit is also unstable. . That is, when the S / N of the input video signal is deteriorated and the nonstandard detection circuit 8 is erroneously detected, and the standard / nonstandard detection signal is incorrect, the standard / nonstandard determination signal from the nonstandard determination circuit 40 is output. Will be wrong. Then, when the output signals of the two-dimensional processing circuit 3 and the three-dimensional processing circuit 4 are switched by the switch circuit 5 by such an erroneous determination signal, an erroneously processed video signal is output from the output end 2. become.

Here, for example, the two-dimensional processing circuit 3 and the three-dimensional processing circuit are luminance / color signal (Y / C) separation filters for separating the luminance / color signal of the input video signal by two-dimensional and three-dimensional processing, respectively. Suppose there is. Then, even though the input video signal is a non-standard signal, a video signal that has been filtered by three-dimensional processing due to the erroneous determination that it is a standard signal is output via the switch circuit 5, and is output. The image signal causes adverse effects such as significant dot interference on the screen.

When the standard / non-standard of the input video signal is frequently switched in a short period of time, the standard / non-standard determination signal is also switched accordingly, and the two-dimensional processing and three-dimensional processing of the input video signal are frequently performed. Because it switches
The output video signal is adversely affected, such as visual discomfort.

[0019]

Since the conventional non-standard signal judging circuit is constructed as described above, the standard / non-standard of the input video signal is frequently switched in a short period of time, or the input video signal S / N deteriorates,
When the standard / non-standard detection signal becomes unstable, the standard / non-standard judgment signal is frequently switched along with it, or an incorrect judgment signal is output, and the processing is switched by the judgment signal. There was a problem that the signal was adversely affected.

The present invention has been made to solve the above problems, and the standard / non-standard of the input video signal is frequently switched in a short period of time, or the S of the input video signal is changed.
Even if the standard / non-standard detection becomes unstable due to deterioration of / N, the stable standard / non-standard determination result is output, and the processing for the video signal is switched according to the determination result. It is an object of the present invention to obtain a video signal processing device capable of suppressing an adverse effect on an output video signal in the case of being damaged.

[0021]

According to a first aspect of the present invention, there is provided a video signal processing circuit for detecting whether or not an input video signal is a standard signal conforming to a predetermined format, and counting a predetermined clock signal. The counting means sets the direction of the count based on the detection result of the detecting means, and outputs the determination result of whether or not the input video signal is the standard signal when the count value reaches a predetermined count value, and the determination means. It is characterized by further comprising reset means for resetting the count value of the counting means based on the result, and switching means for switching a plurality of types of processing for the input video signal based on the determination result.

According to the second aspect of the present invention, there is provided a video signal processing device which detects whether an input video signal is a standard signal conforming to a predetermined format, and a predetermined clock signal to count and detect the detection means. Counting means for setting the count direction based on the result and outputting a judgment result as to whether the input video signal is the standard signal or not when the count value reaches a predetermined count value, and when the judgment result is outputted. A count value setting means for detecting the count direction and setting or resetting a predetermined count value in the count means according to the count direction; and a plurality of types of processing for the input video signal based on the determination result. It is characterized in that a switching means for switching is provided.

According to a third aspect of the present invention, the video signal processing device further detects a plurality of types of count values of the counting means and the direction of counting when the count value is reached, and the input is performed according to the detection result. It is provided with a determination result output means for inverting and outputting the determination result as to whether or not the video signal is the standard signal.

[0024]

In the video signal processing device according to the present invention, it is detected whether or not the input video signal is a standard signal conforming to a predetermined format, a predetermined clock signal is counted, and the detection result of the detection means is obtained. Along with setting the count direction based on the original, when the predetermined count value is reached, the input video signal outputs a determination result of whether the standard signal, reset the count value of the counting means based on the determination result, Since a plurality of types of processing for the input video signal are switched based on the determination result, a margin until the output of the determination result is inverted is ensured without the count value remaining in the counting means after the output of the determination result. It is possible to switch the detection result in a short period of time or when it becomes unstable. It is possible to keep the process on the image signal stably.

In the video signal processing device according to the second aspect of the present invention, it is detected whether or not the input video signal is a standard signal conforming to a predetermined format, a predetermined clock signal is counted, and the detection result of the detection means is obtained. While setting the count direction based on the output, when the predetermined count value, the output result of the determination whether the input video signal is a standard signal, the direction of the count when the determination result is output is detected, Since the count value of the counting means is set or reset according to the direction of the count and a plurality of types of processing for the input video signal are switched based on the determination result, the count value is output to the counting means after the determination result is output. It is possible to secure a margin until the output of the above judgment result is reversed without leaving the above, and the above detection result may be switched in a short period of time. It is possible to stably maintain the process for the determination result and thereby switching the input video signal even when it becomes unstable.

In the video signal processing device according to the third aspect of the present invention, further, a plurality of types of count values of the counting means and the direction of counting when the count value is reached are detected, and the input video image is detected according to the detection result. Since the result of deciding whether a signal is a standard signal is inverted and output,
It is possible to arbitrarily set the counter value when the determination result is inverted according to the counting direction.

[0027]

【Example】

Example 1. FIG. 1 is a block diagram showing the configuration of a video signal processing apparatus which is an embodiment of the present invention. In the figure, 1
Is an input end to which a video signal is input, 2 is an output end from which a video signal is output, 3 is a two-dimensional processing circuit for performing two-dimensional processing in the frame on the input video signal, and 4 is a time axis for the input video signal A three-dimensional processing circuit for performing three-dimensional processing between frames including the added direction, 5 is a switch circuit for switching output signals from the two-dimensional processing circuit 3 and the three-dimensional processing circuit 4, and 6 is a clock to which a counting clock is input. An input terminal 7 is a non-standard signal determination circuit that detects whether or not the input video signal conforms to the NTSC system and determines whether or not the input video signal complies with the NTSC system based on the result. Is a non-standard signal detection circuit for detecting whether the input video signal complies with the NTSC system, 9 is an up & down counter with reset input, 10 is a reset circuit,
Reference numeral 101 is a D flip-flop, and 102 is an OR gate circuit. In the present embodiment, the non-standard decision circuit 7
Is constituted by the up & down counter 9 and the reset circuit 10, and the standard / non-standard judgment result is the Q4 output signal of the up & down counter 9.

Next, the operation will be described. First, similarly to the conventional example, the input video signal from the input terminal 1 is two-dimensionally processed within the frame by the two-dimensional processing circuit 3. Further, the input video signal is subjected to three-dimensional processing by the three-dimensional processing circuit 4 between frames including the time axis direction. And
The output signals of the two-dimensional processing circuit 3 and the three-dimensional processing circuit 4 are input to the switch circuit 5. On the other hand, the input video signal from the input terminal 1 is also input to the non-standard determination circuit 7 and the NTS
Whether or not the input video signal conforms to the NTSC system is determined based on the result of the detection of whether or not the C system complies.

In the non-standard decision circuit 7, first, the non-standard detection circuit 8 detects whether or not the input video signal complies with the NTSC system. Here, the non-standard detection circuit 8
In the same manner as in the conventional example, the NTS system (standard system) -compliant video signal color subcarrier has an opposite phase for each frame, and the input video signal is
Outputs the standard / non-standard detection signal of the "H" level for the detection result of the standard signal conforming to the C system and the "L" level of the non-standard signal not conforming to the NTSC system for each frame. To do.

The standard / non-standard detection signal is input to the U / D terminal of the up & down counter 9. The up & down counter 9 performs a count-up operation when the U / D- terminal is at "H" level, and a count-down operation when the U / D- terminal is at "L" level.
The standard / non-standard detection signal sets (controls) the direction of counting. On the other hand, the counting clock from the counting clock input terminal 6 having one frame period of the video signal as one cycle is input to the clock terminal T of the up & down counter 9, and the up & down counter 9 rises at this clock. Performs count operation.
In addition, the ripple carry output terminal RC has Q4 to Q
When the count value representing 1 in hexadecimal (H) becomes F (H) or 0 (H), the RC signal of "H" level is output. The enable terminal EN is a control signal input terminal for the counting operation, and the counting operation is stopped when the EN signal of "H" level is input. Then, the Q4 output signal of the up & down counter 31 is output from the non-standard determination circuit 7 to the switch circuit 5 as a standard / non-standard determination signal.

The switch circuit 5 selects (switches) the output signal of the three-dimensional processing circuit 4 and outputs it to the output end 2 when the standard / non-standard determination signal is at the "H" level representing the standard signal. , The output signal of the two-dimensional processing circuit 3 is selected (switched) and output to the output terminal 2 when it is at the “L” level indicating a non-standard signal.

On the other hand, the reset circuit 10 comprises, for example, a D flip-flop 101 and an OR gate 102, and the Q4 output signal of the up & down counter 9 is input to the D input terminal of the D flip-flop 101 and to the clock terminal T. It is delayed by one clock by the counting clock, and its inverted output Q is ORed by the OR gate 102.
(Logical sum) is taken. In this way, when the Q4 output signal of the up & down counter 9 changes from "H" level to "L" level, the reset circuit 10 outputs a reset signal of one clock cycle width for resetting the up & down counter 9. Occur.

Next, FIG. 2 is a timing chart of signals at various parts in the non-standard decision circuit 7. It is assumed that the initial count value is F (H). First, the standard / non-standard detection signal from the non-standard signal detection circuit 8 is input to the U / D terminal of the up & down counter 9, but the count value does not advance when this input signal is at "H" level. Therefore, the initial value F (H) remains unchanged. Next, when the "L" level standard / non-standard detection signal is input to the U / D terminal,
The up & down counter 9 sequentially performs a countdown operation at the rising edge of the clock. When the count value changes from 8 (H) to 7 (H), which is the threshold value in the countdown direction at the 10th clock, the count output Q4 of the up & down counter 9 becomes "L" level, and the determination result indicating the non-standard signal is obtained. The standard / non-standard determination signal of "L" level is output.

On the other hand, as described above, the Q4 output signal of the up & down counter 9 is also output to the reset circuit 10 so that it is at the "H" level for a period corresponding to one clock cycle width from its falling point. Generate a reset signal. The reset signal is the OR gate 102.
It will be delayed for some time. Therefore, the rising edge of the reset signal is slightly behind the rising edge of the clock. And this reset signal is up &
The count value is input to the reset terminal RST of the down counter 9, and the count value of the up & down counter 9 is set to 0 (H) at the time when the clock rises with the reset signal at the “L” level, that is, at the time when the 11th clock rises. (The count value is reset).

After that, due to a malfunction of a device for inputting a video signal to the input terminal 1, the nonstandard signal is switched to a standard signal for a relatively short period during nonstandard signal input, or the S / N of the input video signal is deteriorated, etc. The operation in the case where the standard / non-standard detection signal becomes unstable because the detection result representing the standard signal is output although the input video signal is a non-standard signal in 8 will be described. In FIG.
For example, the 12th to 13th clock periods correspond to such a case. When the detection signal of the non-standard detection circuit 8 becomes the “H” level which represents the standard signal and is input to the U / D_ terminal of the up & down counter 9, the reset value 0 (H) is output at the 12th to 13th clocks. After being counted up to 1 (H), it is counted down to 0 (H) again. Further, when the input signal to the U / D terminal becomes "H" level near the 17th clock, the up & down counter 9 sequentially counts up from 0 (H) at each clock rising, and the count value becomes 8 ( H), Q
The four outputs become the “H” level, and the determination result representing the standard signal is output.

FIG. 3 shows the count value for the transition of the clock with the passage of time in the above operation.
The dotted line in the figure represents the count value in the countdown of the conventional example. As described above, even if the standard / non-standard detection signal becomes unstable after the determination result becomes “L” level by the countdown operation, the threshold value in the countdown direction is 7 (H) as shown in FIG. As described above, since the count value is once reset and the count value does not remain, the margin until the threshold value 8 (H) exceeds the threshold value becomes larger than the conventional one even if the count-up operation is switched. Therefore, the standard of the input video signal /
Even if the standard / nonstandard detection switches to "H" level instability due to frequent switching of the nonstandard in a short period of time or deterioration of the S / N of the input video signal, the nonstandard judgment circuit It is possible to stably output the determination result of the “L” level representing the non-standard signal output from the output terminal 7, and suppress the adverse effect on the output video signal when the processing for the video signal is switched by the determination result. it can.

In addition, the standard / non-standard detection signal goes from "L" level representing the non-standard signal to "H" representing the standard signal.
When switching to the level, the standard / non-standard detection signal to the U / D terminal becomes "H" level, and when the count-up starts, the count-up remaining from the up & down counter 9 should start the count-up. Because,
Depending on the count value, the time required for the determination result from the non-standard determination circuit 7 to reach the "H" level representing the standard signal varies. However, according to the configuration of this embodiment, since the count value is once reset as described above, the U / D
The detection signal to the ￣ terminal becomes “H” level and the remaining count value at the time of starting the count-up can be suppressed to a small value, and when the non-standard signal is switched to the standard signal, the judgment result indicating the standard signal is output. It is possible to suppress the variation in the time until the start. In the present embodiment, for example, as shown after the 17th clock in FIG. 2, when the standard / non-standard detection signal is switched to the “H” level, the “H” level determination signal representing the standard signal is output. It is possible to suppress the variation by setting the time until it is set to about 8 frame periods.

Example 2. FIG. 4 is a block diagram showing the configuration of a video signal processing device which is another embodiment of the present invention. Two
0 is a non-standard judgment circuit, 21 is an up & down counter with a load (LD) terminal, 30 is a judgment of the counting direction and the state of the count value of the up & down counter 21, and the count value is set to the up & down counter 21. This is a count value setting circuit. FIG. 5 is a block diagram of the count value setting circuit 30, wherein 301 and 302 are 4-input AND gate circuits having partially inverted inputs, and 303 and 3.
04 is a D flip-flop, and 305 and 306 are AN
D gate circuit, 307 is an OR gate circuit, and 308 is a switch circuit. Since the other configurations are the same as those described in the first embodiment, detailed description thereof will be omitted here.

Next, the operation will be described. Similar to the first embodiment, the detection signal of the non-standard detection circuit 8 and the counting clock input from the clock input terminal 6 are input to the U / D-terminal and the clock terminal T of the up & down counter 21, respectively. . A ripple carry (RC) output signal is also input to the enable terminal EN.
Further, in the up & down counter 21, when a signal is input to the LD terminal, the count value is set (loads the count value) to the count value (load value) input to the load value input terminals D1 to D4.

The count value setting circuit 30 is constructed, for example, as shown in FIG. 5, and AND gate circuits 301 and 3 are provided.
02 is an "H" level output signal when the count outputs Q1 to Q4 from the up & down counter 21 are 7 (H) and 8 (H), respectively. The output signals of the AND gate circuits 301 and 302 are delayed by one clock period in the D flip-flops 303 and 304, respectively, and input to the AND gates 305 and 306.
The AND gate circuit 305 is a D flip-flop 303.
And the output signal of the AND gate circuit 302 is ANDed (logical product) to obtain the up & down counter 21
It is detected that the count value of 7 has changed from 7 (H) to 8 (H), and an "H" level signal is output as a 7 → 8 detection signal.

Similarly, the AND gate circuit 306 takes the AND (logical product) of the output signals of the D flip-flop 304 and the AND gate circuit 301 to obtain 8 → 7.
Output the detection signal. In other words, the AND gate circuit 3
05 detects the count direction when the count value becomes 8 (H) which is the count threshold value in the count-up direction,
If it is in the count-up direction, an "H" level signal is output. Similarly, the AND gate 306 detects the count direction when the count value becomes 7 (H), which is the threshold value in the countdown direction, and outputs the signal at the “H” level if it is the countdown direction.

The OR gate circuit 307 operates 7 → 8.
By taking the OR (logical sum) of the detection signal and the 8 → 7 detection signal, the count value of the up & down counter 21 changes from 7 (H) to 8 (H) or from 8 (H) to 7
The change to (H) is detected, and the detection signal is output to the LD terminal of the up & down counter 21 as an LD signal. On the other hand, the switch circuit 308 receives the 7 → 8 detection signal from the AND gate circuit 305 and switches from the 0 (H) side to the F (F) side.
It is switched to the (H) side.

As described above, the count value setting circuit 30 causes the up & down counter 21 to set the count value to 7
When (H) changes to 8 (H) or from 8 (H) to 7 (H), the "H" level LD signal is input to the LD terminal, and when the former change occurs, the load value F
(H) is set as the count value (the count value is set), and when the latter change occurs, the load value 0
(H) is set as the count value (counter value is reset).

Next, the non-standard judgment circuit 20 when the up & down counter 21 performs a countdown operation
FIG. 6 shows a timing chart of signals in each part in FIG.
The initial value of the counter is F (H). First, the count value does not advance during the "H" level period in which the standard / non-standard detection signal to the U / D terminal indicates the detection result of the standard signal, and therefore remains at F (H). Then, when the standard / non-standard detection signal to the U / D terminal becomes "L" level, the countdown operation is performed. Then, when the count value changes from 8 (H) to 7 (H) by the 10th clock, the load value 0 is output from the count value setting circuit 30 as described above.
(H) and the LD signal are output and input to the load value input terminals D4 to D1 and the LD terminal of the up & down counter 21, respectively. And the next clock, 11
The count value becomes the load value 0 (H) by the second clock (the count value is reset).

After that, even if the non-standard detection signal becomes unstable due to S / N deterioration of the input video signal or the like, it does not exceed the count threshold value 8 (H) in the count-up direction and is output from the non-standard determination circuit 20. As a result of the determination, the "L" level state representing the non-standard signal can be stably maintained.

Further, the non-standard judgment circuit 2 when the up & down counter 21 performs a count up operation
FIG. 8 shows a timing chart of signals at various parts in 0. The initial value of the counter is 0 (H). First,
The count value does not advance during the period of "L" level in which the standard / non-standard detection signal to the U / D terminal indicates the detection result of the non-standard signal, and therefore remains 0 (H). Then, when the standard / non-standard detection signal to the U / D terminal becomes "H" level, a count-up operation is performed. Then, when the count value changes from 7 (H) to 8 (H) by the 10th clock, the count value setting circuit 30 loads the load value F (H) as described above.
And the LD signal are output, and are input to the load input terminals D4 to D1 and the LD terminal of the up & down counter 21, respectively. Then, the count value becomes the load value F (H) at the next clock, that is, the 11th clock (the count value is set).

After that, even if the non-standard detection signal becomes unstable due to S / N deterioration of the input video signal or the like, it does not exceed the count threshold value 7 (H) in the countdown direction and is output from the non-standard determination circuit 20. As a result of the determination, the "H" level state representing the standard signal can be stably held.

FIG. 7 and FIG. 9 show the count values with the passage of time (transition of clock) in the above countdown and countup operations, respectively. The dotted line in the figure represents the count value in the conventional example. After the standard / non-standard determination results become the “L” level and the “H” level by the countdown and countup operations, for example, 1 shown in FIG. 6 and FIG.
When the non-standard detection signal becomes unstable as in the period of the 1st to 16th clocks, in the countdown operation, the count value is set to 7 (H) which is the threshold value in the countdown direction as shown in FIG. Is loaded (set) with 0 (H), and in the count-up operation, the count value is loaded (set) with F (H) as described above at 8 (H) which is the threshold value in the count-up direction as shown in FIG. ) Will be done.

Therefore, the count value is set to 0 (H) and F (H), respectively, after the standard / non-standard determination results become "L" level and "H" level by the countdown and countup operations, respectively. Since the count value does not remain (the count value is reset and set) and the count value does not remain, even if the count operation is switched in the opposite direction, that is, from the down direction to the up direction and from the up direction to the down direction, the threshold value of
The margin until exceeding (H) and 7 (H) becomes larger than that of the conventional one.

Therefore, the standard / non-standard of the input video signal is frequently switched in a short period of time, the S / N of the input video signal is deteriorated, and the standard / non-standard detection is switched instable. Also, it is possible to stably output the determination result indicating the standard signal / non-standard signal, and it is possible to suppress the adverse effect on the output video signal when the processing for the video signal is switched by the determination result.

In addition, also in the present embodiment, as in the first embodiment, when the standard / non-standard detection signal is switched, the count value is set or reset without remaining, so that the determination signal corresponding thereto is output. It takes about 8 frame periods to perform the processing, and the variation can be suppressed.

Although the signal from the Q4 output of the up / down counter is used as the output standard / non-standard determination result in each of the above-described embodiments, a gate circuit is provided to gate any or all of the Q1 to Q4 output signals. By outputting the output signal of this gate circuit as a determination result indicating a standard signal / non-standard signal, the count threshold values in the count-up and count-down directions can be set to values other than 8 (H) and 7 (H). , For example, if the count-up threshold value is reduced, the transition from the determination result indicating the non-standard signal to the determination result indicating the standard signal can be made faster, and the determination result indicating the standard signal can be output more stably, and the threshold value can be increased. By doing so, the transition from the judgment result showing the standard signal to the judgment result showing the non-standard signal is quick, and the judgment result showing the non-standard signal is more stable. It is possible to output. As described above, depending on the requirements of the system in which the non-standard decision circuit is used, when it is desired to output the standard / non-standard decision result more stably or more quickly, the corresponding count value May be output as the determination result.

Embodiment 3 In each of the above embodiments, the judgment result of the non-standard judgment circuit is taken from the count output Q4 of the up & down counter, the threshold value in the count-up direction is 8 (H), and the threshold value in the count-down direction is 7 (H). ), The count outputs Q1 to Q4 of the up & down counter are described.
On the other hand, by further providing an output circuit as shown in FIG. 10, it is possible to arbitrarily set the count threshold in the count-up and count-down directions. In FIG. 10, for example, the count threshold in the count-up direction is D (H) and the threshold in the count-down direction is 2 (H). In the figure, 31 and 32 are up / down counters 21.
D (H) detection circuit and 2 (H) detection circuit for detecting that the count value becomes D (H) in the count-up direction and 2 (H) in the count-down direction by the count outputs Q1 to Q4 of It is an RS (reset set) flip-flop.

Next, the operation will be described. The D (H) detection circuit 31 detects that the count values have become D (H) in the count-up direction by the count outputs Q1 to Q4 of the up & down counter 21, and outputs an "H" level detection signal. Output. Similarly, the 2 (H) detection circuit 32 detects that the count becomes 2 (H) in the countdown direction, and outputs a detection signal of "H" level. Then, the set / reset flip-flop 33 sets the output Q when the “H” level detection signal is input to the set signal input terminal S from the D (H) detection circuit 31, and the input video signal is the standard signal. Then, the non-standard determination signal of "H" level indicating that is is output (the non-standard determination signal is inverted). Then, the nonstandard judgment signal from the output Q is kept at "H" until the "H" level signal is inputted to the reset signal input terminal R.
Hold on to the level.

On the other hand, the set / reset flip-flop 33 has a 2 (H) detection circuit 3 at the reset signal input terminal R.
When the "H" level detection signal is input from 2, the output Q
Is reset, and an "L" level non-standard determination signal indicating that the input video signal is a non-standard signal is output (the non-standard determination signal is inverted). Then, the non-standard determination signal is held at the “L” level until the “H” level signal is input to the reset signal input terminal R.

FIG. 11 shows a characteristic diagram of the nonstandard decision signal with respect to the count value of the up & down counter 21. In this way, the threshold value in the count-up direction is set to D
(H), the threshold value in the countdown direction is set to 2 (H),
By providing the hysteresis characteristic, it is possible to further increase the margin until the determination result of the standard / nonstandard signal is inverted, and even if the standard / nonstandard detection signal from the nonstandard detection circuit 8 becomes unstable. , It is possible to more stably output the standard / non-standard determination result of the input video signal.

In each of the above embodiments, the video signals from the two-dimensional and three-dimensional processing circuits 3 and 4 are switched by the switch circuit 5 and output based on the determination result of the non-standard determination circuit. However, the processing mode of the input video signal in one processing circuit may be directly switched according to the above determination result, and the processing for the switched video signal is limited to two-dimensional processing and three-dimensional processing. is not.

[0058]

Since the present invention is configured as described above, it has the following effects. The video signal processing device according to the invention of claim 1 stably outputs the standard / non-standard determination result even when the standard / non-standard detection result in the input video signal switches or becomes unstable in a short period of time. It is possible to suppress the adverse effect on the output video signal when the processing for the video signal is switched according to the determination result.

According to the second aspect of the present invention, there is provided the video signal processing apparatus, wherein even when the standard / non-standard detection result in the input video signal is switched or becomes unstable in a short period of time,
It is possible to stably output the non-standard determination result, and it is possible to suppress the adverse effect on the output video signal when the processing for the video signal is switched by the determination result.

The video signal processing device according to the invention of claim 3 can further arbitrarily set the counter value when the standard / non-standard determination result of the input video signal is inverted depending on the direction of counting. Even if the standard / non-standard detection result of the input video signal is switched or becomes unstable in a short period of time, the margin until the standard / non-standard determination result is reversed can be increased. It is possible to more stably output the nonstandard determination result, and it is possible to suppress the adverse effect on the output video signal when the processing for the video signal is switched by the determination result.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a video signal processing apparatus that is Embodiment 1 of the present invention.

FIG. 2 is a timing chart of signals of respective parts in the video signal processing device according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram showing changes in the count value with respect to clock transitions in the video signal processing device according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a video signal processing device which is Embodiment 2 of the present invention.

FIG. 5 is a circuit configuration diagram showing a configuration of a count value setting circuit of a video signal processing device which is Embodiment 2 of the present invention.

FIG. 6 is a timing chart of signals at respective parts during countdown in the video signal processing device according to the second embodiment of the present invention.

FIG. 7 is an explanatory diagram showing changes in the count value with respect to clock transitions in the video signal processing device according to the second embodiment of the present invention.

FIG. 8 is a timing chart of signals of respective parts at the time of counting up in the video signal processing device which is Embodiment 2 of the present invention.

FIG. 9 is an explanatory diagram showing changes in the count value with respect to clock transitions in the video signal processing device that is Embodiment 2 of the present invention.

FIG. 10 is a block diagram showing a configuration of a video signal processing device that is Embodiment 3 of the present invention.

FIG. 11 is a characteristic diagram of the standard / non-standard determination signal with respect to the count value in the video signal processing device according to the third embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration of a conventional video signal processing device.

FIG. 13 is a timing chart of signals of respective parts at the time of counting up in the conventional video signal processing device.

FIG. 14 is a timing chart of signals at respective parts during countdown in the conventional video signal processing device.

FIG. 15 is a timing chart of signals at respective parts during countdown in the conventional video signal processing device.

[Explanation of symbols]

3 2 dimensional processing circuit, 4 3 dimensional processing circuit, 5 switch circuit, 7 non-standard judgment circuit, 8 non-standard detection circuit, 9
Up & down counter, 10 reset circuit, 20
Non-standard judgment circuit, 21 up & down counter, 3
0 count value setting circuit, 31 D (H) detection circuit, 3
22 (H) detection circuit, 33 RS flip-flop.

Front page continued (72) Inventor Kazuhiro Kurisaki 1 Baba Institute, Nagaokakyo, Kyoto Prefecture Mitsubishi Electric Co., Ltd. Kyoto Works (72) Inventor Masaki Yamakawa 1 Nagabakyo Baba Institute, Kyoto Mitsubishi Electric Corporation Kyoto In-house (56) Reference JP-A-2-252390 (JP, A) JP-A-6-225321 (JP, A) JP-A-7-67071 (JP, A) JP-A-1-233897 (JP, A) ) JP-A-7-115660 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 9/64 H04N 5/14 H04N 5/46 H04N 9/79

Claims (3)

(57) [Claims] 1. A detection means for detecting whether or not an input video signal is a standard signal conforming to a predetermined format, and a predetermined clock signal is counted, and the counting direction is set based on the detection result of the detection means. At the same time, a count means for outputting a determination result of whether the input video signal is the standard signal when a predetermined count value is obtained, and a reset means for resetting the count value of the counting means based on the determination result, A video signal processing apparatus comprising a switching means for switching a plurality of types of processing for an input video signal based on the above determination result. 2. A detecting means for detecting whether or not an input video signal is a standard signal conforming to a predetermined format, and a predetermined clock signal is counted, and the counting direction is set based on the detection result of the detecting means. At the same time, a count means for outputting a judgment result as to whether the input video signal is the standard signal when the count value reaches a predetermined count value, and a direction of the count when the judgment result is outputted are detected, A video signal, comprising: a count value setting means for setting or resetting the count value of the counting means in accordance with the direction, and a switching means for switching a plurality of types of processing for the input video signal based on the determination result. Processing equipment. 3. A plurality of types of count values of the counting means and a count direction when the count value is reached are detected, and a determination result as to whether or not the input video signal is the standard signal is determined according to the detection result. The video signal processing device according to claim 1 or 2, further comprising a determination result output means for inverting and outputting.