JP3522926B2 - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a contact hole can be formed by a self-alignment method without deteriorating electrical characteristics and a method for manufacturing the semiconductor device.

[0002]

2. Description of the Related Art With the recent high integration of semiconductor devices, the pattern size has been miniaturized and the margin for misalignment during photolithography has been reduced. Therefore, at the time of forming the contact hole, a mask pattern having a size larger than the width of the semiconductor substrate exposed in the actual contact hole, that is, the contact hole size is formed, and the surrounding film is etched without any trouble even if it is etched. A self-alignment method of forming a contact hole by utilizing selectivity has been proposed.

5 and 6 are sectional views showing a method of manufacturing a contact hole by the self-alignment method.
Next, a method of manufacturing this semiconductor device will be described. First, the element isolation region 2 is formed on the semiconductor substrate 1, and the gate insulating film 3 is laminated on the semiconductor substrate 1. Next, the gate electrode 4 and the protective film 5 are formed at desired locations on the semiconductor substrate 1, and then impurities are implanted into the semiconductor substrate 1 using the protective film 5 and the element isolation region 2 as a mask to form a first diffusion layer 6 is formed (FIG. 5A).

Next, sidewalls 7 are formed on the sidewalls of the gate electrode 4 and the protective film 5, and then the first diffusion layer is formed on the semiconductor substrate 1 using the protective film 5, the element isolation region 2 and the sidewall 7 as a mask. Impurities are implanted at a concentration higher than that of the impurities of No. 6 to form the second diffusion layer 8, and the LDD structure 9 is formed of the first diffusion layer 6 and the second diffusion layer 8 (FIG. )). Next, the silicon oxide film 10 and the etching stopper film 11 are sequentially laminated on the entire surface. Next, a silicon oxide film is laminated and etched back by RIE or the like to form a planarized interlayer insulating film 12 (FIG. 5).
(C)).

Next, a resist is applied on the interlayer insulating film 12 and patterned by photolithography to form a resist film 13. Next, using the resist film 13 as a mask and the etching stopper film 11 as an etching stopper, the interlayer insulating film 12 is dry-etched using, for example, RIE to form an opening 14 (FIG. 6A). At this time, the etching stopper film 11 functions as an etching stopper but is accompanied by some etching. The etching stopper film 11 has a flat portion A on the protective film 5,
There is an inclined portion B on the sidewall 7.
Therefore, the etching stopper film 11 is etched faster in the inclined portion B than in the flat portion A due to the sputtering of ions used for etching.

Next, using the resist film 13 as a mask, the etching stopper film 11 and the silicon oxide film 10 exposed in the opening 14 are etched until the semiconductor substrate 1 is exposed to form a contact hole 15. Next, the resist film 13 is removed by a removing device, and the electrode film 16 to be the bit line is laminated via the contact hole 15 (FIG. 6B). As described above, when the inclined portion B is present in the etching stopper film 11, the inclined portion B is more easily etched than the flat portion A, so that the etching stopper film 11 does not sufficiently function as an etching stopper in the inclined portion B. The protective film 5 and the side wall 7 as an insulating film surrounding the gate electrode 4 are etched and thinned. Therefore, a short circuit may be caused due to a poor withstand voltage between the gate electrode 4 and the electrode film 16, and the gate electrode 4 may not operate normally.

As a method for easily avoiding this, the etching stopper film 11 or the silicon oxide film 1 is used.
A method of making the film thickness of 0 sufficiently thick is also conceivable. But,
In response to such a method, the gate electrode 4 and the electrode film 1
Although a short circuit with 6 can be prevented, the step difference on the entire surface becomes extremely large, which causes a problem in the process in the subsequent process.

Conventionally, in order to solve this, the following 2
One method proposal has been made. For example, Japanese Patent Laid-Open No. 6-1
The semiconductor device disclosed in Japanese Patent No. 51352 will be described. 7 and 8 are cross-sectional views showing a conventional semiconductor device. Next, a method of manufacturing this semiconductor device will be described with reference to the above conventional example. First, as shown in FIG. 5A, the element isolation region 2, the gate insulating film 3, the gate electrode 4, the protective film 5, and the first diffusion layer 6 are formed on the semiconductor substrate 1 through the same steps as in the conventional example. Form. Next, the etching stopper film 17 is laminated on the entire surface (FIG. 7A).

Next, a silicon oxide film 18 is laminated on the etching stopper film 17 (FIG. 7B). Next, the silicon oxide film 18 is etched back by using, for example, RIE to etch the etching stopper film 17 and the silicon oxide film 1.
A side wall 19 of 8 is formed. Next, using the element isolation region 2, the sidewall 19 and the etching stopper film 17 as a mask, impurities are injected into the semiconductor substrate 1 at a concentration higher than that of the first diffusion layer 6 to form the second diffusion layer 20. Then, the LDD structure 21 is formed by the first diffusion layer 6 and the second diffusion layer 20 (FIG. 7).
(C)). Next, the interlayer insulating film 22 is laminated on the entire surface.

Next, a resist is applied on the interlayer insulating film 22 and patterned by photolithography to form a resist film 23 (FIG. 7 (d)). Next, using the resist film 23 as a mask and the etching stopper film 17 as an etching stopper, the interlayer insulating film 22 is dry-etched using, for example, RIE until the semiconductor substrate 1 is exposed to form a contact hole 24 (FIG. 8). (A)). On this occasion,
The silicon oxide film 18 as the sidewall 19 is thinned. Next, the resist film 23 is removed by a removing device, and the electrode film 25 to be a bit line is formed in the contact hole 24.
It is laminated via (FIG. 8B).

When the etching stopper film 17 is formed in this manner, the etching stopper film 17 is flat in all places, so that the etching stopper film 17 is not unnecessarily etched as described above. However, in reality, it is difficult to form the sidewall 19 while leaving the etching stopper film 17 on the protective film 5 in the step of forming the sidewall 19, and as shown in FIG. The upper etching stopper film 17 is etched.

Therefore, if the etching stopper film 17 on the protective film 5 is lost and the contact hole 24 as shown in FIG. 5 is etched and thinned. Therefore, a short circuit may occur due to a poor breakdown voltage between the gate electrode 4 and the electrode film 25, and the gate electrode 4 may not operate normally. Further, since the etching stopper film 17 has a portion directly in contact with the semiconductor substrate 1, the stress of the etching stopper film 17 causes crystal defects in the semiconductor substrate 1.

Next, a semiconductor device disclosed in, for example, Japanese Patent Laid-Open No. 5-13434 will be described. FIG. 10 is a cross-sectional view showing a conventional semiconductor device. Next, a method of manufacturing this semiconductor device will be described with reference to the above conventional example. First, the element isolation region 2, the gate insulating film 3, the gate electrode 4, the protective film 5, and the first diffusion layer 6 are formed on the semiconductor substrate 1 as shown in FIG. Form. Next, a silicon oxide film 26 and an etching stopper film 27 are sequentially laminated on the entire surface. Next, a silicon oxide film is laminated on the etching stopper film 27 and, for example, R
Etch back is performed using IE to form a planarized interlayer insulating film 28 (FIG. 10A).

Next, a resist is applied on the interlayer insulating film 28 and patterned by photolithography to form a resist film 29. Next, using the resist film 29 as a mask and the etching stopper film 27 as an etching stopper, the interlayer insulating film 28 is dry-etched using, for example, RIE to form an opening 30 (FIG. 10B). At this time, since the etching stopper film 27 is flat in all places, the etching stopper film 2 as described above is formed.
7 is no longer unnecessarily etched.

Next, using the resist film 27 as a mask, the silicon oxide film 26 and the etching stopper film 27 exposed in the opening 30 are etched until the semiconductor substrate 1 is exposed to form a contact hole 31 (FIG. 10).
(C)). Next, the resist film 29 is removed by a removing device, and the electrode film 32 to be the bit line is formed in the contact hole 31.
It is laminated via (FIG. 10D).

When the etching stopper film 27 is formed in this way, the etching stopper film 27 is flat in all places, so that the etching stopper film 27 is not unnecessarily etched as described above. Further, since the side wall is not formed, the etching stopper film 27 on the protective film 5 does not disappear before being used as an etching stopper. However, since the side wall is not formed, there is only one impurity diffusion layer and it is not possible to have an LDD structure.

FIG. 11 shows a gate voltage (Vg) and a drain voltage (Vd) for each gate length (L) of a transistor having a silicon oxide film of a semiconductor substrate having only one impurity and a transistor having an LDD structure. 2.5
It shows the current value (lds) between the drain and the source when V and the substrate side voltage (Vb) of 1 V are applied. As can be seen by comparing the current values (lds) between the drains / sources, that is, the current drivability with the same gate length, the current drivability of the transistor having only one impurity layer is better than that of the LDD structure transistor. Inferior Therefore, for example, if the transistors used in the peripheral circuit portion of the DRAM are formed in this way, the access time becomes long and the performance of the DRAM deteriorates.

[0018]

Since the conventional semiconductor device is constructed as described above, when the contact hole is formed by the self-alignment method, deterioration of the electrical characteristics of the semiconductor device cannot be denied. was there.

The present invention has been made to solve the above problems, and a semiconductor device in which a contact hole can be formed by a self-alignment method without deteriorating the electrical characteristics of the semiconductor device, and It is an object to provide a method for manufacturing a semiconductor device.

[0020]

[Means for Solving the Problems] Claim 1 according to the present invention
In the semiconductor device described above, a first diffusion layer formed by implanting impurities into both regions of a semiconductor substrate having a first region and a second region, and first diffusion layers on the semiconductor substrate. A plurality of first wiring layers formed on the interlayers with a gate insulating film interposed therebetween and a first wiring layer formed on the first region and sequentially stacked so as to cover the first wiring layer. A silicon oxide film and an etching stopper film, a sidewall formed by sequentially laminating a silicon oxide film, an etching stopper film and an insulating film on the sidewall of the first wiring layer formed on the second region, and a sidewall. A second diffusion layer, which is formed by implanting impurities into the upper part of the semiconductor substrate around, and has an impurity concentration higher than that of the first diffusion layer, the etching stopper film, the insulating film, and the semiconductor substrate, and
An interlayer insulating film formed by planarizing the upper surface and a first insulating film formed by penetrating the interlayer insulating film, the etching stopper film and the silicon oxide film until reaching the first diffusion layer formed on the first region. A first contact hole, a second contact hole formed through the interlayer insulating film until reaching the second diffusion layer formed on the second region, and each contact hole. And a second wiring layer.

A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the first region is a memory cell forming portion and the second region is a peripheral circuit forming portion.

A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first or second aspect, wherein the interlayer insulating film is a silicon oxide film and the etching stopper film is a silicon nitride film.

A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the third aspect, wherein the thickness of the etching stopper film is 300 angstroms to 1000 angstroms, and the thickness of the silicon oxide film formed below the etching stopper film. Is 150 angstroms to 500 angstroms.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device, the first wiring is formed on both regions of the semiconductor substrate having the first region and the second region via the gate insulating film. A layer is formed, impurities are injected into the semiconductor substrate using each first wiring layer as a mask to form a first diffusion layer, and each first
A silicon oxide film, an etching stopper film, and an insulating film are sequentially stacked so as to cover the wiring layer, and the first region is covered with a resist film. Then, the insulating film, the etching stopper film, and the silicon film on the first wiring layer formed on the second region are anisotropically etched to remain only on the side wall of the first wiring layer. Silicon oxide film on the sidewall of the layer,
A sidewall formed of an etching stopper film and an insulating film is formed, impurities are implanted into the semiconductor substrate by using the sidewall, the first wiring layer, and the resist film as a mask, and the impurity concentration is higher than that of the first diffusion layer. A diffusion layer is formed, the resist film is removed, each first wiring layer,
Top surface while covering the sidewall and semiconductor substrate
And a flattened interlayer insulating film is laminated. Then, the interlayer insulating film and the insulating film corresponding to the first diffusion layer on the first region are etched by using the etching stopper film as an etching stopper to form an opening, and the second insulating layer on the second region is formed. The corresponding interlayer insulating film is etched on the diffusion layer until the second diffusion layer is exposed to form a contact hole, and the etching stopper film and the silicon oxide film exposed at the opening are exposed to the first diffusion layer. Etching is performed to form contact holes, and the second wiring layer is formed through each contact hole.

[0025]

DETAILED DESCRIPTION OF THE INVENTION

Embodiment 1. Embodiments of the present invention will be described below with reference to the drawings. 1 to 4 show Embodiment 1 of the present invention.
3 is a cross-sectional view showing the resist of FIG. Then, the first embodiment
The method of manufacturing a semiconductor device will be described using a DRAM having a memory cell portion (left side on the paper surface) as a first area and a peripheral circuit portion (right side on the paper surface) as a second area.
First, similarly to the conventional case, the element isolation region 2 is formed on the semiconductor substrate 1, and, for example, a silicon oxide film is deposited on the semiconductor substrate 1 to form the gate insulating film 3. Next, for example, a polycrystalline silicon film and a silicon oxide film are sequentially deposited,
Etching is performed using a resist film patterned by photoengraving as a mask to form a gate insulating film 3 having a predetermined pattern, a gate electrode 4 as a first wiring layer, and a protective film 5 (FIG. 1A). . At this time, the distance between the gate electrodes 4 on the memory cell formation portion is smaller than the distance between the gate electrodes 4 on the peripheral circuit formation portion.

Next, using the gate electrode 4 as a mask, phosphorus, for example, is ion-implanted as an impurity to form a first diffusion layer 6 serving as an n-type source / drain region (FIG. 1).
(B)). The impurity implantation amount at this time is set to a low concentration so that the effect of suppressing the short channel effect can be obtained.

Next, a silicon oxide film 33 is deposited, for example, 150 angstrom to insulate the entire surface, and an etching stopper film 34 made of a nitride film, for example, is deposited 500 angstrom on the silicon oxide film 33. Next, the insulating film 35 is deposited on the etching stopper film 34 (see FIG. 1).
(C)). At this time, the silicon oxide film 33 plays a role of the etching stopper film 34 made of a nitride film directly on the semiconductor substrate 1.
This is to prevent the gate electrode 4 and the gate electrode 4 from coming into contact with each other. The presence of the silicon oxide film 33 reduces crystal defects due to stress stress between the etching stopper film 34 and the semiconductor substrate 1, and improves the hot carrier resistance of the gate electrode 4.

Next, a resist is applied, and the resist film 36 is left only on the memory cell forming portion by photolithography. Next, using the resist film 36 as a mask, the insulating film 35 is etched back by using, for example, RIE, and the silicon oxide film 33 is etched.
A side wall 37 composed of a, the etching stopper film 34a and the insulating film 35a is formed only on the side walls of the gate electrode 4 and the protective film 5 on the peripheral circuit forming portion. Next, impurities are implanted into the semiconductor substrate 1 using the sidewalls 37, the gate electrodes 4 and the resist film 36 as a mask,
A second diffusion layer 38 having a concentration higher than the impurity concentration of the first diffusion layer 6 is formed, and an LDD structure 39 composed of the first diffusion layer 6 and the second diffusion layer 38 is formed on the peripheral circuit formation portion. It is formed only around the gate electrode 4 (FIG. 2A).

Next, the resist film 36 is removed by a resist removing device, and a silicon oxide film is deposited on the entire surface.
It is etched back by IE or the like to be flattened to form an interlayer insulating film 40 (FIG. 2B). Next, a resist is applied and a resist film 41 is formed by photolithography (FIG. 3A).
At this time, since the contact hole is formed by the self-alignment method, patterning is performed with an opening dimension d larger than the actual contact opening d '. In FIG. 3A, the case where the registration of the resist films 41 is shifted by the displacement dimension x is shown. Margin m on the peripheral circuit formation part
Is sufficiently larger than the deviation dimension x, the opening dimension d of the resist film 41 and the gate electrode 4 do not overlap.

Next, using the resist film 41 as a mask and the etching stopper film 34 as an etching stopper, for example, dry etching using a gas such as C ₄ F ₈ or the like, and the etching selectivity of the nitride film and the silicon oxide film is 10. The interlayer insulating film 40 and the insulating film 35 are etched under larger conditions. Then, an opening 42 where the etching stopper film 34 is exposed is formed on the memory cell formation portion, and a contact hole 43 where the semiconductor substrate 1 is exposed is formed on the peripheral circuit formation portion (FIG. 3B). At this time, since the etching stopper film 34 is flat in all places,
As shown in the related art, there is no place where the etching stopper film 34 is etched.

Next, for example, the etching gas is changed to a gas such as CF _{4 and the} like is continuously dry-etched under the condition that the etching selection ratio between the nitride film and the silicon oxide film is about 1.
The etching stopper film 34 and the silicon oxide film 33 exposed in the opening 42 are etched to expose the surface of the semiconductor substrate 1 on the memory cell formation portion to form a contact hole 44 (FIG. 4A).

Next, the resist film 41 is removed by a resist removing device, and an electrode film 45 to be a bit line as a second wiring layer is deposited (FIG. 4B). In the above process, only n-type impurities are shown for the sake of convenience.
As a matter of course, in forming the COMS, the step of covering the illustrated portion with the resist film and injecting the p-type impurity into the not-illustrated portion is performed in the same manner as the n-type impurity implantation step. Needless to say.

In the semiconductor device of the first embodiment configured as described above, when the contact hole is formed by the self-alignment method, the sidewall is not formed on the side wall of the gate electrode 4 on the memory cell forming portion, The etching stopper film 34 on the gate electrode 4 is flattened at all places, and the etching stopper film 34 surely functions as an etching stopper when the opening 42 is formed, so that the contact hole 44 short-circuits the gate electrode 4 and the electrode film 45. It can be formed without occurring. Further, the sidewall 37 is formed on the side wall of the gate electrode 4 on the peripheral circuit formation portion, and the etching stopper film 34 does not exist on the gate electrode 4, but the margin m is large, so that the contact hole 4 is formed.
3 can be formed without causing a short circuit between the gate electrode 4 and the electrode film 45.

In the gate electrode on the memory cell formation portion, only one first diffusion layer 6 is formed.
Since it is less necessary to improve the access speed as compared with the gate electrode on the peripheral circuit formation portion, the electrical characteristics of the semiconductor device are not deteriorated. Further, since the LDD structure 37 composed of the first diffusion layer 6 and the second diffusion layer 38 is formed at the gate electrode on the peripheral circuit formation portion, the contact resistance is lowered and the access speed is improved. The electrical characteristics can be improved.

Embodiment 2. In the above-described first embodiment, an example in which the etching stopper film 34 is deposited at 500 angstroms and the silicon oxide film 33 is deposited at 150 angstroms is shown, but the invention is not limited to this, and the etching stopper film 34 functions as an etching stopper. If the silicon oxide film 33 relaxes the stress stress between the etching stopper film 34 and the semiconductor substrate 1 and the etching selectivity is taken into consideration, the etching stopper film 3
4 is 300 angstroms or 1000 angstroms,
If the silicon oxide film 33 is deposited within the range of 150 angstroms to 500 angstroms, the same effect as that of the first embodiment can be obtained.

Embodiment 3. In each of the above-described embodiments, the nitride film is used as the etching stopper film 34 and the silicon oxide film is used as the interlayer insulating film 40. However, the present invention is not limited to this, and the interlayer insulating film 40 and the etching stopper film 34 may be combined. It goes without saying that any material may be used as long as the etching selection ratio is sufficiently large and the etching stopper film 34 functions as an etching stopper when the interlayer insulating film 40 is etched.

[0037]

As described above, according to the first aspect of the present invention, the first region formed by injecting impurities into both upper portions of the semiconductor substrate having the first region and the second region is formed. One diffusion layer, a plurality of first wiring layers formed on the respective first diffusion layers on the semiconductor substrate via a gate insulating film, and a first wiring layer formed on the first region A silicon oxide film and an etching stopper film, which are sequentially stacked so as to cover the first wiring layer, and a silicon oxide film and an etching stopper film on the sidewall of the first wiring layer formed on the second region. And a sidewall formed by sequentially stacking insulating films, a second diffusion layer formed by injecting impurities into the upper portion of the semiconductor substrate around the sidewall, and having a higher impurity concentration than that of the first diffusion layer, Etching stopper film, insulating film and half Covering the body substrate, the top surface flat
The inter-layer insulating film formed by being supported and the first inter-layer insulating film, the etching stopper film, and the silicon oxide film formed through the inter-layer insulating film until reaching the first diffusion layer formed on the first region. A contact hole, a second contact hole formed through the interlayer insulating film until reaching the second diffusion layer formed on the second region, and a second contact hole formed through each contact hole. Since the first wiring layer and the second wiring layer are not short-circuited when the contact hole is formed by the self-alignment method, the first wiring layer according to the desired access speed can be provided. Since the first and second diffusion layers can be formed, it is possible to provide a semiconductor device in which the electrical characteristics of the semiconductor device are not deteriorated and the reliability of the semiconductor device is not impaired.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the first region serves as a memory cell forming portion and the second region serves as a peripheral circuit forming portion. Since the memory cell formation portion and the peripheral circuit formation portion are formed according to the access speed, it is possible to provide a semiconductor device that does not deteriorate the electrical characteristics of the semiconductor device and does not impair the reliability of the semiconductor device. it can.

According to the third aspect of the present invention, in the first or second aspect, since the interlayer insulating film is the silicon oxide film and the etching stopper film is the silicon nitride film, the etching stopper film is surely formed. Since the semiconductor device functions as an etching stopper and can reliably prevent a short circuit between the first wiring layer and the second wiring layer, it is possible to provide a semiconductor device that does not impair the reliability of the semiconductor device.

According to a fourth aspect of the present invention, in the third aspect, the etching stopper film has a film thickness of 300 Å to 1000 Å, and the silicon oxide film formed below the etching stopper film has a film thickness of 150 Å. Since the thickness is from angstrom to 500 angstrom, the etching stopper film functions as a more reliable etching stopper, a short circuit between the first wiring layer and the second wiring layer can be surely prevented, and the etching stopper film and the semiconductor substrate can be surely prevented. Since the silicon oxide film reliably relieves the stress stress on the semiconductor device, it is possible to provide a semiconductor device that does not impair the reliability of the semiconductor device.

According to claim 5 of the present invention, the first
A first wiring layer is formed on both regions of the semiconductor substrate having the regions 1 and 2 and a gate insulating film, and impurities are implanted into the semiconductor substrate using each of the first wiring layers as a mask. A first diffusion layer is formed, a silicon oxide film, an etching stopper film, and an insulating film are sequentially stacked so as to cover each first wiring layer, and the first region is covered with a resist film. Then, the insulating film, the etching stopper film, and the silicon film on the first wiring layer formed on the second region are anisotropically etched to remain only on the side wall of the first wiring layer.
A side wall made of a silicon oxide film, an etching stopper film and an insulating film is formed on the side wall of the wiring layer, and impurities are injected into the semiconductor substrate by using the side wall, the first wiring layer and the resist film as a mask and the first diffusion is performed. A second diffusion layer having a higher impurity concentration than the layer impurity concentration is formed, the resist film is removed, each first wiring layer, the sidewall and the semiconductor substrate are covered, and an interlayer insulating film having a flat upper surface is laminated. To do. Then, the interlayer insulating film and the insulating film corresponding to the first diffusion layer on the first region are etched by using the etching stopper film as an etching stopper to form an opening, and at the same time, on the second region on the second region. The corresponding interlayer insulating film is etched on the diffusion layer until the second diffusion layer is exposed to form a contact hole, and the etching stopper film and the silicon oxide film exposed at the opening are exposed on the first diffusion layer. Etching is performed to form contact holes, and the second wiring layer is formed through each contact hole. Therefore, when the contact holes are formed by the self-alignment method, the first wiring layer and the second wiring layer are formed. Are not short-circuited, and the first and second diffusion layers can be formed according to the desired access speed, so that the electrical characteristics of the semiconductor device are not deteriorated, and It is possible to provide a manufacturing method that no semiconductor device impairing the reliability of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing the method for manufacturing the semiconductor device in the first embodiment of the present invention.

FIG. 3 is a sectional view showing the method for manufacturing the semiconductor device in the first embodiment of the present invention.

FIG. 4 is a sectional view showing the method for manufacturing the semiconductor device in the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device.

FIG. 6 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device.

FIG. 7 is a cross-sectional view showing another conventional method for manufacturing a semiconductor device.

FIG. 8 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device.

9 is a cross-sectional view showing a problem of the method for manufacturing the semiconductor device shown in FIG.

FIG. 10 is a cross-sectional view showing another conventional method for manufacturing a semiconductor device.

FIG. 11 is a diagram for comparing electrical characteristics of a transistor having an LDD structure and a transistor having a single diffusion layer.

[Explanation of symbols]

1 semiconductor substrate, 3 gate insulating film, 4 gate electrode,
6 First diffusion layer, 33, 33a Silicon oxide film, 3
4, 34a etching stopper film, 35, 35a insulating film, 36 resist film, 37 sidewall, 38
Second diffusion layer, 40 Interlayer insulating film.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 27/108 H01L 29/78 301L 29/78 (56) References JP-A-5-90537 (JP, A) JP-A-6 -177349 (JP, A) JP 61-194779 (JP, A) JP 7-122641 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/78

Claims (5)

(57) [Claims] 1. A first diffusion layer formed by implanting an impurity into the upper portion of both regions of a semiconductor substrate having a first region and a second region, and each of the first diffusion layers on the semiconductor substrate. A plurality of first wiring layers formed on the first diffusion layer via a gate insulating film, and the first wiring layer formed on the first region.
A silicon oxide film and an etching stopper film, which are sequentially stacked on the wiring layer to cover the first wiring layer, and silicon on the sidewall of the first wiring layer formed on the second region. An impurity is implanted into a sidewall formed by sequentially stacking an oxide film, an etching stopper film, and an insulating film and an upper portion of the semiconductor substrate around the sidewall, and the impurity concentration is higher than the impurity concentration of the first diffusion layer. By covering the second diffusion layer having a high concentration, the etching stopper film, the insulating film and the semiconductor substrate,
In both cases, an interlayer insulating film whose upper surface is flattened ,
A first contact hole formed through the interlayer insulating film, the etching stopper film and the silicon oxide film until reaching the first diffusion layer formed on the first region; Second contact hole formed through the interlayer insulating film until reaching the second diffusion layer formed on the area of the second wiring layer, and a second wiring layer formed through each of the contact holes. A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein the first region is a memory cell formation portion and the second region is a peripheral circuit formation portion. 3. The semiconductor device according to claim 1, wherein the interlayer insulating film is a silicon oxide film and the etching stopper film is a silicon nitride film. 4. The etching stopper film has a film thickness of 300 Å to 1000 Å, and the silicon oxide film formed under the etching stopper film has a film thickness of 15 Å.
4. The semiconductor device according to claim 3, wherein the semiconductor device has a thickness of 0 angstrom to 500 angstrom. 5. A semiconductor substrate having a first region and a second region, the first region having a gate insulating film interposed between the first region and the second region.
Forming a wiring layer, forming a first diffusion layer by injecting impurities onto the semiconductor substrate using each of the first wiring layers as a mask, and covering each of the first wiring layers. A step of sequentially laminating a silicon oxide film, an etching stopper film, and an insulating film; a step of covering the first region with a resist film; and a step of forming the first region on the second region.
Anisotropically etch the insulating film, the etching stopper film, and the silicon film on the wiring layer to leave only the side wall of the first wiring layer, and the silicon oxide film on the side wall of the first wiring layer. A step of forming a side wall composed of the etching stopper film and the insulating film, and using the side wall, the first wiring layer and the resist film as a mask, impurities are injected into the semiconductor substrate and the first diffusion is performed. Forming a second diffusion layer having an impurity concentration higher than the layer impurity concentration, removing the resist film, covering the first wiring layers, the sidewalls and the semiconductor substrate, and planarizing the upper surface. laminating a layer <br/> insulating film, etching of the interlayer insulating film and the insulating film corresponding to the first of the above region first diffusion layer The etching stopper film is used as an etching stopper to form an opening, and the interlayer insulating film corresponding to the second diffusion layer on the second region is etched until the second diffusion layer is exposed. A step of forming contact holes, a step of etching the etching stopper film and the silicon oxide film exposed in the opening until the first diffusion layer is exposed, and forming the contact holes; And a step of forming the second wiring layer via the interposition, respectively.