JP3523000B2 - D / A converter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter that converts a digital signal into an analog signal.

In recent years, digital processing techniques for converting analog signals into digital signals for processing have been used in an increasingly diverse field. Along with this, in the D / A converter used for digital control, the conversion speed has to be increased due to the increase in the speed of the digital processing system.

[0003]

2. Description of the Related Art FIG. 10 shows an example of a conventional D / A converter. The digital signals D0 to Dn are input to the (n + 1) -bit D / A conversion unit 1, and the D / A conversion unit 1 converts the digital signals D0 to Dn into analog signals and outputs them to the buffer amplifier 2 configured by an operational amplifier. Output.

The buffer amplifier 2 amplifies the input analog signal and outputs it as an analog signal Aout having a sufficient load driving capability. A phase compensation capacitor Cc is connected between the input and output terminals of the inverting amplifier that constitutes the output stage of the buffer amplifier 2.

In the D / A converter thus constructed,
For example, if the power supply VDD is supplied as the high-potential side reference power supply and the ground GND level is supplied as the low-potential side reference power supply, for example, as shown in FIG. 11, the input digital signals D0 to Dn are all "0". Output signal A1 of the D / A conversion unit 1 when all "1"
Even if the signal changes from the ground GND level to the VDD level at high speed, the rising speed of the analog output signal Aout depends on the operation speed of the buffer amplifier 2, and the transition delay time until the analog output signal Aout changes from 0V to VDD. t
It costs 1.

[0006]

[Problems to be Solved by the Invention] Analog output signal Aou
In order to reduce the transition delay time t1 of t 1, it is necessary to improve the operation speed of the buffer amplifier 2. In order to improve the operation speed of the buffer amplifier 2, it is effective to reduce the capacitance value of the phase compensation capacitance Cc. That is, as shown in FIG. 12, the smaller the capacitance value of the phase compensation capacitance Cc, the higher the gain of the output signal of the buffer amplifier 2 with respect to the high-frequency input signal, and the higher the operating speed. .

However, when the frequency of the input signal increases, the phase delay of the output signal with respect to the input signal increases due to the delay of the buffer amplifier, and this output signal is fed back.

Then, when the phase delay of the output signal exceeds 180 degrees, if the gain of the buffer amplifier 2 is 0 dB or more, a positive feedback operation is performed and the buffer amplifier 2 oscillates.

Therefore, it is difficult to improve the output speed of the analog output signal Aout because it tends to oscillate when trying to increase the operation speed of the buffer amplifier 2.
An object of the present invention is to provide a D / A converter that outputs an analog output signal via a buffer amplifier and that can stably increase the D / A conversion speed.

[0010]

FIG. 1 is a diagram for explaining the principle of claim 1. That is, the plurality of D / A conversion units 21 are supplied with the digital signals D0 to Dn-1 and are supplied with a voltage obtained by dividing the potential difference between the high-potential-side reference power supply VDD and the low-potential-side reference power supply GND. Multiple buffer amplifiers 2
2 is supplied with an analog signal output from the D / A converter 21 to which the voltage is supplied . Selection circuit 23
Selects an analog signal Aout corresponding to the digital signals D0 to Dn-1 from the output signals of the plurality of buffer amplifiers 22 based on the control signal Dn.

[0011]

[0012]

[0013]

(Operation) In claim 1, the selection circuit 23 is based on the control signal Dn.
By the selection of the output signal of the buffer amplifier 22 is switched, analog signal A output from the selection circuit 23
out is a voltage supplied to the D / A converter 21 connected to the buffer amplifier 22 and divides the potential difference of the reference power source.
The output signal of the buffer amplifier 22 based on the output signal of the D / A conversion unit 21 is instantaneously switched to the analog signal Aout within the range of the divided voltage , and the analog signal based on the digital input signals D0 to Dn-1. It is output as Aout.

[0015]

[0016]

DETAILED DESCRIPTION OF THE INVENTION

(First Embodiment) FIG. 2 shows an embodiment of the present invention.
1 shows a first embodiment of a +1 bit D / A converter.

First and second D / A converters 11a and 11
The n-bit digital input signals D0 to Dn-1 are input to b. The first D / A converter 11a is supplied with the power supply VDD as the high-potential side reference voltage and VDD / 2 as the low-potential side reference voltage. The second D / A converter 11b is supplied with the power supply VDD / 2 as the high-potential side reference voltage and the ground GND level as the low-potential side reference voltage.

The analog output signal of the first D / A conversion section 11a changes in the range of VDD / 2 to VDD based on the digital input signals D0 to Dn-1, and is constituted by an operational amplifier. It is input to the buffer amplifier 12a.

The analog output signal of the second D / A converter 11b changes in the range of ground GND level to VDD / 2 based on the digital input signals D0 to Dn-1.
It is input to the second buffer amplifier 12b configured by an operational amplifier.

The first and second buffer amplifiers 12
a and 12b have operating speeds similar to those of the buffer amplifier of the conventional example, and the first and second D / A converters 11 are provided.
Buffer the analog output signals of a and 11b,
The output signals OUT1 and OUT2 are output to the selection circuit 13.

The most significant bit digital input signal Dn is input to the selection circuit 13, and if the digital input signal Dn is at the H level, the first buffer amplifier 12a.
Output signal OUT1 is output as an analog output signal Aout, and if the digital input signal Dn is at L level, the output signal OUT2 of the second buffer amplifier 12b is output as an analog output signal Aout.

In the selection circuit 13, for example, as shown in FIG. 3, a transfer gate 14 is turned on depending on whether the digital input signal Dn is at H level or L level.
a, 14b.

In the D / A converter configured as described above, when the most significant bit of the digital input signal Dn is "1", the selection circuit 13 outputs the output signal OUT1 of the first buffer amplifier 12a. An analog output signal Aout that is selected and changes in the range of VDD / 2 to VDD is output.

When the most significant bit of the digital input signal Dn is "0", the output signal OUT2 of the second buffer amplifier 12b is selected by the selection circuit 13 to change the level from the ground GND level to VDD / 2. An analog output signal Aout that changes in the range is output.

The operation when the digital input signals D0 to Dn shift from all "0" to all "1" will be described with reference to FIG. 4. When the digital input signals D0 to Dn are all "0", D / A Based on the output signal of the converter 11b, the output signal OUT2 of the ground GND level output from the second buffer circuit 12b is selected by the selection circuit 13 and output as the analog output signal Aout.

When the digital input signals D0 to Dn are switched from all "0" to all "1", the selection circuit 13 is selected.
Thus, the analog output signal Aout is switched from the output signal OUT2 of the second buffer amplifier 12b to the output signal OUT1 of the first buffer amplifier 12a.

Then, the analog output signal Aout is instantly raised from the ground GND level to the VDD / 2 level. Then, the output signal of the D / A converter 11a is raised to the VDD level, and the output signal OUT1 of the first buffer amplifier 11a is changed from the VDD / 2 level to the VDD level based on the output signal of the D / A converter 11a. The output signal OUT1 is pulled up and output as the analog output signal Aout.

Then, the analog output signal Aout becomes VDD /
The transition delay time t2 from the 2nd level to the VDD level is 1/2 of the transition delay time t1 of the conventional example. Therefore, when the digital input signals D0 to Dn are switched from all "0" to all "1", the transition delay time until the analog output signal Aout transitions from the ground GND level to the VDD level is approximately t2, and the conventional example described above. Can be shortened to about 1/2.

When the digital input signals D0 to Dn are switched from all "1" to all "0", the analog output signal Aout is instantly lowered from the VDD level to the VDD / 2 level, and then the second level. An analog output signal Aout based on the digital input signals D0 to Dn is output based on the output signal OUT2 of the buffer amplifier 12b.

With the D / A converter configured as described above, the following operational effects can be obtained. (B) When the most significant bit signal Dn of the digital input signals D0 to Dn is inverted from "0" to "1", the output signal OUT2 of the second buffer amplifier 12b output as the analog output signal Aout is One buffer amplifier 1
The output signal OUT1 of 2a is instantaneously switched, and the analog output signal Aout is instantaneously switched from the potential between the ground GND level and the VDD / 2 level to the potential between the VDD / 2 level and the VDD level.

Next, the output signal O of the first buffer amplifier 12a based on the output signal of the first D / A converter 11a.
Since the UT1 is output as the analog output signal Aout, the D / A conversion speed can be increased without increasing the operation speed of the buffer amplifiers 12a and 12b. In particular, when the analog output signal Aout shifts from near the ground GND level to near the VDD level based on the digital input signals D0 to Dn, the D / A conversion speed is remarkably increased. (B) When the most significant bit signal Dn of the digital input signals D0 to Dn is inverted from "1" to "0", the output signal OUT1 of the first buffer amplifier 12a output as the analog output signal Aout is Second buffer amplifier 1
The output signal OUT2 of 2b is instantaneously switched, and the analog output signal Aout is instantaneously switched from the potential between the VDD level and the VDD / 2 level to the potential between the ground GND level and the VDD / 2 level.

Next, the output signal O of the second buffer amplifier 12b based on the output signal of the second D / A converter 11b.
Since the UT 2 is output as the analog output signal Aout, the D / A conversion speed can be increased without increasing the operation speed of the buffer amplifiers 12a and 12b. Especially, based on the digital input signals D0 to Dn, the analog output signal Aout is changed from near the VDD level to the ground G
When shifting to the vicinity of the ND level, the speedup of the D / A conversion speed becomes remarkable. (Second Embodiment) FIG. 5 shows a case where the first buffer amplifier 12a is composed of an operational amplifier composed of MOS transistors and an N-channel MOS transistor is used as an input transistor. The case where the buffer amplifier 12b is composed of an operational amplifier made of MOS transistors and the P-channel MOS transistors are used as input transistors is shown.

The first buffer amplifier 12a shown in FIG.
Is supplied with the power supply VDD to the sources of the P-channel MOS transistors Tr1 and Tr2, and the gates of both transistors Tr1 and Tr2 are connected to each other.

The gates of the transistors Tr1 and Tr2 are
The drain of the transistor Tr1 is connected to the drains of the N-channel MOS transistor Tr3, and the drain of the transistor Tr2 is connected to the drain of the N-channel MOS transistor Tr4.

The sources of the transistors Tr3 and Tr4 are
It is connected to the ground GND via the current source 15a. The drains of the transistors Tr2 and Tr4 are the inverting amplifier 1
The output signal OUT1 is output from the inverting amplifier 16a connected to the input terminal of 6a. The inverting amplifier 16a
Operates to decrease the output voltage OUT1 when the input voltage rises and to increase the output voltage OUT1 when the input voltage decreases.

The output signal of the first D / A converter 11a is input as the input signal IN1 to the gate of the transistor Tr4, and the output signal OUT1 of the inverting amplifier 16a is input to the gate of the transistor Tr3.

In the first buffer amplifier 12a thus configured, when the voltage level of the input signal IN1 drops and the gate-source voltage of the transistor Tr4 becomes lower than the threshold value, the transistor Tr4 is turned off. , The output signal OUT1 equal to the voltage level of the input signal IN1 is not output.

However, since a signal in the range of VDD / 2 level to VDD level is input as the input signal IN1, the gate-source voltage of the transistor Tr4 never becomes lower than the threshold value of the transistor Tr4. The first buffer amplifier 12a can be used at an input level that allows normal and high-speed operation.

The second buffer amplifier 12b shown in FIG.
The sources of the P-channel MOS transistors Tr5 and Tr6 are connected to the power supply VDD through the current source 15b. The drain of the transistor Tr5 is connected to the gates of the N-channel MOS transistors Tr7 and Tr8 and the drain of the transistor Tr7, and the sources of both the transistors Tr7 and Tr8 are connected to the ground GND.

The drain of the transistor Tr6 is connected to the drain of the transistor Tr8 and the input terminal of the inverting amplifier 16b. The inverting amplifier 16b operates similarly to the inverting amplifier 16a, and the output signal OUT2 is output from the inverting amplifier 16b.

The output signal of the second D / A converter 11b is input as an input signal IN2 to the gate of the transistor Tr6, and the output signal OUT2 of the inverting amplifier 16b is input to the gate of the transistor Tr5.

In the second buffer amplifier 12b thus constructed, the transistor Tr6 is turned off when the voltage level of the input signal IN2 rises and the gate-source voltage of the transistor Tr6 falls below the threshold value. , The output signal OUT2 equal to the voltage level of the input signal IN2 is not output.

However, as the input signal IN2, the ground G
Since the signal in the range from the ND level to the VDD / 2 level is input, the gate-source voltage of the transistor Tr6 does not become lower than the threshold value of the transistor Tr6, and the second buffer amplifier 12b operates normally. In addition, it can be used at an input level capable of operating at high speed.

Therefore, by using the first and second buffer amplifiers 12a and 12b as described above, a D / A converter that makes a full swing between the ground GND level and the VDD level can be constructed. . (Third Embodiment) FIG. 7 shows a case in which the first buffer amplifier 12a is composed of an operational amplifier made of a bipolar transistor and an NPN transistor is used as an input transistor. FIG. 8 shows the second buffer. Amplifier 1
The case where 2b is composed of an operational amplifier made of a bipolar transistor and the PNP transistor is used as an input transistor is shown.

The first buffer amplifier 12a shown in FIG.
The power supply VDD is supplied to the emitters of the PNP transistors Tr9 and Tr10, and the bases of the transistors Tr9 and Tr10 are connected to each other.

The bases of the transistors Tr9 and Tr10 are based on the transistors Tr9 and NPN transistor Tr1.
The collector of the transistor Tr10 is connected to the collector of the NPN transistor Tr12.

The emitters of the transistors Tr11 and Tr12 are connected to the ground GND via the current source 15c. The collectors of the transistors Tr10 and Tr12 are connected to the input terminal of the inverting amplifier 16c, and the output signal OUT1 is output from the inverting amplifier 16c. The inverting amplifier 16c outputs the output voltage O when the input voltage rises.
When UT1 is lowered and the input voltage thereof is lowered, the output voltage OUT1 is raised.

The output signal of the first D / A converter 11a is input as the input signal IN3 to the gate of the transistor Tr12, and the output signal OUT1 of the inverting amplifier 16c is input to the gate of the transistor Tr11.

In the first buffer amplifier 12a thus configured, when the voltage level of the input signal IN3 drops and the base-emitter voltage of the transistor Tr12 becomes lower than the threshold value, the transistor Tr12 is turned off. , An output signal OU equal to the voltage level of the input signal IN3
T1 is no longer output.

However, since a signal in the range of VDD / 2 level to VDD level is input as the input signal IN3, the base-emitter voltage of the transistor Tr12 never becomes lower than the threshold value of the transistor Tr12. The first buffer amplifier 12a can be used at an input level that allows normal and high-speed operation.

The second buffer amplifier 12b shown in FIG.
Has the emitters of the PNP transistors Tr13 and Tr14 connected to the power supply VDD through the current source 15d. The collector of the transistor Tr13 is an NPN transistor Tr15.
, Tr16 and the collector of the same transistor Tr15, and the emitters of both transistors Tr15, Tr16 are connected to ground GND.

The collector of the transistor Tr14 is connected to the collector of the transistor Tr16 and also to the input terminal of the inverting amplifier 16d. The inverting amplifier 16d operates similarly to the inverting amplifier 16c, and the output signal OUT2 is output from the inverting amplifier 16d.

The output signal of the second D / A converter 11b is input as the input signal IN4 to the base of the transistor Tr14, and the output signal OUT2 of the inverting amplifier 16d is input to the base of the transistor Tr13.

In the second buffer amplifier 12b thus constructed, when the voltage level of the input signal IN4 rises and the base-emitter voltage of the transistor Tr14 becomes lower than the threshold value, the transistor Tr14 is turned off. , An output signal OU equal to the voltage level of the input signal IN4
T2 is no longer output.

However, the ground G is used as the input signal IN4.
Since the signal in the range from the ND level to the VDD / 2 level is input, the base-emitter voltage of the transistor Tr14 does not become lower than the threshold value of the transistor Tr14, and the second buffer amplifier 12b operates normally. In addition, it can be used at an input level capable of operating at high speed.

Therefore, by using the first and second buffer amplifiers 12a and 12b as described above, it is possible to construct a D / A converter which makes a full swing between the ground GND level and the VDD level. . Fourth Embodiment FIG. 9 shows four n-2 bit D / A converters 17a to 17
d, the buffer amplifiers 18a to 18d, and the selection circuit 19
An embodiment in which an n + 1-bit D / A converter is configured by using is shown.

That is, the D / A converters 17a to 17
In d, the digital input signals D0 to Dn excluding the upper 2 bits of the n + 1 bit digital input signals D0 to Dn.
-2 is input.

The power supply VDD is supplied to the D / A conversion section 17a as the high potential side reference voltage, and 3 VDD / 4 is supplied to the low potential side reference voltage. The D / A converter 17b is supplied with 3 VDD / 4 as the high-potential side reference voltage and VDD / 2 as the low-potential side reference voltage.

VDD / 2 is supplied to the D / A converter 17c as a high potential side reference voltage, and VDD / 4 is supplied to a low potential side reference voltage. VDD / 4 is supplied to the D / A converter 17d as the high-potential side reference voltage, and the ground GND level is supplied to the low-potential side reference voltage.

The output signals of the D / A converters 17a to 17d are buffered by the buffer amplifiers 18a to 18d and output to the selection circuit 19. The buffer amplifiers 18a and 18b use the circuit shown in FIG. 5 or 7, and the buffer amplifiers 18c and 18d use the circuit shown in FIG. 6 or 8.

The selection circuit 19 is supplied with the higher-order 2-bit digital input signals Dn-1 and Dn. And
When the digital input signals Dn and Dn-1 are "1, 1", the output signal of the buffer amplifier 18a is selected and output as the analog output signal Aout.

When the digital input signals Dn and Dn-1 are "1, 0", the selection circuit 19 operates as the buffer amplifier 1
The output signal of 8b is selected and output as the analog output signal Aout.

When the digital input signals Dn, Dn-1 are "0, 1", the selection circuit 19 operates as the buffer amplifier 1
The output signal of 8c is selected and output as the analog output signal Aout.

When the digital input signals Dn, Dn-1 are "0, 0", the selection circuit 19 operates in the buffer amplifier 1
The output signal of 8d is selected and output as the analog output signal Aout.

In the D / A converter thus constructed,
Since any one of the output signals of the four buffer amplifiers 18a to 18d is selected and output by the selection circuit 19 based on the higher-order 2-bit digital input signals Dn and Dn-1, the analog signals that are instantaneously switched by the selection circuit 19 are selected. The output signal Aout can be set to a level closer to the analog output signal Aout to be output based on the digital input signals D0 to Dn.

Therefore, the operation speed can be further improved as compared with the first to third embodiments. Also,
By further increasing the numbers of D / A converters and buffer amplifiers, the operating speed can be further improved. At this time, if the number of D / A converters and buffer amplifiers is 2 ^m , the upper m bits of the digital input signals D0 to Dn are input to the selector, and any one of the 2 ^m buffer amplifiers outputs. A signal may be selected, and the digital input signals D0 to Dn-m of lower nm bits may be input to each D / A converter.

[0067]

[0068]

As described above in detail, the present invention is a D / A converter that outputs an analog output signal via a buffer amplifier, and is capable of stably increasing the D / A conversion speed. Can be provided.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a first embodiment.

FIG. 3 is a circuit diagram showing a selection circuit of the first embodiment.

FIG. 4 is a waveform diagram showing the operation of the first embodiment.

FIG. 5 is a circuit diagram showing a buffer amplifier according to a second embodiment.

FIG. 6 is a circuit diagram showing a buffer amplifier according to a second embodiment.

FIG. 7 is a circuit diagram showing a buffer amplifier according to a third embodiment.

FIG. 8 is a circuit diagram showing a buffer amplifier according to a third embodiment.

FIG. 9 is a block diagram showing a fourth embodiment.

FIG. 10 is a circuit diagram showing a conventional example.

FIG. 11 is a waveform chart showing the operation of the conventional example.

FIG. 12 is a frequency characteristic and phase characteristic diagram of a buffer amplifier.

[Explanation of symbols]

21 D / A converter 22 Buffer amplifier 23 Selection circuit D0 to Dn-1 Digital input signal Aout Analog input signal VDD High potential side reference power supply GND Low potential side reference power supply Dn Control signal

─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-4-115626 (JP, A) JP-A-56-146326 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (6)

(57) [Claims] 1. A D / A converter for converting a digital signal into an analog signal, wherein the digital signal is input and a voltage obtained by dividing a potential difference between a high potential side reference power source and a low potential side reference power source is supplied. A plurality of D / A converters, a plurality of buffer amplifiers to which analog signals output from the D / A converters are supplied, and output signals of the plurality of buffer amplifiers to digital signals based on a control signal. The corresponding voltage is supplied
A D / A converter comprising: a selection circuit that selects an analog signal from the D / A conversion unit. 2. A plurality of D / A's to which digital signals are input
A conversion unit, and a plurality of buffer amplifiers connected to the plurality of D / A conversion unit, a selection circuit for selecting an analog signal corresponding to the digital signal from the output signal of said plurality of buffer amplifiers based on a control signal , a D / a converter having a high potential side voltage and the low-potential-side voltage is supplied to each of the plurality of D / a conversion unit, the high-potential-side reference power supply and before
From the voltage obtained by dividing the potential difference from the low-potential side reference power supply,
A D / A converter characterized by being selected . 3. The control signal is added to the digital signal.
It is added to claim 1 or claim 2 characterized in that
The described D / A converter. 4. A high potential side reference power source and a low potential side reference power source
The potential difference of the
A contract characterized by supplying to multiple buffer amplifiers
The D / A converter according to claim 1, claim 2, or claim 3. 5. In the plurality of buffer amplifiers, Input at least one N-channel MOS transistor
It is an operational amplifier using a transistor, Input at least one P-channel MOS transistor
Be an operational amplifier that uses a transistor Characterized by
D according to claim 1, claim 2, claim 3, or claim 4
/ A converter. 6. In the plurality of buffer amplifiers, At least one is an NPN transistor
Is an operational amplifier that At least one is a PNP transistor input transistor
2. An operational amplifier which is a
D / A conversion according to claim 2, claim 3, or claim 4
vessel.