JP3525697B2 - Scanning method discriminator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scanning system discriminating apparatus (international patent classification H04N 17/00, G) for discriminating whether a scanning system of a video signal is interlaced or non-interlaced.
09G 1/16).

[0002]

2. Description of the Related Art FIG. 7 shows the structure of a conventional scanning system discrimination device. In FIG. 7, reference numeral 1 is a horizontal synchronizing signal, 2 is a vertical synchronizing signal, 300 is a differentiating circuit, 400 is a logic integrated circuit,
Reference numeral 500 denotes an integrating circuit. The horizontal synchronizing signal 1 and the vertical synchronizing signal 2 are input, and the vertical synchronizing signal 2 is differentiated by the differentiating circuit 300 to become a signal as shown in C of FIG. Differentiating circuit 300
The differentiated signal C differentiated by is input to the AND circuit 400 and is ANDed with the horizontal synchronizing signal A. Next, the operation of FIG. 7 will be described.

In the case of interlace, a pulse D is obtained every two fields as shown in FIG. AND circuit 40
The output signal D of 0 is input to the integration circuit 500 having the integration constant set for one frame or more, and the AND circuit 500
The pulse signal output from is integrated. Therefore, in the case of interlace, since the pulse signal is input to the integrating circuit 500, a signal of a predetermined level "1" is output.

On the other hand, in the case of non-interlace, as shown in FIG. 9, the output signal C of the differentiating circuit 300 and the horizontal synchronizing signal A are obtained.
No pulse signal can be obtained by ANDing Therefore, since the pulse signal is not input to the integration circuit 500, the integration circuit 5
The output signal from "00" is "0". With the above configuration, an interlaced / non-interlaced discrimination signal can be obtained.

[0005]

In this scanning system discriminating apparatus, it is necessary to set the duty ratio of the horizontal synchronizing signal to be 1/2. When the polarity of the horizontal sync signal as in A of FIG. 10 is inverted and the phase of the vertical sync signal has a phase difference as in F of FIG. 10, “0” is output when the interlaced signal is input. However, there is a problem that the correct determination cannot be made.

Further, when signals having different vertical synchronizing signal frequencies are input, it is necessary to change the constant of the integrating circuit.

[0007]

In order to solve this problem, the first aspect of the present invention is based on the interlaced video signal scanning method.
It is a scanning system discrimination device that discriminates between non-interlace and
A frequency dividing circuit for inputting the horizontal synchronizing signal and the vertical synchronizing signal of the video signal and dividing each by 1/2, and a judging circuit for judging the scanning system from the output signals of the respective frequency dividing circuits. The state of the output signal of the horizontal synchronizing signal is detected by the output signal of the frequency dividing circuit that divides the vertical synchronizing signal, and the scanning method is determined by whether or not a change in the state has occurred.

A second aspect of the present invention is a video signal scanning method.
Scanning format judgment to discriminate between interlaced and non-interlaced
A separate device, which receives a horizontal synchronizing signal and a vertical synchronizing signal of a video signal and divides the horizontal synchronizing signal by ½, and a second dividing circuit that divides the vertical synchronizing signal by ¼. A frequency divider circuit, a first flip-flop circuit that holds the state of the output signal of the first frequency divider circuit during the rising period of the output signal of the second frequency divider circuit, and a rising edge of the output signal of the second frequency divider circuit. An interlace circuit is provided, which includes a second flip-flop circuit that holds the state of the output signal of the first frequency divider circuit during the falling period, and a comparison circuit that compares the levels of the output signals of the first and second flip-flop circuits. This is a scanning method determination device that determines whether the scanning method is non-interlaced.

According to the first and second aspects of the invention, even if the duty ratios of the horizontal synchronizing signals are different, since the discrimination is performed from the frequency-divided signals, the accurate scanning method can be discriminated. Further, since the time direction is not limited even when the synchronizing signals of different frequencies are input, it is possible to provide a scanning method determination device that outputs an accurate scanning method determination signal even in multi-scan.

[0010]

The first invention in the Detailed Description of the Invention The present invention provides movies
Image signal scanning method is interlaced or non-interlaced
A scanning method determining device for determining a horizontal scanning signal and a vertical synchronizing signal of a video signal, each of which is divided by ½ and a scanning method based on an output signal of each of the dividing circuits. And a determination circuit that determines the state of the output signal of the horizontal synchronizing signal from the output signal of the frequency dividing circuit that divides the vertical synchronizing signal, and determines whether or not a change in the state has occurred. It has an effect of discriminating the method.

Further, the second invention is a method of scanning a video signal.
Scanning method that distinguishes between interlaced and non-interlaced expressions
A first discriminating device for inputting a horizontal synchronizing signal and a vertical synchronizing signal of a video signal to divide the horizontal synchronizing signal by ½.
A frequency dividing circuit, a second frequency dividing circuit for frequency-dividing the vertical synchronizing signal by 1/4, and a second frequency dividing circuit for holding the state of the output signal of the first frequency dividing circuit during the rising period of the output signal of the second frequency dividing circuit. One flip-flop circuit, a second flip-flop circuit that holds the state of the output signal of the first frequency divider circuit during the falling period of the output signal of the second frequency divider circuit, and the first and second flip-flop circuits A comparison circuit for comparing the levels of the output signals of the circuits is provided, and if the levels of the output signals of the first flip-flop circuit and the second flip-flop circuit are the same, it is determined as non-interlace, and if the levels are different, it is determined as the interlace. Has the effect of

A scanning system discriminating apparatus according to an embodiment of the present invention will be described below with reference to FIGS.

(Embodiment 1) FIG. 1 is a block diagram of a scanning system discriminating apparatus according to Embodiment 1 of the present invention. In FIG. 1, reference numeral 1 is a horizontal synchronizing signal, 2 is a vertical synchronizing signal, 3 and 4 are frequency dividing circuits, 5 is a discrimination circuit, 6 is a discrimination signal output terminal, 50 is a register, and 51 is a flip-flop circuit.

In FIG. 1, the frequency dividing circuit 3 is composed of a counter circuit, and the horizontal synchronizing signal 1 is input to the frequency dividing circuit 3 to perform 1/2 frequency division processing and supply it to the discriminating circuit 5. The frequency dividing circuit 4 is composed of a counter circuit, and the vertical synchronizing signal 2 is input to the frequency dividing circuit 4 to perform 1/2 frequency division processing and supply it to the determination circuit 5. The determination circuit 5 is a register 50 that captures the output signal of the frequency dividing circuit 3 at the rising or falling timing of the output signal of the frequency dividing circuit 4.
And a flip-flop circuit 51 for detecting a change in state. If there is a change in state, it is judged as interlaced,
If there is no change, it is judged as non-interlaced, and output terminal 6
Supply to.

Next, the operation of the scanning system discriminating apparatus shown in FIG. 1 will be described with reference to the waveform diagram in the case of interlacing shown in FIG.

The horizontal synchronizing signal (A in FIG. 2) supplied to the input terminal 1 is supplied to the frequency dividing circuit 3 and divided by ½ (B in FIG. 2) and then supplied to the discriminating circuit 5. The vertical synchronizing signal (C in FIG. 2) supplied to the input terminal 2 is supplied to the frequency dividing circuit 4, divided by ½ (D in FIG. 2), and then supplied to the determination circuit 5.

The decision circuit 5 outputs the output signal of the frequency dividing circuit 4 (see FIG. 2).
D) at the rising or falling timing of the register 50 that holds the state of the output signal (B in FIG. 2) of the frequency dividing circuit 3 and the flip-flop circuit 51 that detects a change in the output signal (E in FIG. 2) of the register. Determine with. In the case of interlace, since the output signal of the register changes, the flip-flop circuit 51 operates at the timing when a signal with a change image is input, so that the "1" level is output.

Next, the operation in the case of non-interlace will be described with reference to FIG. As shown in FIG. 3, in the case of non-interlace, the output signal of the frequency dividing circuit 3 is at the same level at the rising or falling timing of the output signal of the frequency dividing circuit 4, so that it is always at a constant level and does not change.

Therefore, since the flip-flop circuit 51 does not operate, "0" level is output.

A discriminant output signal is obtained by the above configuration. (Embodiment 2) FIG. 4 is a block diagram showing the configuration of a scanning system discriminating apparatus according to Embodiment 2 of the present invention. In FIG. 4, reference numeral 30 is a first frequency dividing circuit, 40 is a second frequency dividing circuit, and 60.
Is a coincidence detection circuit, 70 is an inverting circuit, and 80 and 81 are registers.

In FIG. 4, the first frequency dividing circuit 30 is composed of a counter circuit, and the horizontal synchronizing signal 1 is input to the first frequency dividing circuit 30 to perform 1/2 frequency division processing and supply it to the registers 80 and 81. The second frequency dividing circuit 40 is composed of a counter circuit, receives the vertical synchronizing signal 2 and performs a 1/4 frequency dividing process, and supplies it to the register 80 and the inverting circuit 70. The inverting circuit 70 inverts the output signal of the frequency dividing circuit 40 and supplies it to the register 81.

The register 80 holds the state of the output signal of the frequency dividing circuit 30 at the rising or falling edge of the frequency dividing circuit 40, and the register 41 holds it at the rising or falling edge of the output signal of the frequency dividing circuit 40. The output signal of the register is supplied to the coincidence detection circuit 60. The coincidence detection circuit is composed of an exclusive OR circuit 61, and outputs "0" level when the polarities of the input signals are the same, and outputs "1" level when the polarities of the input signals are different.

The operation of the scanning system discriminating apparatus configured as described above will be described with reference to the waveform diagram in the case of interlacing shown in FIG.

The signal obtained by dividing the horizontal synchronizing signal (A in FIG. 5) by 1/2 by the first frequency dividing circuit 30 (B in FIG. 5) is inverted in polarity between frames and supplied to the registers 80 and 81. . On the other hand, the vertical synchronizing signal supplied to the input terminal 2 (see FIG.
C) is supplied to the frequency dividing circuit 4 and divided by 1/4 (D in FIG. 5).
It is then supplied to the register 80 and the inverting circuit 70. Next, the register 80 shows a state of the signal obtained by dividing the horizontal synchronizing signal by 1/2 at the rising or falling timing of the signal obtained by dividing the vertical synchronizing signal by 1/4 (F in FIG. 5, "1" level). Is held and the output signal thereof is supplied to the coincidence detection circuit 60.

The register 81 is an output signal of the inverting circuit 70,
That is, it is 1 as a signal whose timing is shifted for one frame.
State of signal divided by two (G in FIG. 5, "0" level)
Is held and the output signal thereof is supplied to one of the coincidence detection circuits 60.

In the case of interlace, the output signal of the register supplied to the coincidence detection circuit 60 outputs "1" level because the polarities are different in one frame.

On the other hand, in the case of non-interlace, if the horizontal synchronizing signal is frequency-divided by a frequency dividing circuit, it becomes an even number between frames. Therefore, the polarities are always the same between frames and are supplied to the registers 80 and 81. Therefore, since signals having the same polarity are input to the coincidence detection circuit 60, a "0" level is output. With the above configuration, the system discrimination signal can be obtained.

[0028]

As described above, according to the present invention,
Even when the duty ratios of the horizontal synchronizing signals are different, since the discrimination is performed from the divided signals, it is possible to discriminate the accurate scanning method. Further, even if a synchronizing signal of a system having a different frequency is input, there is no limitation in the time direction, so that a scanning system discrimination device which outputs an accurate scanning system discrimination signal even in multi-scan can be provided.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a scanning system determination device according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation in the case of interlacing in FIG.

FIG. 3 is a waveform diagram for explaining the operation in the case of non-interlace in FIG.

FIG. 4 is a block configuration diagram of a scanning system discrimination device according to a second embodiment of the present invention.

5 is a waveform diagram for explaining the operation in the case of the interlace of FIG.

6 is a waveform diagram for explaining the operation in the case of non-interlace in FIG.

FIG. 7 is a block configuration diagram of a conventional scanning method determination device.

8 is a waveform diagram for explaining the operation in the case of the interlace of FIG.

9 is a waveform diagram for explaining the operation in the case of non-interlace in FIG.

FIG. 10 is a waveform diagram illustrating the problem of FIG.

[Explanation of symbols]

1 Horizontal sync signal 2 Vertical sync signal 3, 4 divider circuit 5 Discrimination circuit 6 Discrimination signal output terminal 30 1st frequency divider 40 Second frequency divider 50, 80, 81 registers 51 flip-flop circuit 60 Match detection circuit 70 Inversion circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 17/00 H04N 7/01

Claims (3)

(57) [Claims] 1. A video signal scanning system is interlaced or non-interlaced.
A scanning system discrimination device for discriminating interlace , wherein a frequency dividing circuit for inputting a horizontal synchronizing signal and a vertical synchronizing signal of a video signal and dividing each by 1/2, and outputs of the respective frequency dividing circuits And a discriminating circuit for discriminating the scanning method from the signal, wherein the discriminating circuit is a signal obtained by dividing the vertical synchronizing signal by 1/2.
A register that holds the horizontal sync signal divided by 1/2
And a flip for detecting a change in the output signal of the register
And a flip-flop circuit.
If a change is detected by interlacing, if there is no change
A scanning method discrimination device characterized by being discriminated as non-interlaced . 2. A scanning method of a video signal is interlaced.
It is a scanning system discrimination device that discriminates non-interlace.
The horizontal synchronizing signal and the vertical synchronizing signal of the video signal are input to divide the horizontal synchronizing signal by 1/2, and the second dividing circuit divides the vertical synchronizing signal by 1/4. A first flip-flop circuit that holds the state of the output signal of the first frequency divider circuit during the rising period of the output signal of the second frequency divider circuit; and the first flip-flop circuit during the falling period of the output signal of the second frequency divider circuit. comprises a second flip-flop circuit for holding the state of the output signal of the first frequency divider and a comparator circuit for comparing the level of said first output signal of the second flip-flop circuit, the output of the comparator circuit A scanning method determination device that determines whether interlaced or non-interlaced. 3. The scanning system discrimination apparatus according to claim 2, wherein the comparison circuit detects coincidence detection and non-coincidence detection.