JP3525790B2 - DMA data transfer method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA data transfer method.

[0002]

2. Description of the Related Art In an information processing apparatus, a main memory and a SCSI (Small Computation) are used.
er system interface) DMA (D
Data transfer (DMA) using irect Memory Access
When performing data transfer), as shown in FIG. 4A, a method (sequential address transfer method) of sequentially transferring data of consecutive addresses from the head data of the data transfer area D,
As shown in FIG. 4B, the data transfer area D is divided into a number of areas A to G (divided areas), and the data in the areas A to G is transferred in an arbitrary order according to the cache hit status and the like. Method (discontinuous address transfer method).
However, when the SCSI magnetic storage device is connected to an information processing device having an input / output control device that supports only the continuous address transfer system, data cannot be transferred according to the discontinuous address transfer system.

The present invention has been made in view of the above problems, and when a SCSI magnetic storage device is connected to an information processing device having an input / output control device which supports only a continuous address transfer system, The purpose is to realize discontinuous address transfer.

[0004]

To achieve the above object, the present invention, as a first means, supports only a continuous address transfer system in which continuous data is sequentially DMA-transferred from the start address of a data transfer area. A method of performing DMA transfer of data in each divided area obtained by dividing the data transfer area into a plurality of areas from a transfer source to a transfer destination in an arbitrary order of divided areas by using an input / output control device, and sequentially from the first divided area. When the DMA transfer of the data of the divided area is specified, the sum of the start address and size of each divided area and the size from the start of the data transfer area to the immediately preceding divided area is plural in the input / output control device. The prefetch of the data to be stored in one of the provided entries and the DMA transfer of the data of the divided area based on the start address and the size of the start divided area by the prefetch of the data For each of the divided areas continuous with the leading divided area, the data prefetch and the DMA transfer based on the head address and the size of the divided area by the data prefetch are sequentially repeated, and the divided division is not continuous. When DMA transfer of area data is instructed,
The divided area to be DMA-transferred is searched by comparing the offset value of the address of the divided area obtained from the transfer destination with the sum of the sizes from the head of the data transfer area stored in each entry to the immediately preceding divided area. Specified DMA
To adopt the means of performing the transfer.

As a second means, in the first means, the data is written in a predetermined order for a plurality of entries.
Prefetch and DMA transfer are performed, and the last entry is deleted.
When data prefetch and DMA transfer are performed, from the first entry
A method of prefetching data and performing DMA transfer is adopted.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a DMA data transfer method according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the functional arrangement of a computer system to which this embodiment is applied. In this figure, reference numeral 1 is a main storage device, 2 is an arithmetic processing device,
Reference numeral 3 is a system controller, 4 is an input / output controller, 5 is a device controller, and 6 is a SCSI magnetic storage device. Of these components, the main storage device 1, the arithmetic processing device 2, and the system control device 3 are well-known components, and detailed description thereof will be omitted.

The input / output control device 4 has a data prefetch table 40 having 32 entries (first entry to 32nd entry), a data prefetch pointer 41 and a data current pointer 42 pointing to each entry of the data prefetch table 40, and a SCSI. The register 43 and the DMA transfer control unit 44 for receiving the offset value sent from the magnetic storage device 6 at the time of discontinuous address transfer are provided.

Each entry of the data prefetch table 40 has a total of 16 elements from D00 to D0F.
As shown in FIG. 2, the element of D00 is the start address of the divided area on the main storage device 1, the element of D01 is the size of this area, and the element of D02 is the area up to the immediately preceding area. The total size is stored. When the input / output control device 4 detects a discontinuous address transfer, the arithmetic processing device 2 notifies the firmware in the input / output control device 4 of an interrupt and executes the processing shown in the flowchart of FIG.

Next, the DMA data transfer method (discontinuous address transfer method) in the computer system will be described in detail with reference to FIGS.

First, at the start of data transfer, the information processing apparatus 2 initializes the data prefetch pointer 41 and the data current pointer 42 to point to the first entry of the data prefetch table 40. Then, as shown in FIG. 2, the data transfer area C on the main storage device 1 is divided into divided areas (P00 to P0X) of a predetermined size, and the start address, size, and data of each divided area P00 to P0X are divided. The total sum of the sizes of the areas from the beginning of the transfer area C to the immediately preceding area is stored in the respective elements D00 to D02 of the above entry.

For example, as shown in the figure, the divided area P02
In the third entry corresponding to
The first address of 2 is stored, and the divided area P is stored in the element D01.
The size of No. 02 is stored, and the sum of the sizes of the areas from the beginning of the data transfer area C to the immediately preceding divided area, that is, the sum of the sizes of the divided areas P00 and P01 (that is, the address The offset value of is stored.

Such processing is performed by the data prefetch pointer 41 one by one from the beginning of the data transfer area C.
This is done by specifying one entry. It should be noted that such processing is called "data pre-fetching".

For example, when the "data prefetching" of the divided area P00 for the first entry is completed, the information processing apparatus 2 stores the data in the elements D00 and D01 of the first entry pointed to by the data current pointer 42, respectively. The start address of the divided area P00 and its size are set in the DMA transfer control unit 44, and the data of the divided area P00 is SCS based on this start address and its size.
DMA transfer to the I magnetic storage device 6 (transfer destination).

At this point, since the data current pointer 42 points to the same entry as the data prefetch pointer 41, that is, the first entry, the data prefetch pointer 41 is incremented and the data of the next entry (second entry) is incremented. Of the divided area P01 based on each of the above-mentioned data related to the divided area P01 stored in the second entry, by executing the prefetching of the data current pointer 42.
DMA transfer is performed to the CSI magnetic storage device 6.

When the DMA transfer of the data in the divided area P01 is completed, all the data in the data transfer area C is DMA-transferred by repeating the prefetching of the data in each divided area P02, ... And the DMA transfer. When the data current pointer 42 and the data prefetch pointer 41 point to the last 32nd entry, the data current pointer 42 and the data prefetch pointer 41 are set to the first
Set to point to the entry and continue processing.

In the DMA transfer of the divided area P00 and each of the divided areas P01, P02, ... Continuing to the divided area P00, the discontinuous addresses of the discontinuous addresses are based on the offset value of the address sent from the SCSI magnetic storage device 6, for example. D
When the MA transfer is detected, the information processing device 2 notifies the firmware in the input / output control device 4 of the interrupt and executes the process shown in FIG. I do.

That is, first, by comparing the element D02 of the entry pointed to by the data current pointer 42 with the data in the register 43 at this point, each data in the divided area to be transferred is stored in the data prefetch table 40. It is confirmed whether the entry has been read (step S1). Here, if the element D02 is smaller, it may not have been read into the data prefetch table 40, so the sum of the data of the element D02 and the data of the element D01 of the entry pointed to by the data current pointer 42. (D02 + D01) is compared with the data in the register 43 (step S2).

If the register 43 is larger,
Since the entry designated by the data current pointer 42 is not the corresponding entry, the data current pointer 4
2 is incremented (step S3). At this time,
If the data current pointer 42 points to the 32nd entry, the data prefetch pointer 41 and the data current pointer 42 are set to point to the 1st entry.

After such an increment of the data current pointer 42, whether the entry designated by the data current pointer 42 is prefetched, that is, the entry pointed to by the data current pointer 42 and the entry pointed to by the data prefetch pointer 41 Is checked (step S4), and if the data is not pre-fetched, the data is pre-fetched (step S5 ) and then the process of step S6 is performed. If the data is pre-fetched, The process of step S6 is immediately performed.

Then, in step S6, the above-mentioned step S
If the data in the register 43 is smaller, the entry indicated by the data current pointer 42 is the entry for which data transfer is to be performed, so the data transfer address and count are calculated and DMA is performed.
This is set in the transfer control unit 44, the DMA transfer is activated, and the process ends.

On the other hand, if it is determined in step S1 that the data in the register 43 is smaller, the corresponding entry may already exist in the data prefetch table 40, so the data current pointer 42 is decremented (step S8). ), Also element D02 and register 45
Are compared (step S9).

At this time, if the data in the register 43 is larger, the entry pointed to by the data current pointer 42 is the entry to which the data transfer should be performed, so that the process in step S7 is subsequently executed.
If the data in the register 43 is smaller, it is confirmed whether or not the data current pointer 42 points to "0", that is, the first entry. If the data does not point to the first entry, the process of step S8 is performed. repeat.

The data current pointer 42 is the first
Data prefetch pointer 4 if pointing to an entry
1 and the data current pointer 42 are reset to point to the first entry, data is prefetched from the beginning of the data transfer area C, and then step S2 is performed.
The process of is executed.

As described above, the sum of the divided areas of the data transfer area C in the main storage device 1, that is, the start addresses and sizes of the divided areas P00 to P0X and the sizes up to the immediately preceding area is stored in the data prefetch table 40. Each element D00 of each entry
~ D02, by performing the series of processing in the firmware, at the time of discontinuous address transfer,
It becomes possible to retrieve the data transfer address on the main memory 1 and transfer the data. The number of entries in the data prefetch table 40 and the number of elements in each entry are arbitrary.

[0026]

As described above, the D according to the present invention
The MA data transfer method has the following effects. (1) The data of each divided area can be DMA-transferred in the order of an arbitrary divided area by using the input / output control device which supports only the continuous address transfer method. (2) When the data is pre-fetched in a predetermined order for a plurality of entries and the data is pre-fetched for all entries, the next data is pre-fetched in the above-mentioned order from the entry which pre-fetched the data first. In this case, since the entry can be reused, it is not necessary to provide the entry by the number of divided areas, and the capacity of the storage area required for the entry can be suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a functional configuration of an apparatus to which an embodiment of the present invention is applied.

FIG. 2 is an explanatory diagram for explaining an embodiment of the present invention.

FIG. 3 is a flowchart showing a process at a discontinuous address according to the embodiment of the present invention.

FIG. 4 is an explanatory diagram for explaining a conventional DMA data transfer method.

[Explanation of symbols]

1 ... Main memory 2 ... Arithmetic processing unit 3 ... System control device 4 ... Input / output control device 5: Device control device 6 ... SCSI magnetic storage device 40 ... Data prefetch table 41: Data prefetch pointer 42 ... Data current pointer 43 ... Register 44, 50 ... DMA transfer control unit

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 13/20-13/378

Claims (2)

(57) [Claims] 1. A data transfer area is divided into a plurality of parts by using an input / output control device (4) which supports only a continuous address transfer method of sequentially DMA-transferring continuous data from a start address of the data transfer area (C). A method of DMA-transferring data in each divided area (P00 to P0X) from a transfer source to a transfer destination in the order of an arbitrary divided area.
If transfer is instructed, the start address of each divided area ,
Preemption of data for storing the sum of the size and the size from the beginning of the data transfer area to the immediately preceding divided area in one of the plurality of entries provided in the input / output control device, and the division of the beginning by preemption of the data The data of the divided area is DMA-transferred based on the start address and size of the area, and for each divided area continuous to the first divided area, the prefetch of the data and the start of the divided area by the prefetch of the data are performed. When the DMA transfer based on the address and the size is sequentially repeated and the DMA transfer of the data of the non-continuous divided areas is instructed, the offset value of the address of the divided area obtained from the transfer destination and the value stored in each entry are stored. By comparing the sum of the sizes from the head of the data transfer area to the immediately preceding divided area, the divided area to be DMA-transferred is searched and specified to perform DMA. A DMA data transfer method, characterized in that the transfer is performed . 2. A de in a predetermined order to a plurality of entries
Perform preemption and DMA transfers over data, when the preempt and DMA transfer of data for the last entry, according to claim 1, characterized in that the preemption and DMA transfer of data from the first entry <br/> DMA data transfer method.