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JP3526526B2 - Package for storing semiconductor elements - Google Patents
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JP3526526B2 - Package for storing semiconductor elements - Google Patents

Package for storing semiconductor elements

Info

Publication number
JP3526526B2
JP3526526B2 JP33908497A JP33908497A JP3526526B2 JP 3526526 B2 JP3526526 B2 JP 3526526B2 JP 33908497 A JP33908497 A JP 33908497A JP 33908497 A JP33908497 A JP 33908497A JP 3526526 B2 JP3526526 B2 JP 3526526B2
Authority
JP
Japan
Prior art keywords
semiconductor element
insulating
sio
mgo
weight
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP33908497A
Other languages
Japanese (ja)
Other versions
JPH11176990A (en
Inventor
邦英 四方
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP33908497A priority Critical patent/JP3526526B2/en
Publication of JPH11176990A publication Critical patent/JPH11176990A/en
Application granted granted Critical
Publication of JP3526526B2 publication Critical patent/JP3526526B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Compositions Of Oxide Ceramics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、LSI(大規模集
積回路素子)等の半導体素子を収容するための半導体素
子収納用パッケージに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element housing package for housing a semiconductor element such as an LSI (Large Scale Integrated Circuit Element).

【0002】[0002]

【従来の技術】従来、LSI(大規模集積回路素子)等
の半導体素子を収容する半導体素子収納用パッケージ
は、一般に酸化アルミニウム質焼結体等の電気絶縁材料
から成り、その上面略中央部に半導体素子を収容するた
めの凹部を設けた絶縁基体と、該絶縁基体の凹部周辺か
ら下面にかけて導出されたタングステン、モリブデン、
マンガン等の高融点金属粉末から成る複数個の配線層
と、蓋体とから構成されており、絶縁基体の凹部底面に
半導体素子を搭載収容するとともに半導体素子の各電極
をボンディングワイヤ等の電気的接続手段を介して配線
層に接続させ、しかる後、絶縁基体の上面に蓋体を封止
用の接着材を介して接合させ、絶縁基体と蓋体とから成
る容器内部に半導体素子を気密に収容することによって
製品としての半導体装置が完成する。
2. Description of the Related Art Conventionally, a semiconductor element housing package for housing a semiconductor element such as an LSI (Large Scale Integrated Circuit Element) is generally made of an electrically insulating material such as an aluminum oxide sintered body and has a substantially central portion on its upper surface. An insulating base provided with a recess for accommodating a semiconductor element, and tungsten and molybdenum led out from the periphery of the recess of the insulating base to the lower surface,
It is composed of a plurality of wiring layers made of refractory metal powder such as manganese, and a lid. The semiconductor element is mounted and housed on the bottom surface of the recess of the insulating base, and each electrode of the semiconductor element is electrically connected by a bonding wire or the like. It is connected to the wiring layer via the connecting means, and thereafter, the lid is joined to the upper surface of the insulating base with an adhesive for sealing, and the semiconductor element is hermetically sealed inside the container composed of the insulating base and the lid. A semiconductor device as a product is completed by housing.

【0003】かかる半導体装置は絶縁基体の下面に導出
している配線層の一部を外部電気回路基板の配線導体に
接続させることによって半導体素子の各電極が外部電気
回路に接続されることとなり、外部電気回路基板の配線
導体を介して半導体素子の各電極に電気信号が出し入れ
されることになる。
In such a semiconductor device, each electrode of the semiconductor element is connected to the external electric circuit by connecting a part of the wiring layer extending to the lower surface of the insulating substrate to the wiring conductor of the external electric circuit board. An electric signal is input and output to and from each electrode of the semiconductor element via the wiring conductor of the external electric circuit board.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、近年、
情報処理装置は高性能化が急激に進展し、これに伴って
半導体素子も高速駆動が行われ、ノイズの影響を極めて
受け易いものになってきたこと、従来の半導体素子収納
用パッケージは絶縁基体に設けたタングステンやモリブ
デン等から成る配線層が高調波のノイズを伝搬させ易い
こと等から配線層に外部電気回路基板の配線導体から高
調波のノイズが入り込んだ場合、このノイズがそのまま
配線層を伝搬して半導体素子に入り込み、半導体素子を
誤動作させてしまうという欠点を有していた。
However, in recent years,
Information processing devices have rapidly advanced in performance, and along with this, semiconductor elements have been driven at high speed, and have become extremely susceptible to noise. Since the wiring layer made of tungsten, molybdenum, etc., provided in the section easily propagates the harmonic noise, when the harmonic noise enters from the wiring conductor of the external electric circuit board into the wiring layer, this noise is directly transmitted to the wiring layer. It has a drawback that it propagates and enters the semiconductor element, causing the semiconductor element to malfunction.

【0005】本発明は、上記欠点に鑑み案出されたもの
で、その目的は、絶縁基体に設けた配線層に外部電気回
路基板の配線導体よりノイズが入り込んだとしてもその
ノイズを良好に吸収し、ノイズがそのまま半導体素子に
入り込むのを有効に防止して半導体素子を長期間にわた
り正常に作動させることができる半導体素子収納用パッ
ケージを提供することにある。
The present invention has been devised in view of the above-mentioned drawbacks, and an object thereof is to favorably absorb even if noise enters from a wiring conductor of an external electric circuit board into a wiring layer provided on an insulating substrate. It is another object of the present invention to provide a semiconductor element housing package that can effectively prevent noise from directly entering the semiconductor element and operate the semiconductor element normally over a long period of time.

【0006】[0006]

【課題を解決するための手段】本発明は、上面に半導体
素子が搭載される搭載部を有し、該搭載部より下面にか
けて導出される電気抵抗率が3μΩ・cm以下の複数個
の配線層を有する絶縁基体と、前記絶縁基体に取着さ
れ、搭載部に搭載される半導体素子を封止する蓋体とか
ら成る半導体素子収納用パッケージであって、前記絶縁
基体を複数のSiO2 ーAl2 3 ーMgOーZnOー
2 3 系結晶性ガラスから成る絶縁層を積層して前記
配線層と同時焼成によって形成するとともに少なくとも
最下層の絶縁層に粒径が0.5μm〜10μmの磁性材
料を含有させて磁性絶縁層とし、前記磁性絶縁層に、粒
径が0.5〜5μmの無機物フィラーを外添加で10〜
40重量部含有させたことを特徴とするものである。
According to the present invention, a plurality of wiring layers having a mounting portion on which a semiconductor element is mounted on an upper surface and having an electric resistivity of 3 μΩ · cm or less derived from the mounting portion to the lower surface. A package for storing a semiconductor element, comprising: an insulating substrate having a substrate; and a lid attached to the insulating substrate and sealing a semiconductor element mounted on a mounting portion, wherein the insulating substrate comprises a plurality of SiO 2 -Al. 2 O 3 —MgO—ZnO—B 2 O 3 -based crystalline glass is laminated and formed by co-firing with the wiring layer, and at least the lowermost insulating layer has a grain size of 0.5 μm to 10 μm. A magnetic insulating layer is formed by containing a magnetic material, and an inorganic filler having a particle size of 0.5 to 5 μm is externally added to the magnetic insulating layer by 10 to 10.
It is characterized by containing 40 parts by weight.

【0007】また本発明は、前記磁性絶縁層における磁
性材料の含有量が50〜90重量%であることを特徴と
するものである。
Further, the present invention is characterized in that the content of the magnetic material in the magnetic insulating layer is 50 to 90% by weight.

【0008】[0008]

【0009】本発明の半導体素子収納用パッケージによ
れば、上面に半導体素子が搭載される搭載部を有し、該
搭載部より下面にかけて複数個の配線層が被着形成され
ている絶縁基体を複数のSiO2 ーAl2 3 ーMgO
ーZnOーB2 3 系結晶性ガラスから成る絶縁層を積
層して形成するとともに少なくとも最下層の絶縁層に磁
性材料を含有させて磁性絶縁層としたことから外部電気
回路基板の配線導体より配線層にノイズが入り込もうと
してもそのノイズは絶縁基体の最下部に位置する磁性絶
縁層に含有されている磁性材料で熱エネルギーに変換さ
れて吸収され、その結果、ノイズが配線層に入り込んで
半導体素子に伝搬することはなく、半導体素子を常に正
常に作動させることが可能となる。
According to the package for accommodating a semiconductor element of the present invention, the insulating substrate having the mounting portion on which the semiconductor element is mounted on the upper surface, and the plurality of wiring layers being adhered to the lower surface from the mounting portion is formed. Multiple SiO 2 -Al 2 O 3 -MgO
-ZnO-B 2 O 3 -based crystalline glass is laminated to form a magnetic insulating layer containing a magnetic material in at least the lowermost insulating layer. Even if noise enters the wiring layer, the noise is converted into heat energy and absorbed by the magnetic material contained in the magnetic insulating layer located at the bottom of the insulating substrate, and as a result, the noise enters the wiring layer. It does not propagate to the semiconductor element, and the semiconductor element can always be normally operated.

【0010】また本発明の半導体素子収納用パッケージ
によれば、絶縁基体を構成する絶縁層がSiO2 ーAl
2 3 ーMgOーZnOーB2 3 系結晶性ガラスで形
成されており、該SiO2 ーAl2 3 ーMgOーZn
OーB2 3 系結晶性ガラスはその焼成温度が800〜
1050℃と低いことからこの結晶性ガラス中に磁性材
料を含有させて焼成しても磁性材料は磁性を失うことは
なく、ノイズを良好に吸収することが可能となる。
Further, according to the package for accommodating semiconductor elements of the present invention, the insulating layer constituting the insulating substrate is made of SiO 2 -Al.
2 O 3 —MgO—ZnO—B 2 O 3 type crystalline glass, and the SiO 2 —Al 2 O 3 —MgO—Zn
The firing temperature of OB 2 O 3 based crystalline glass is 800 to
Since the temperature is as low as 1050 ° C., the magnetic material does not lose its magnetism even if the crystalline glass is mixed with the magnetic material and fired, and noise can be well absorbed.

【0011】同時にSiO2 ーAl2 3 ーMgOーZ
nOーB2 3 系結晶性ガラスの焼成温度が低いことか
ら銅、銀、金等の融点が低くく、導通抵抗の低い材料か
ら成る配線層を同時焼成によって形成することが可能と
なり、配線層を電気信号が伝搬した際、電気信号に減衰
等が生じるのを有効に防止して半導体素子を正確に作動
させることもできる。
At the same time, SiO 2 --Al 2 O 3 --MgO--Z
Since the firing temperature of the nO-B 2 O 3 -based crystalline glass is low, it is possible to form a wiring layer made of a material having a low melting point, such as copper, silver, and gold, and a low conduction resistance by simultaneous firing. When the electric signal propagates through the layer, it is possible to effectively prevent the electric signal from being attenuated or the like and operate the semiconductor element accurately.

【0012】更に絶縁基体を構成するSiO2 ーAl2
3 ーMgOーZnOーB2 3 系結晶性ガラスに無機
物フィラーを外添加で10〜40重量部の範囲で含有さ
せているので、SiO2 ーAl2 3 ーMgOーZnO
ーB2 3 系結晶性ガラスの機械的強度が強くなり、こ
れによって絶縁基体に外力等が印加されても破損等が発
生するのを有効に防止することができる。
[0012] SiO 2 over Al 2 further constituting the insulating substrate
Since an inorganic filler is externally added to O 3 —MgO—ZnO—B 2 O 3 -based crystalline glass in the range of 10 to 40 parts by weight, SiO 2 —Al 2 O 3 —MgO—ZnO
The mechanical strength of the —B 2 O 3 -based crystalline glass is strengthened, and thereby, it is possible to effectively prevent the occurrence of damage or the like even when an external force or the like is applied to the insulating substrate.

【0013】[0013]

【発明の実施の形態】次に本発明を添付図面に基づき詳
細に説明する。図1は本発明の半導体素子収納用パッケ
ージの一実施例を示し、1は絶縁基体、2は蓋体であ
る。この絶縁基体1と蓋体2とで半導体素子を内部に収
容するための容器が構成される。
DETAILED DESCRIPTION OF THE INVENTION The present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of a package for housing a semiconductor device of the present invention, in which 1 is an insulating base and 2 is a lid. The insulating base body 1 and the lid body 2 constitute a container for housing the semiconductor element therein.

【0014】前記絶縁基体1は、その上面中央部に半導
体素子3が載置収容される凹部1aが設けてあり、該凹
部1a底面に半導体素子3が接着材を介して接着固定さ
れる。
The insulating base 1 is provided with a recess 1a in which the semiconductor element 3 is placed and housed in the center of the upper surface thereof, and the semiconductor element 3 is adhered and fixed to the bottom surface of the recess 1a via an adhesive material.

【0015】前記絶縁基体1は3つのSiO2 ーAl2
3 ーMgOーZnOーB2 3 系結晶性ガラスから成
る絶縁層4、5、6を積層一体化して形成されており、
例えば、SiO2 、Al2 3 、MgO、ZnO、B2
3 に適当な有機溶剤、溶媒、可塑剤等を添加混合して
泥漿状となすとともに、該泥漿物をドクターブレード法
やカレンダーロール法等によりシート状に成形して複数
枚のグリーンシート(生シート)を得、しかる後、前記
グリーンシートに適当な打ち抜き加工を施すとともに所
定の順に上下に積層し、800〜1050℃の温度で焼
成することによって製作される。
The insulating substrate 1 comprises three SiO 2 -Al 2
O 3 and the over MgO over ZnO over B 2 O 3 based dielectric layer 4, 5 and 6 made of crystalline glass is formed by laminating integrally,
For example, SiO 2 , Al 2 O 3 , MgO, ZnO, B 2
A suitable organic solvent, a solvent, a plasticizer, etc. are added to O 3 and mixed to form a slurry, and the slurry is formed into a sheet by a doctor blade method, a calendar roll method or the like, and a plurality of green sheets (green sheet) are prepared. A green sheet is obtained, and thereafter, the green sheet is subjected to appropriate punching processing, laminated vertically in a predetermined order, and fired at a temperature of 800 to 1050 ° C.

【0016】また前記絶縁基体1は凹部1aの周囲から
絶縁基体1に設けた貫通孔7を介して下面に導出する複
数個の配線層8が形成されており、該配線層8は内部に
収容する半導体素子3の各電極を外部電気回路に電気的
に接続する作用をなし、配線層8の凹部1a周辺部には
半導体素子3の各電極がボンディングワイヤ等の電気的
接続手段9を介して電気的に接続され、また絶縁基体1
の下面に導出する部位には外部電気回路基板の配線導体
に接続される外部リートピン10がロウ材を介して接合
されている。
Further, the insulating base 1 is formed with a plurality of wiring layers 8 extending from the periphery of the recess 1a to the lower surface through the through holes 7 provided in the insulating base 1, and the wiring layers 8 are housed inside. Each of the electrodes of the semiconductor element 3 serves to electrically connect the electrodes of the semiconductor element 3 to an external electric circuit. Electrically connected and insulating base 1
The external lead pin 10 connected to the wiring conductor of the external electric circuit board is joined to the portion led out to the lower surface of the via a brazing material.

【0017】前記配線層8は銅、銀、金等の電気抵抗率
が3μΩ・cm以下の金属材料から成り、例えば、銅等
の金属粉末に適当な有機溶剤、溶媒を添加混合して得た
金属ペーストを絶縁基体1となるグリーンシートの上面
及びグリーンシートに孔開け加工により開けた孔内に予
め従来周知のスクリーン印刷法等により所定パターンに
印刷塗布しておくことによって絶縁基体1の凹部周囲か
ら下面にかけて被着形成される。この場合、銅、銀、金
等の金属材料から成る配線層8はSiO2 ーAl2 3
ーMgOーZnOーB2 3 系結晶性ガラスから成る絶
縁基体1の焼成温度が800〜1050℃と低いため、
絶縁基体1の焼成時に金属ペーストの銅や銀等の金属粉
末が気散してしまうことはなく、絶縁基体1と同時焼成
によって絶縁基体1の所定位置に形成することができ
る。
The wiring layer 8 is made of a metal material having an electric resistivity of 3 μΩ · cm or less such as copper, silver and gold. For example, it is obtained by adding and mixing a suitable organic solvent or solvent to a metal powder such as copper. Around the concave portion of the insulating substrate 1 by applying the metal paste by printing in a predetermined pattern in advance on the upper surface of the green sheet to be the insulating substrate 1 and in the holes formed by punching the green sheet by a conventionally known screen printing method or the like. To the lower surface. In this case, the wiring layer 8 made of a metal material such as copper, silver or gold is SiO 2 -Al 2 O 3
Since the firing temperature of the insulating substrate 1 made of over MgO over ZnO over B 2 O 3 based crystalline glass is 800 to 1050 ° C. and lower,
When the insulating base 1 is fired, the metal powder of the metal paste, such as copper or silver, is not dispersed, and can be formed at a predetermined position on the insulating base 1 by simultaneous firing with the insulating base 1.

【0018】また前記配線層8を形成する銅、銀、金等
はその電気抵抗率が3μΩ・cm以下と低いことから配
線層8を電気信号が伝搬しても電気信号に減衰等が生じ
るのを有効に防止することができ、その結果、半導体素
子3に対し電気信号を正確に出し入れすることが可能と
なり、半導体素子3を常に正常に作動させることができ
る。
Since copper, silver, gold, etc. forming the wiring layer 8 have a low electric resistivity of 3 μΩ · cm or less, even if the electric signal propagates through the wiring layer 8, the electric signal is attenuated. Can be effectively prevented, and as a result, an electric signal can be accurately taken in and out of the semiconductor element 3, and the semiconductor element 3 can always be normally operated.

【0019】なお、前記配線層8は銅や銀から成る場
合、その露出表面に耐蝕性に優れる金等をメッキ法によ
り1.0〜20μmの厚みに被着させておくと配線層8
の酸化腐蝕を有効に防止することができるとともに配線
層8とボンディングワイヤ等の電気的接続手段9との接
続及び配線層8への外部リードピン10の接合を強固と
なすことができる。従って、前記配線層8は銅や銀から
成る場合、その露出表面に金等の耐蝕性に優れる金属を
メッキ法により1.0〜20μmの厚みに被着させてお
くことが好ましい。
When the wiring layer 8 is made of copper or silver, the wiring surface 8 is formed by depositing gold having excellent corrosion resistance on the exposed surface to a thickness of 1.0 to 20 μm by a plating method.
It is possible to effectively prevent the above-mentioned oxidative corrosion and to strengthen the connection between the wiring layer 8 and the electrical connecting means 9 such as a bonding wire and the connection of the external lead pin 10 to the wiring layer 8. Therefore, when the wiring layer 8 is made of copper or silver, it is preferable to deposit a metal having excellent corrosion resistance such as gold on the exposed surface to a thickness of 1.0 to 20 μm by a plating method.

【0020】また前記絶縁基体1の下面において配線層
8に接合されている外部リードピン10は鉄ーニッケル
ーコバルト合金や鉄ーニッケル合金、銅等の金属材料か
ら成り、半導体素子3の各電極を外部電気回路に電気的
に接続する用をなす。
The external lead pins 10 bonded to the wiring layer 8 on the lower surface of the insulating substrate 1 are made of a metal material such as iron-nickel-cobalt alloy, iron-nickel alloy, and copper, and each electrode of the semiconductor element 3 is externally connected. Used to electrically connect to an electric circuit.

【0021】前記外部リードピン10は鉄ーニッケルー
コバルト合金等のインゴット(塊)を圧延加工法や打ち
抜き加工法等、従来周知の金属加工法を採用することに
よって所定形状に形成される。
The external lead pin 10 is formed in a predetermined shape by adopting a conventionally known metal working method such as a rolling working method or a punching working method for an ingot (lump) of iron-nickel-cobalt alloy or the like.

【0022】前記外部リードピン10は例えば、融点が
500℃以下の金属材料からなるロウ材、具体的には、
10〜50重量%のインジウムまたは錫と、10〜70
重量%の銀と、10〜75重量%のアンチモンと、10
重量%以下の銅とから成る合金、15〜25重量%の錫
と、75〜85重量%の金とから成る合金、10〜15
重量%のゲルマニウムと、85〜90重量%の金とから
成る合金、鉛と、錫、インジウム、アンチモン、ビスマ
スの少なくとも1種との合金等を使用することによって
絶縁基体1の下面で配線層8に接合される。
The external lead pin 10 is, for example, a brazing material made of a metal material having a melting point of 500 ° C. or less, specifically,
10 to 50% by weight of indium or tin, and 10 to 70
10% by weight silver, 10-75% by weight antimony
Alloys consisting of up to 15% by weight of copper, 15 to 25% by weight of tin and 75 to 85% by weight of gold, 10 to 15
The wiring layer 8 is formed on the lower surface of the insulating substrate 1 by using an alloy of germanium of 85 wt% and gold of 85 to 90 wt%, an alloy of lead and at least one of tin, indium, antimony and bismuth. To be joined to.

【0023】前記融点が500℃以下の金属材料からな
るロウ材を使用して外部リードピン10を絶縁基体1の
下面で配線層8に接合させた場合、ロウ付けの際のロウ
材を加熱溶融させる温度が低く、ロウ材の加熱溶融の熱
によって絶縁基体1が大きく変形することはなく、これ
によって絶縁基体1に設けられている配線層8に断線等
を招来するのを有効に防止することができる。
When the external lead pin 10 is bonded to the wiring layer 8 on the lower surface of the insulating substrate 1 by using a brazing material made of a metal material having a melting point of 500 ° C. or less, the brazing material at the time of brazing is heated and melted. Since the temperature is low and the insulating base material 1 is not largely deformed by the heat of heating and melting the brazing material, it is possible to effectively prevent the wiring layer 8 provided on the insulating base material 1 from being broken. it can.

【0024】かくして、上述の半導体素子収納用パッケ
ージよれば、絶縁基体1の凹部1a内に半導体素子3を
接着材を介して搭載固定するとともに半導体素子3の各
電極をボンディングワイヤ等の電気的接続手段9を介し
て配線層8に接続し、しかる後、絶縁基体1の上面に蓋
体2をガラス、樹脂、ロウ材等の封止部材を介して接合
させ、絶縁基体1と蓋体2とから成る容器内部に半導体
素子3を気密に封止することによって製品としての半導
体装置となる。
Thus, according to the above-mentioned package for accommodating semiconductor elements, the semiconductor element 3 is mounted and fixed in the recess 1a of the insulating substrate 1 via the adhesive, and each electrode of the semiconductor element 3 is electrically connected by a bonding wire or the like. It is connected to the wiring layer 8 via the means 9, and then the lid 2 is joined to the upper surface of the insulating base 1 via a sealing member such as glass, resin, or brazing material to form the insulating base 1 and the lid 2. A semiconductor device as a product is obtained by hermetically sealing the semiconductor element 3 inside a container made of.

【0025】かかる半導体装置は外部リードピン10を
外部電気回路基板の配線導体(不図示)に半田等を介し
て接続すれば、容器内部に収容する半導体素子3の各電
極は外部リードピン10、配線層8及び電気的接続手段
9を介して外部電気回路基板の配線導体に接続されるこ
ととなり、半導体素子3と外部電気回路基板の配線導体
との間で電気信号の出し入れが可能となる。
In such a semiconductor device, when the external lead pin 10 is connected to a wiring conductor (not shown) of an external electric circuit board via solder or the like, the electrodes of the semiconductor element 3 housed inside the container are the external lead pin 10 and the wiring layer. 8 and the electrical connection means 9 are connected to the wiring conductor of the external electric circuit board, so that an electric signal can be taken in and out between the semiconductor element 3 and the wiring conductor of the external electric circuit board.

【0026】本発明においては絶縁基体1を構成する各
絶縁層4、5、6をSiO2 ーAl2 3 ーMgOーZ
nOーB2 3 系結晶性ガラスで形成することが重要で
ある。
In the present invention, the insulating layers 4, 5 and 6 constituting the insulating substrate 1 are formed of SiO 2 —Al 2 O 3 —MgO—Z.
It is important to use nO-B 2 O 3 based crystalline glass.

【0027】このSiO2 ーAl2 3 ーMgOーZn
OーB2 3 系結晶性ガラスは、例えば、SiO2 :4
0〜46重量%、Al2 3 :25〜30重量%、Mg
O:8〜13重量%、ZnO:6〜9重量%、B
2 3 :8〜11重量%で形成されている。
This SiO 2 --Al 2 O 3 --MgO--Zn
The OB 2 O 3 based crystalline glass is, for example, SiO 2 : 4.
0 to 46% by weight, Al 2 O 3 : 25 to 30% by weight, Mg
O: 8 to 13% by weight, ZnO: 6 to 9% by weight, B
2 O 3 : 8 to 11% by weight.

【0028】前記SiO2 ーAl2 3 ーMgOーZn
OーB2 3 系結晶性ガラスは、焼成時にガーナイト
(ZnO・Al2 3 )、コージェライト(2MgO・
2Al2 3 )、スピネル型結晶相(MgO・Al2
3 、ZnO・Al2 3 )等の結晶相を生成するが、こ
れらの結晶相の生成により絶縁基体1の強度が向上する
という性質を持っている。
The above SiO 2 --Al 2 O 3 --MgO--Zn
O-B 2 O 3 -based crystalline glass is formed by firing at a temperature of garnite (ZnO.Al 2 O 3 ) or cordierite (2MgO.
2Al 2 O 3), spinel-type crystal phase (MgO · Al 2 O
3 , ZnO.Al 2 O 3 ) and other crystal phases are generated, but the strength of the insulating substrate 1 is improved by the generation of these crystal phases.

【0029】前記SiO2 ーAl2 3 ーMgOーZn
OーB2 3 系結晶性ガラスはその焼成温度が800〜
1050℃と低いことから、配線層8を銅、銀、金等の
融点が低くく、導通抵抗の低い材料としても絶縁基体1
と同時焼成によって形成することが可能となり、配線層
8を電気信号が伝搬した際、電気信号に減衰等が生じる
のを有効に防止して半導体素子3を正確に作動させるこ
とができる。
Said SiO 2 --Al 2 O 3 --MgO--Zn
The firing temperature of OB 2 O 3 based crystalline glass is 800 to
Since the wiring layer 8 has a low melting point of 1050 ° C., the insulating substrate 1 has a low melting point such as copper, silver, and gold and has a low conduction resistance.
It becomes possible to form the semiconductor element 3 by firing simultaneously, and when the electric signal propagates through the wiring layer 8, it is possible to effectively prevent the electric signal from being attenuated and the semiconductor element 3 can be operated accurately.

【0030】また前記SiO2 ーAl2 3 ーMgOー
ZnOーB2 3 系結晶性ガラスはその比誘電率が約5
(室温1MHz)と低いことから、絶縁基体1に形成し
た配線層8に電気信号を伝搬させても伝搬遅延を招来す
ることはなく、その結果、配線層8に高速で電気信号を
伝搬させることが可能となる。
The SiO 2 -Al 2 O 3 -MgO-ZnO-B 2 O 3 -based crystalline glass has a relative dielectric constant of about 5
Since it is as low as (room temperature 1 MHz), propagation of an electric signal to the wiring layer 8 formed on the insulating substrate 1 does not cause propagation delay, and as a result, the electric signal can be propagated to the wiring layer 8 at high speed. Is possible.

【0031】なお、前記SiO2 ーAl2 3 ーMgO
ーZnOーB2 3 系結晶性ガラスは、SiOの量が4
0重量%未満、或いは46重量%を超えるとSiO2
Al2 3 ーMgOーZnOーB2 3 系結晶性ガラス
の焼成温度が高いものとなって銅等の金属材料からなる
配線層8を同時に焼成するのが困難となる。従って、S
iO2 の量は40〜46重量%の範囲としておくことが
好ましい。
The above-mentioned SiO 2 --Al 2 O 3 --MgO
Over ZnO over B 2 O 3 based crystalline glass, the amount of SiO 4
If it is less than 0% by weight or exceeds 46% by weight, the SiO 2 —Al 2 O 3 —MgO—ZnO—B 2 O 3 -based crystalline glass has a high firing temperature and is a wiring layer made of a metal material such as copper. It becomes difficult to fire 8 at the same time. Therefore, S
The amount of iO 2 is preferably set in the range of 40 to 46% by weight.

【0032】またAl2 3 の量が25重量%未満、或
いは30重量%を超えるとSiO2ーAl2 3 ーMg
OーZnOーB2 3 系結晶性ガラスの焼成温度が高い
ものとなって銅等の金属材料からなる配線層8を同時に
焼成するのが困難となる。従って、Al2 3 の量は2
5〜30重量%の範囲としておくことが好ましい。
If the amount of Al 2 O 3 is less than 25% by weight or exceeds 30% by weight, SiO 2 -Al 2 O 3 -Mg
The firing O over ZnO over B 2 O 3 system interconnection layer 8 baking temperature of the crystallizable glass is made of a metal material such as copper becomes high at the same time is difficult. Therefore, the amount of Al 2 O 3 is 2
It is preferably set in the range of 5 to 30% by weight.

【0033】またMgOの量が8重量%未満となると焼
成によってSiO2 ーAl2 3 ーMgOーZnOーB
2 3 系結晶性ガラスからなる絶縁基体1を製作する
際、生成するコージェライト(2MgO・2Al
2 3 )の量が少なくなって絶縁基体1の強度を大きく
向上させることができず、また13重量%を超えるとS
iO2ーAl2 3 ーMgOーZnOーB2 3 系結晶
性ガラスの焼成温度が高いものとなって銅等の金属材料
からなる配線層8を同時に焼成するのが困難となる。従
って、MgOの量は8〜13重量%の範囲としておくこ
とが好ましい。
When the amount of MgO is less than 8% by weight, firing is performed to obtain SiO 2 --Al 2 O 3 --MgO--ZnO--B.
Cordierite (2MgO.2Al) generated when the insulating substrate 1 made of 2 O 3 type crystalline glass is manufactured.
The amount of 2 O 3 ) decreases and the strength of the insulating substrate 1 cannot be greatly improved, and when it exceeds 13% by weight, S
iO 2 over Al 2 O 3 that is baked over MgO over ZnO over B 2 O 3 based wiring layer 8 made of a metal material such as copper is as firing temperature of the crystallizable glass is high at the same time difficult. Therefore, the amount of MgO is preferably set in the range of 8 to 13% by weight.

【0034】またZnOの量が6重量%未満となると焼
成によってSiO2 ーAl2 3 ーMgOーZnOーB
2 3 系結晶性ガラスからなる絶縁基体1を製作する
際、生成するガーナイト(ZnO・Al2 3 )の量が
少なくなって絶縁基体1の強度を大きく向上させること
ができず、また9重量%を超えるとSiO2 ーAl2
3 ーMgOーZnOーB2 3 系結晶性ガラスの焼成温
度が高いものとなって銅等の金属材料からなる配線層8
を同時に焼成するのが困難となる。従って、ZnOの量
は6〜9重量%の範囲としておくことが好ましい。
When the amount of ZnO is less than 6% by weight, firing is performed to obtain SiO 2 --Al 2 O 3 --MgO--ZnO--B.
When the insulating substrate 1 made of 2 O 3 -based crystalline glass is produced, the amount of garnite (ZnO.Al 2 O 3 ) produced is small and the strength of the insulating substrate 1 cannot be greatly improved. SiO 2 -Al 2 O when it exceeds the weight percentage
3 over MgO over ZnO over B 2 O 3 system firing temperature of the crystalline glass is made of a metal material such as copper becomes high wiring layer 8
It becomes difficult to bake them simultaneously. Therefore, the amount of ZnO is preferably set in the range of 6 to 9% by weight.

【0035】またB2 3 の量が8重量%未満となると
焼成によってSiO2 ーAl2 3ーMgOーZnOー
2 3 系結晶性ガラスからなる絶縁基体1を製作する
際、ガーナイト(ZnO・Al2 3 )、コージェライ
ト(2MgO・2Al2 3)、スピネル型結晶相(M
gO・Al2 3 、ZnO・Al2 3 )等の結晶相が
過剰に生成され、絶縁基体1が多孔質のものとなって容
器の気密の信頼性が大きく低下してしまい、また11重
量%を超えると耐薬品性が大きく低下し、半導体阻止収
納用パッケージの信頼性が低下してしまう。従って、B
2 3 の量は8〜11重量%の範囲としておくことが好
ましい。
Further in fabricating the insulating base 1, the amount of B 2 O 3 is made of SiO 2 over Al 2 O 3 over MgO over ZnO over B 2 O 3 based crystalline glass by firing less than 8 wt%, gahnite (ZnO · Al 2 O 3) , cordierite (2MgO · 2Al 2 O 3) , spinel-type crystal phase (M
Crystal phases such as gO.Al 2 O 3 and ZnO.Al 2 O 3 ) are excessively generated, the insulating substrate 1 becomes porous, and the reliability of the airtightness of the container is greatly reduced. If it exceeds 5% by weight, the chemical resistance is greatly reduced, and the reliability of the semiconductor blocking storage package is reduced. Therefore, B
The amount of 2 O 3 is preferably set in the range of 8 to 11% by weight.

【0036】また本発明においては、前記絶縁基体1を
構成する絶縁層4、5、6のうち少なくとも最下層の絶
縁層4に磁性材料を含有させて磁性絶縁層4aとしてお
くことが重要である。
Further, in the present invention, it is important that at least the lowermost insulating layer 4 among the insulating layers 4, 5, 6 constituting the insulating substrate 1 contains a magnetic material to form the magnetic insulating layer 4a. .

【0037】前記絶縁基体1の最下層を磁性絶縁層4a
としておく外部リードピン10を外部電気回路基板の配
線導体に接続させ、半導体素子3と外部電気回路との間
で電気信号の出し入れをする場合、外部電気回路基板の
配線導体より配線層8にノイズが入り込もうとしてもそ
のノイズは絶縁基体1の最下層に位置する磁性絶縁層4
aに含有されている磁性材料で熱エネルギーに変換され
吸収されて配線層8に入り込むことはなく、その結果、
ノイズが配線層8を伝搬し半導体素子3に入り込みこと
は殆どなく、これによって半導体素子3を常に正常に作
動させることが可能となる。
The lowermost layer of the insulating substrate 1 is the magnetic insulating layer 4a.
When the external lead pin 10 is connected to the wiring conductor of the external electric circuit board and an electric signal is input and output between the semiconductor element 3 and the external electric circuit, noise is generated in the wiring layer 8 from the wiring conductor of the external electric circuit board. Even if it tries to enter, the noise is generated in the magnetic insulating layer 4 located at the lowermost layer of the insulating substrate 1.
The magnetic material contained in a does not convert into heat energy and is absorbed and does not enter the wiring layer 8. As a result,
The noise hardly propagates through the wiring layer 8 and enters the semiconductor element 3, which allows the semiconductor element 3 to always operate normally.

【0038】なお、前記磁性絶縁層4aは、SiO2
Al2 3 ーMgOーZnOーB2O3 系結晶性ガラスの
焼成温度が800〜1050℃と低いことから焼成時、
磁性材料の磁性が失われることはなく、これによって配
線層8に入り込んだノイズを良好に吸収することが可能
となる。
[0038] Incidentally, the magnetic insulating layer 4a is during firing since the firing temperature of the SiO 2 chromatography Al 2 O 3 over MgO over ZnO over B 2 O 3 based crystalline glass is 800 to 1050 ° C. and lower,
The magnetism of the magnetic material is not lost, and this makes it possible to favorably absorb noise that has entered the wiring layer 8.

【0039】前記磁性絶縁層4aに含有される磁性材料
としてはZnFe2 4 、MnFe2 4 、FeFe2
4 、CoFe2 4 、NiFe2 4 、CuFe2
4 の少なくとも1種が好適に使用され、例えば、焼成に
よって絶縁層4となるグリーンシートに、ZnFe2
4 、MnFe2 4 、FeFe2 4 、CoFe
2 4 、NiFe2 4 、CuFe2 4 の少なくとも
1種から成る磁性粉末を添加含有させておくことによっ
て絶縁層4内に含有され、磁性絶縁層4aとなる。
The magnetic material contained in the magnetic insulating layer 4a includes ZnFe 2 O 4 , MnFe 2 O 4 and FeFe 2.
O 4 , CoFe 2 O 4 , NiFe 2 O 4 , CuFe 2 O
At least one of 4 is preferably used. For example, ZnFe 2 O is added to the green sheet that becomes the insulating layer 4 by firing.
4 , MnFe 2 O 4 , FeFe 2 O 4 , CoFe
A magnetic powder made of at least one of 2 O 4 , NiFe 2 O 4 , and CuFe 2 O 4 is added and contained in the insulating layer 4 to form the magnetic insulating layer 4a.

【0040】また前記磁性絶縁層4aは磁性材料が90
重量%を超える、言い換えるとSiO2 ーAl2 3
MgOーZnOーB2 3 系結晶性ガラスの量が10重
量%未満となるとSiO2 ーAl2 3 ーMgOーZn
OーB2 3 系結晶性ガラスの焼成温度が高いものとな
って銅等の金属材料からなる配線層8を同時に焼成する
のが困難となり、また磁性材料が50重量%未満、言い
換えるとSiO2 ーAl2 3 ーMgOーZnOーB2
3 系結晶性ガラスの量が50重量%を超えると、外部
電気回路基板の配線導体より配線層8にノイズが入り込
むのを良好に防止することができず、半導体素子3に誤
動作を起こさせてしまう。従って、前記磁性絶縁層4a
は磁性材料の量を50〜90重量%の範囲にしておくこ
とが好ましい。
The magnetic insulating layer 4a is made of a magnetic material of 90%.
If the amount of the crystalline glass in excess of 10% by weight, that is, SiO 2 —Al 2 O 3 —MgO—ZnO—B 2 O 3 is less than 10% by weight, SiO 2 —Al 2 O 3 —MgO—Zn
Since the firing temperature of the OB 2 O 3 -based crystalline glass becomes high, it becomes difficult to simultaneously fire the wiring layer 8 made of a metal material such as copper, and the magnetic material is less than 50% by weight, in other words, SiO. 2 -Al 2 O 3 -MgO-ZnO-B 2
If the amount of the O 3 -based crystalline glass exceeds 50% by weight, it is not possible to properly prevent noise from entering the wiring layer 8 from the wiring conductor of the external electric circuit board, which causes the semiconductor element 3 to malfunction. Will end up. Therefore, the magnetic insulating layer 4a
It is preferable to keep the amount of the magnetic material in the range of 50 to 90% by weight.

【0041】更に前記磁性材料はその粒径が0.5μm
未満となると焼成によってSiO2ーAl2 3 ーMg
OーZnOーB2 3 系結晶性ガラスからなる絶縁基体
1を製作する際、SiO2 ーAl2 3 ーMgOーZn
OーB2 3 系結晶性ガラスとの反応が進行し磁性材料
の残存率が低下してノイズを効果的に吸収することがで
きなくなり、また10μmを超えるとSiO2 ーAl2
3 ーMgOーZnOーB2 3 系結晶性ガラスの焼成
温度が高いものとなって銅等の金属材料からなる配線層
8と同時に焼成するのが困難となる。従って、前記磁性
材料はその粒径を0.5μm〜10μmの範囲とする。
Further, the magnetic material has a particle size of 0.5 μm.
If it is less than the above, it is calcined by firing SiO 2 -Al 2 O 3 -Mg
When manufacturing the insulating substrate 1 made of O—ZnO—B 2 O 3 based crystalline glass, SiO 2 —Al 2 O 3 —MgO—Zn
When the reaction with the OB 2 O 3 -based crystalline glass proceeds, the residual ratio of the magnetic material decreases and it becomes impossible to effectively absorb noise, and when it exceeds 10 μm, SiO 2 —Al 2
Since the O 3 —MgO—ZnO—B 2 O 3 -based crystalline glass has a high firing temperature, it becomes difficult to fire it simultaneously with the wiring layer 8 made of a metal material such as copper. Therefore, the particle size of the magnetic material is in the range of 0.5 μm to 10 μm.

【0042】また更に前記絶縁基体1を構成する磁性絶
縁層4及び絶縁層5、6はその内部に無機物フィラー,
具体的にはアルミナ、シリカ、窒化珪素、窒化アルミニ
ウム等の粉末を外添加で10〜40重量部添加含有させ
ているため、機械的強度が大幅に向上し、外力印加によ
って破損等を招来するのが有効に防止される。従って、
絶縁基体1の機械的強度を向上させ、外力印加によって
破損等を招来しないようにするのはSiO2 ーAl2
3 ーMgOーZnOーB2 3 系結晶性ガラスから成る
磁性絶縁層4及び絶縁層5、6に無機物フィラーを外添
加で10〜40重量部添加含有させておくこととする。
Furthermore, the magnetic insulating layer 4 and the insulating layers 5 and 6 which constitute the insulating base 1 have an inorganic filler,
Specifically, powder of alumina, silica, silicon nitride, aluminum nitride or the like is added externally and contained in an amount of 10 to 40 parts by weight, so that the mechanical strength is significantly improved, and damage or the like is caused by the application of external force. Is effectively prevented. Therefore,
It is SiO 2 -Al 2 O that improves the mechanical strength of the insulating substrate 1 and prevents damage or the like from being applied by an external force.
3 over MgO over ZnO over B 2 O 3 based inorganic filler outer 10 to 40 parts by weight additives are contained in addition to the magnetic insulating layer 4 and the insulating layers 5 and 6 made of crystalline glass and it kept.

【0043】前記絶縁基体1を構成する磁性絶縁層4及
び絶縁層5、6に無機物フィラーを添加含有させる場
合、無機物フィラーの粒径を0.5〜5μmの範囲とし
ているため、無機物フィラーがガラスセラミック焼結体
中に均一に分散含有されて磁性絶縁層4及び絶縁層5、
6から成る絶縁基体1の機械的強度を均一に向上させる
ことができる。従って、前記無機物フィラーはその粒径
を0.5〜5μmの範囲とする。
When an inorganic filler is added to the magnetic insulating layer 4 and the insulating layers 5 and 6 constituting the insulating substrate 1, since the particle diameter of the inorganic filler is in the range of 0.5 to 5 μm, the inorganic filler is glass. The magnetic insulating layer 4 and the insulating layer 5 are uniformly dispersed and contained in the ceramic sintered body.
The mechanical strength of the insulating substrate 1 made of 6 can be improved uniformly. Therefore, the particle size of the inorganic filler is in the range of 0.5 to 5 μm.

【0044】なお、本発明は上述の実施例に限定される
ものではなく、本発明の要旨を逸脱しない範囲であれば
種々の変更は可能であり、例えば、上述の実施例におい
ては外部リードピン10を外部電気回路基板の配線導体
に接続させることによって半導体素子3の各電極が外部
電気回路に接続されるようになっているが、外部リード
ピンを設けず、絶縁基体1の下面に導出する配線層8を
そのまま外部電気回路基板の配線導体に接続させるよう
にしてもよい。
The present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the present invention. For example, in the above-mentioned embodiments, the external lead pin 10 is used. Is connected to the wiring conductor of the external electric circuit board so that each electrode of the semiconductor element 3 is connected to the external electric circuit. However, the wiring layer extending to the lower surface of the insulating base 1 without providing the external lead pin. 8 may be directly connected to the wiring conductor of the external electric circuit board.

【0045】また上述の実施例では絶縁基体1を3つの
絶縁層4,5,6で形成したが、これを2つの絶縁層で
形成しても、また4つ以上の絶縁層で形成してもよい。
Further, in the above-mentioned embodiment, the insulating substrate 1 is formed of three insulating layers 4, 5 and 6, but it may be formed of two insulating layers or four or more insulating layers. Good.

【0046】更に上述の実施例では絶縁基体1の最下層
の絶縁層4のみを磁性絶縁層4aとしたが、全ての絶縁
層に磁性材料を含有させて磁性絶縁層としてもよい。
Further, in the above-mentioned embodiments, only the lowermost insulating layer 4 of the insulating substrate 1 is the magnetic insulating layer 4a, but all the insulating layers may be made to contain a magnetic material to form the magnetic insulating layer.

【0047】[0047]

【発明の効果】本発明の半導体素子収納用パッケージに
よれば、上面に半導体素子が搭載される搭載部を有し、
該搭載部より下面にかけて複数個の配線層が被着形成さ
れている絶縁基体を複数のSiO2 ーAl2 3 ーMg
OーZnOーB2 3 系結晶性ガラスから成る絶縁層を
積層して形成するとともに少なくとも最下層の絶縁層に
磁性材料を含有させて磁性絶縁層としたことから外部電
気回路基板の配線導体より配線層にノイズが入り込もう
としてもそのノイズは絶縁基体の最下部に位置する磁性
絶縁層に含有されている磁性材料で熱エネルギーに変換
されて吸収され、その結果、ノイズが配線層に入り込ん
で半導体素子に伝搬することはなく、半導体素子を常に
正常に作動させることが可能となる。
According to the package for accommodating a semiconductor element of the present invention, it has a mounting portion on which a semiconductor element is mounted,
An insulating substrate on which a plurality of wiring layers are formed from the mounting portion to the lower surface is formed into a plurality of SiO 2 —Al 2 O 3 —Mg
The wiring conductor of the external electric circuit board is formed by stacking insulating layers made of O-ZnO-B 2 O 3 -based crystalline glass and forming a magnetic insulating layer by including a magnetic material in at least the lowermost insulating layer. Even if noise tries to enter the wiring layer, the noise is converted into heat energy and absorbed by the magnetic material contained in the magnetic insulating layer located at the bottom of the insulating substrate, and as a result, the noise enters the wiring layer. Therefore, the semiconductor element can be always operated normally without being propagated to the semiconductor element.

【0048】また本発明の半導体素子収納用パッケージ
によれば、絶縁基体を構成する絶縁層がSiO2 ーAl
2 3 ーMgOーZnOーB2 3 系結晶性ガラスで形
成されており、該SiO2 ーAl2 3 ーMgOーZn
OーB2 3 系結晶性ガラスはその焼成温度が850〜
1000℃と低いことからこの結晶性ガラス中に磁性材
料を含有させて焼成しても磁性材料は磁性を失うことは
なく、ノイズを良好に吸収することが可能となる。
Further, according to the package for accommodating semiconductor elements of the present invention, the insulating layer constituting the insulating substrate is made of SiO 2 -Al.
2 O 3 —MgO—ZnO—B 2 O 3 type crystalline glass, and the SiO 2 —Al 2 O 3 —MgO—Zn
The firing temperature of OB 2 O 3 -based crystalline glass is 850 to
Since the temperature is as low as 1000 ° C., the magnetic material does not lose its magnetism even if the crystalline glass is mixed with a magnetic material and fired, and noise can be absorbed well.

【0049】同時にSiO2 ーAl2 3 ーMgOーZ
nOーB2 3 系結晶性ガラスの焼成温度が低いことか
ら銅、銀、金等の融点が低くく、導通抵抗の低い材料か
ら成る配線層を同時焼成によって形成することが可能と
なり、配線層を電気信号が伝搬した際、電気信号に減衰
等が生じるのを有効に防止して半導体素子を正確に作動
させることもできる。
At the same time, SiO 2 --Al 2 O 3 --MgO--Z
Since the firing temperature of the nO-B 2 O 3 -based crystalline glass is low, it is possible to form a wiring layer made of a material having a low melting point, such as copper, silver, and gold, and a low conduction resistance by simultaneous firing. When the electric signal propagates through the layer, it is possible to effectively prevent the electric signal from being attenuated or the like and operate the semiconductor element accurately.

【0050】更に絶縁基体を構成するSiO2 ーAl2
3 ーMgOーZnOーB2 3 系結晶性ガラスに無機
物フィラーを外添加で10〜40重量部の範囲で含有さ
せているので、SiO2 ーAl2 3 ーMgOーZnO
ーB2 3 系結晶性ガラスの機械的強度が強くなり、こ
れによって絶縁基体に外力等が印加されても破損等が発
生するのを有効に防止することができる。
The SiO 2 chromatography Al 2 further constituting the insulating substrate
Since an inorganic filler is externally added to O 3 —MgO—ZnO—B 2 O 3 -based crystalline glass in the range of 10 to 40 parts by weight, SiO 2 —Al 2 O 3 —MgO—ZnO
The mechanical strength of the —B 2 O 3 -based crystalline glass is strengthened, and thereby, it is possible to effectively prevent the occurrence of damage or the like even when an external force or the like is applied to the insulating substrate.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。
FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor element housing package of the present invention.

【符号の説明】[Explanation of symbols]

1・・・・・・絶縁基体 2・・・・・・蓋体 3・・・・・・半導体素子 4、5、6・・絶縁層 4a・・・・・磁性絶縁層 1 ... Insulating substrate 2 ... Lid 3 ・ ・ Semiconductor element 4, 5, 6 ... Insulating layer 4a ... Magnetic insulating layer

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 上面に半導体素子が搭載される搭載部を
有し、該搭載部より下面にかけて導出される電気抵抗率
が3μΩ・cm以下の複数個の配線層を有する絶縁基体
と、前記絶縁基体に取着され、搭載部に搭載される半導
体素子を封止する蓋体とから成る半導体素子収納用パッ
ケージであって、前記絶縁基体を複数のSiO2 ーAl
2 3 ーMgOーZnOーB2 3 系結晶性ガラスから
成る絶縁層を積層して前記配線層と同時焼成によって
成するとともに少なくとも最下層の絶縁層に粒径が0.
5μm〜10μmの磁性材料を含有させて磁性絶縁層と
、前記磁性絶縁層に、粒径が0.5〜5μmの無機物
フィラーを外添加で10〜40重量部含有させたことを
特徴とする半導体素子収納用パッケージ。
1. An electrical resistivity which has a mounting portion on which a semiconductor element is mounted and which is led out from the mounting portion to the lower surface.
A package for storing a semiconductor element, comprising: an insulating base having a plurality of wiring layers of 3 μΩ · cm or less ; and a lid attached to the insulating base and sealing a semiconductor element mounted on a mounting portion. , The insulating substrate is made of a plurality of SiO 2 -Al
An insulating layer made of 2 O 3 —MgO—ZnO—B 2 O 3 -based crystalline glass is laminated and formed by co-firing with the wiring layer, and at least the lowermost insulating layer has a grain size of 0. .
A magnetic insulating layer containing a magnetic material of 5 μm to 10 μm, wherein the magnetic insulating layer has an inorganic particle size of 0.5 to 5 μm
A package for accommodating a semiconductor device, characterized in that a filler is added externally to contain 10 to 40 parts by weight .
【請求項2】 前記磁性絶縁層における磁性材料の含有
量が50〜90重量%であることを特徴とする請求項1
に記載の半導体素子収納用パッケージ。
2. The content of the magnetic material in the magnetic insulating layer is 50 to 90% by weight.
The package for storing a semiconductor element according to.
JP33908497A 1997-12-09 1997-12-09 Package for storing semiconductor elements Expired - Fee Related JP3526526B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33908497A JP3526526B2 (en) 1997-12-09 1997-12-09 Package for storing semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33908497A JP3526526B2 (en) 1997-12-09 1997-12-09 Package for storing semiconductor elements

Publications (2)

Publication Number Publication Date
JPH11176990A JPH11176990A (en) 1999-07-02
JP3526526B2 true JP3526526B2 (en) 2004-05-17

Family

ID=18324112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33908497A Expired - Fee Related JP3526526B2 (en) 1997-12-09 1997-12-09 Package for storing semiconductor elements

Country Status (1)

Country Link
JP (1) JP3526526B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100377472B1 (en) * 1999-12-10 2003-03-26 앰코 테크놀로지 코리아 주식회사 semiconductor package and its manufacturing method
KR100377470B1 (en) * 1999-12-10 2003-03-26 앰코 테크놀로지 코리아 주식회사 semiconductor package

Also Published As

Publication number Publication date
JPH11176990A (en) 1999-07-02

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