JP3528124B2 - Frame format converter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame format conversion device, and more particularly to SDH (Synchronouou) for data signals of 2016 lines multiplexed with an in-device frame signal.
s Digital Hierarchy) STM (Synchronous Tr
ansport Module) -1 multiplex format conversion method for mapping on a signal.

[0002]

2. Description of the Related Art An example of this type of frame format conversion system will be described with reference to FIG. The in-device frame format 1 is composed of main information and vacant bits, and as shown in 2 and 3, data strings IN # are parallel to each other.
1 to IN # 9 (parallel 9 bits). A signal having this in-device frame format 1 is transmitted by the ITU-
T recommendation NNI (network node interface)
It is necessary to convert the frame format 5 and send it to the network.

The NNI frame format 5 is composed of main information, a fixed stack signal R, SHO (section overhead), and POH (path overhead), and as shown in 4, parallel data strings OUT. #
1 to # 8 (parallel 8 bits).

[0004]

In order to convert the in-apparatus frame format to the NNI frame format, it is necessary to convert the number of data strings (the number of parallel bits) differently (from 9 bits to 8 bits). Therefore, there is a drawback that the circuit configuration becomes complicated.

An object of the present invention is to provide a frame format conversion device capable of converting an in-device frame format to an NNI frame format with a simple structure.

Another object of the present invention is to provide a frame format conversion device capable of efficiently performing frame replacement in an interface (9 bits → 8 bits) in which the number of parallel data (bit number) of the frame format is different. It is to be.

[0007]

According to the present invention, the in-device frame format signals for the first to Nth (N is an integer of 2 or more) lines which are input in parallel with each other are output in parallel with each other. A frame format conversion device for converting the first to Mth (M is an integer of 2 or more) network node interface (NNI) frame format signals corresponding to the first to Nth in-device frame format signals. First to N-th, which are provided in order to sequentially capture and store M bits of the frame format signal in the corresponding device.
Storage means, first to Mth signal deriving means for deriving the first to Mth NNI frame format signals, and storage of corresponding storage means provided corresponding to the first to Nth storage means. First to Nth selecting means for selectively distributing bits to the first to Mth signal deriving means respectively;
There is provided a frame format conversion device including a selection control unit that controls the bit selection distribution of the Nth selection unit.

The first to Nth in-apparatus frame format signals are divided into blocks for every M bits, and conversion is performed in block units. Further, each of the first to Nth storage means shifts while sequentially taking in the frame format signal in the corresponding device.
The NNI frame format signal is an SDH ST
It is characterized by being an M-1 signal.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a format showing an example of a signal sequence in the embodiment of the present invention. The in-apparatus frame format 1 is composed of main information and empty bits, and the NNI frame format 5 is main information and information such as transmission line management. (SHO and POH). As shown in 2 and 3, the in-device frame format 1 is the line data IN # 1 to IN # 9 for 9 lines (9 bits) input in parallel with each other, and the NNI frame format 5 is as shown in 4. , 8-bit parallel data OUT1
# To OUT # 8.

Therefore, in the embodiment of the present invention, 9 bits →
Since it is necessary to replace the 8-bit frame, the arrangement of each bit is devised as shown in the bit details 3 of the in-apparatus frame format and the bit details 4 of the NNI frame format. In addition, since the circuit size of the frame format conversion device can be reduced by dividing the main information into as many blocks as possible, the frame format conversion device can be divided into 252 blocks as shown in the frame format block detail 2 in the device, and one block unit The format conversion is completed with.

FIG. 2 is a block diagram showing an outline of the frame format conversion device of the present invention, and FIG. 3 is a diagram showing the details of the block in FIG. 2. In both figures, the same parts are designated by the same reference numerals. . Referring to these figures, I
The nine parallel device frame format signals N # 1 to IN # 9 correspond to the corresponding frame format conversion unit 11
~ 19 shift registers 111, 121, 131, 14
1, 151, 161, 171, 181, 191 are sequentially input, stored, and shifted.

The data stored in these shift registers correspond to the corresponding data selectors 112, 122, 132, 14 respectively.
2, 152, 162, 172, 182, 192, and P / S (parallel / parallel) of its own frame format conversion unit in response to a control signal from the selector control unit 10.
(Serial) converter 113, 123, 133, 143, 1
53, 163, 173, 183, 193, or is selectively distributed to the P / S converter of another frame format converter. Each P / S converter derives the parallel data supplied from itself or another data selector as serial data OUT # 1 to OUT # 8. The P / S converter 1 in the frame format converter 19
In the present example (the example of FIG. 1), 93 is not necessary because OUT # 9 is not provided, but it is shown in FIG. 3 in relation to other frame format conversion units.

FIG. 4 is a diagram showing a specific example of the frame format conversion section 11, in which the shift register 111 is an 8-bit register, and the timing chart 2 of FIG.
As shown in FIG. 3, when the input data example is divided into blocks of 0 to 252 and format conversion is performed in block units (8 bit units), the first block (01) of the input data string IN # 1 is sequentially A1, B1. , C1, D1, E
1, F1, G1, and H1 are shown in a shifted state while being taken in and stored.

Then, in the data selector 112,
Only the main information necessary for the output data OUT # 1 is selected from the data stored in the shift register 111, and P /
The signal is supplied to the 9-bit shift register that constitutes the S conversion unit 113. In addition, another frame format conversion unit 12
To 19 (corresponding to input data strings IN # 2 to # 9) data selectors 112, 132, 142, 152, 162, 1
The main information selectively supplied from 72, 182, 192 is also supplied to the P / S conversion unit 113. At this time, in the 9-bit shift register of the P / S converter 113, as shown in FIG. 4, A1, A9, B8, C7, D6, E5, F4, G
3, H2 is stored. By serially reading the contents of this shift register, as shown at 4 in FIG.
The NNI frame format output OUT # 1 of the first block (01) will be obtained.

Also in the data selector 112 of the frame format conversion unit 11 corresponding to the input data string IN # 1, it is necessary to appropriately distribute the bits stored in the shift register 111 to the other frame format conversion units 12 to 18. Therefore, selection control of these data selectors is performed by the selector control unit 10.

The SOH, POH and fixed stuff signal R shown at 4 and 5 in FIG. 1 are inserted in the P / S conversion section, and their insertion timing is known in advance.
These pieces of insertion information are sequentially inserted in accordance with this insertion timing, and that portion is not particularly shown.

FIG. 5 is an operation timing chart of another embodiment of the present invention, where the number of data in the in-apparatus frame format is N (N bits) and the number of data in the NNI frame format is M (M bits). This is a general case including the example of FIG. Note that N and M are N> M and N
It may be an integer having a relationship of <M and N = M.

N bit internal frame format 3
1 is converted into an M-bit NNI frame format 35, and in-apparatus frame format bit details 33 and NNI frame format bit details 3
Conversion is performed by arranging bits as shown in 4. Also,
The main information is divided into blocks as finely as possible (in the example of Fig. 5,
(Y block) and the conversion is performed in block units, thereby reducing the scale of the frame conversion circuit.

[0019]

As described above, according to the present invention, it is possible to convert frame formats having different numbers of data with a simple circuit configuration. There is also an effect that the circuit scale can be reduced by dividing the main information to be subjected to the frame format conversion into thin blocks and performing the frame format conversion in block units.

[Brief description of drawings]

FIG. 1 is an operation timing chart of an embodiment of the present invention.

FIG. 2 is a schematic block diagram of an embodiment of the present invention.

FIG. 3 is a diagram showing details of blocks in FIG. 2;

FIG. 4 is a diagram showing a part of details of the blocks of FIG. 3;

FIG. 5 is an operation timing of another embodiment of the present invention.

[Explanation of symbols]

1,31 Internal frame format 2,32 Details of frame format block in device 3,33 Details of frame format bit in device 4,34 NNI frame format bit details 5,35 NNI frame format 10 Selector control unit 11-19 Frey format converter 111,121 shift register 112,122 selector 113,123 P / S converter

Claims (4)

(57) [Claims] 1. The first to Nth (N) input in parallel with each other
Is an integer greater than or equal to 2), and the in-apparatus frame format signals for the lines are output in parallel with each other from the first to M-th (M is 2)
Network node interface (N above integer)
NI) A frame format conversion device for converting into a frame format signal, which is provided corresponding to the first to N-th in-device frame format signals and sequentially captures and stores M bits of the corresponding in-device frame format signal. First to Nth storage means, first to Mth signal derivation means for deriving the first to Mth NNI frame format signals, and corresponding to the first to Nth storage means Control means for selectively distributing the bits stored in the corresponding storage means to the first to Mth signal deriving means, respectively, and the bit selection distribution of the first to Nth selection means. And a selection control means for controlling the frame format conversion device. 2. The frame format conversion apparatus according to claim 1, wherein the first to Nth in-apparatus frame format signals are divided into blocks for every M bits and conversion is performed in block units. 3. The frame format according to claim 1, wherein each of the first to N-th storage means is an M-bit shift register that sequentially shifts the frame format signals in the corresponding device while sequentially fetching them. Converter. 4. The frame format conversion device according to claim 1, wherein the NNI frame format signal is an SDH (Synchronous Digital Hierarchy) STM (Synchronous Transport Module) -1 signal.