JP3529488B2 - Compound semiconductor crystal growth method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention relates to a compound semiconductor crystal growth <br/> how relates buried growth into the mesa structure formed by dry etching process particularly in compound semiconductor crystal growth.

[0002]

2. Description of the Related Art In recent years, large-capacity high-speed transmission has been performed due to the spread of optical communication systems. When optical transmission of even larger capacity is required in the future, from light to electricity as before,
If signal conversion such as electricity to light is performed, the transmission capacity will be significantly limited. To solve this problem, it is necessary to directly modulate the light. In other words, the module size can be reduced and high-capacity high-speed transmission can be achieved by connecting optical boards or optical waveguides instead of electrically connecting the boards with or without the optical device chips. Will be possible.

As a means for producing such an optical waveguide, there is used a method of forming a mesa stripe structure by an etching process using a mask formed on a semiconductor wafer and embedding it in another semiconductor layer. As a method of embedding this semiconductor layer, MOCVD (Metalorganic
Chemical Vapor Deposition) method. This technique
For example, in InGaAsP-based materials, the group III element I
n and Ga as raw materials of TMI (Trimethylindiu
m) and TEG (Triethylgallium), AsH3 and PH3 are used as the raw materials of As and P, which are group V elements, respectively, and these are thermally decomposed to grow crystals on the substrate. In the InGaAsP-based material, a mesa structure including an InGaAsP layer which is an active layer for propagating light is embedded by using an InP layer having a wider energy band gap (bandgap) than the active layer. In this case, there are cases where the burying is performed well depending on the difference in the mesa structure or the method for forming the mesa structure, and cases where it is not.

For example, for the etching process, a wet process using a liquid type etchant,
Although there is a dry process using gas, when a wet process is used, a mask canopy is formed due to side etching on the side surface of the mesa, and this mask can be used to successfully embed the mesa (references). : For example, El
ectronics Letters, 28 (1992) 1844-1845). However,
In the case of the mesa structure formed by the dry process, the mask eaves are not formed. Therefore, when crystal growth is performed, the mask 1 formed on the mesa structure 6a is formed as shown in FIG.
It is known that the semiconductor layer 12 has a shape overlying both sides of the mask 0, that is, an overgrowth on the mask (reference document: For example, Journal
l of Crystal Growth, 130 (1993) 287-294). However, the wet process has poor controllability, and it is difficult to form a thin mesa structure due to the presence of side etching. Also, since the etching shape largely depends on the crystal plane orientation, it is possible to move it in any direction onto the wafer. It is very difficult to form an optical waveguide. On the other hand, in the case of the dry process, the mesa can be formed in any direction regardless of the crystal plane orientation, and thus the dry process is advantageous for forming the optical waveguide. That is, in the future, in order to realize an optical integrated device, it will be essential to have a crystal growth technique in which the mesa structure formed by the dry process is well embedded.

Recently, a method for satisfactorily embedding the mesa structure formed by this dry process by using the MOCVD growth technique has been announced (reference document: Journal, for example).
of Crystal Growth, 131 (1993) 204-208). This method
This is done by introducing an etching gas containing chlorine during the growth. That is, this method is a method in which chlorine gas is mixed during crystal growth to control the crystal growth direction so that the overgrowth shape 12 shown in FIG. 4 is less likely to occur. In this case, it is feared that the device characteristics may be adversely affected, such as chlorine being mixed into the device. Further, by making the growth temperature at the time of embedded growth higher than the normal growth temperature (600 to 650 ° C.) (675 ° C.), the migration of atoms on the growth surface is increased to the (111) B plane. The mesa structure can be satisfactorily embedded by suppressing the growth of the (see References, for example, Journal of Crystal Growth, 11
4 (1991) 92-98), however, in this case, there is a problem that diffusion of impurities may adversely affect device characteristics.

[0006]

The conventional compound semiconductor crystal growth method is configured as described above, and MOCV is applied to the semiconductor mesa structure formed by the dry process.
When the embedded crystal growth is performed while introducing the chlorine gas by using the D growth technique, it is possible to satisfactorily embed the mesa structure without causing problems such as overgrowth on the mask. However, in this method, chlorine contained in the etching gas is taken into the crystal, which may adversely affect the device characteristics, and the growth temperature at the time of embedded growth is made higher than the normal growth temperature. Therefore, the method of embedding the mesa structure has a problem that the diffusion of impurities may adversely affect the device characteristics.

The present invention has been made in order to solve the above problems, and it is possible to perform good crystal burying growth on a semiconductor mesa structure, and eliminate adverse effects on device characteristics. It is an object of the present invention to provide a compound semiconductor crystal growth method capable of performing the above.

[0008]

[0009]

Means for Solving the Problems] compound semiconductor crystal growth method according to the present invention, a wafer having a semiconductor multilayer structure serving as an active layer, by dry etching using a mask patterned into a predetermined shape, according to the mask mask
Forming a semiconductor mesa stripe without causing eaves, by supplying the raw material gas on the susceptor while rotating the susceptor was placed on the wafer at a high speed higher than a predetermined rotational speed, thin on the wafer By forming a stagnant layer, (111) of the wafer in the mask is formed.
And a step of forming buried growth layers on both sides of the semiconductor mesa structure while selectively suppressing crystal growth on the B surface.

[0010]

[0011]

In the present invention, since the epitaxial crystal growth is performed while the wafer is rotated at a high speed, the thickness of the stagnant layer of the material gas on the surface of the wafer becomes thin so that the raw material species reach the substrate without being decomposed. As a result, crystal growth on the (111) B plane of the wafer is selectively suppressed.

Further, a wafer having a semiconductor laminated structure to be an active layer is used with a mask patterned into a predetermined shape.
By dry etching to create a mask eaves
A semiconductor mesa stripe structure is formed without, Ma
The optical waveguide formed by forming the buried growth layers on both sides of the semiconductor mesa stripe structure while selectively suppressing the crystal growth on the (111) B plane of the wafer in the mask has a negative influence on the device. And the like, and is not limited to the crystal plane orientation, and can be formed in any direction.

[0013]

【Example】

Example 1. Hereinafter, a susceptor high-speed rotation type MOC, which is a compound semiconductor crystal growth method according to a first embodiment of the present invention, will be described.
A dry etch mesa embedding method using a VD growth apparatus will be described.

FIG. 1 is an external structural view of the susceptor high speed rotary MOCVD growth apparatus according to the first embodiment. In the figure, reference numeral 1 is a reactor in which a susceptor 2 capable of high-speed rotation is housed, and nozzles 3 and 4 connected to the upper part thereof.
As a result, a group III source gas and a group V source gas, which are source gases, are introduced. Reference numeral 5 is a flow rate adjusting valve arranged in the branched nozzles 3 and 4. A plurality of wafers 6 are arranged on the upper surface of the susceptor 2.
Using such a device, the group III and V source gas is introduced onto the wafer 6 set on the susceptor 2 rotating at high speed and heated to the growth temperature, and the introduced group III, The group V source gas is pyrolyzed to cause crystal growth on the wafer 6.

Hereinafter, the susceptor high speed rotary MOCVD will be described.
The principle of the crystal growth method using the growth apparatus will be described in detail. The InP wafer to be set has the following plane orientation:
It has a (001) plane and has a mesa structure (6 in FIG. 2).
a) is R using a gas such as C2 H6 / H2 system.
It is formed in the [110] direction by a dry process by IE (Reactive Ion Etching) and has a mesa width of, for example, 1.5.
Since the μm and the mesa height are set to 2.5 μm, for example, the thickness of the stagnant layer 7 on the wafer is equal to that of a normal lateral MO.
The stagnation layer 8 of the CVD growth apparatus is much thinner than that in the stagnation layer 8 (Fig. 5 (b)) (Fig. 5 (a)), and usually becomes a diffusion state in the stagnation layer 8 and is thermally decomposed. The raw material species will reach the substrate without being decomposed. Therefore, PH3
The decomposition efficiency of V decreases to V / III ([PH3] /
[TMI]) ratio decreases. When the V / III ratio decreases,
On the (111) B plane, which is the group V stabilization plane, the surface migration length of the group III raw material species becomes long, and (111) B
Growth on the surface will be suppressed. For this reason,
As shown in FIG. 5, the (111) B surface 9a extending from the end of the mask 10 is formed in the buried growth layer 11. Once, (11
1) When the B surface 9a is formed, the same effect (11
1) Upward growth (111) with growth on the B side suppressed
The B side will be extended. Therefore, the growth that covers the mask 10 is suppressed, and good selective embedded growth can be performed.

The quality relationship of the embedding shape with respect to the rotation speed of the susceptor and the growth temperature will be described in detail below with reference to FIG. Even if the susceptor high speed rotation type MOCVD growth apparatus is used, if the susceptor rotation speed is less than 200 rpm (revolutions / second),
The stagnant layer, which is a characteristic of high-speed rotation of the susceptor, is not thin enough and becomes equivalent to a normal lateral MOCVD growth device, and the V / III ratio does not decrease substantially.
1) The surface migration length of the group III source species on the B-plane does not extend, and as shown in FIG. 4, growth 12 occurs on the (111) B-plane. Therefore, overgrowth on the mask 10 occurs, and good selective embedded growth cannot be realized. Reference numeral 9b in FIG. 4 indicates an imaginary line of the (111) B plane formed during favorable burying growth. Even if the growth temperature is high, if the rotation speed is low, the reactor 1
It is not possible to maintain the laminar flow of the internal gas, and the material gas causes convection and the reaction of the material gas in the vapor phase occurs, resulting in a large film thickness distribution within the wafer surface and surface roughness. Will be caused. Therefore, in order to satisfactorily embed the dry etch mesa 6a, it is necessary to use the susceptor high-speed rotary MOCVD growth apparatus and set the susceptor rotation speed to 200 rpm or more.

As already described in the section of the prior art, when the growth temperature is generally high, the dry etch mesa 6a can be filled with the crystal growth layer without overgrowing on the mask 10. However, when the growth temperature is lowered, the growth layer covers the mask 10. However, if the growth temperature is high, diffusion of impurities will occur, so it is desirable to carry out buried growth at a temperature as low as possible. As shown in the experimental data of FIG. 3, when the susceptor high-speed rotation MOCVD growth apparatus is used, it is possible to perform favorable selective embedded growth up to a low temperature of 580 ° C.

A semiconductor laser manufactured by using the wafer grown by the above-mentioned manufacturing method will be described below with reference to FIG. First, p-type InP (00
1) A p-InP clad layer 21 is sequentially formed on the substrate 20.
(Thickness 2 μm, carrier concentration p = 1 × 10 ¹⁸ cm ⁻³ ),
Undoped InGaAsP active layer 22 having 1.3 μm composition
(Thickness 0.1 μm), n-InP clad layer 23 (thickness 0.7 μm, carrier concentration n = 1 × 10 ¹⁸ cm ⁻³ )
The layers are laminated using the OCVD method (FIG. 6 (a)).

Next, in the [110] direction, stripes 24 (thickness 0.2 μm, width 1.5 μm) which will serve as a mask in a later step are formed of SiO 2 (FIG. 6 (b)).

By using this SiO2 stripe 24 as a selective mask, RIE using a C2 H6 / H2 system gas was performed.
A mesa structure having a height of 1.5 μm is formed (FIG. 6 (c)).

After that, the above-described susceptor high-speed rotation type M
The p-InP current blocking layer 25 (p = 8 × 10 ¹⁷ cm ⁻³ ) was formed to 0.2 μm and n-InP was formed using an OCVD growth apparatus.
0.5 μ of the current blocking layer 26 (n = 7 × 10 ¹⁸ cm ⁻³ ).
m, p-InP current blocking layer 27 (p = 8 × 10 ¹⁷ cm
^-3 ) is successively grown to 0.8 μm (FIG. 6 (d)).

Further, the SiO2 film 23 formed as the mask is selectively removed by buffered hydrofluoric acid, and an n-InP contact layer 28 (n = 7 × 10 ¹⁸ cm 2) is formed thereon.
^-3 ) is grown by 2 μm (FIG. 6 (e)). Then, in a step not shown, a separation groove is formed and upper and lower electrodes are formed, whereby a semiconductor laser oscillating at a wavelength of 1.3 μm can be manufactured.

Since the semiconductor laser and the optical waveguide integrated device manufactured in this manner do not introduce a chlorine-based gas or raise the growth temperature, they exhibit good characteristics without adversely affecting the device characteristics. Become.

As described above, according to the first embodiment, the mesa structure 6a is formed in the [110] direction by the dry process on the InP wafer 6 having the plane orientation (001), and the wafer 6 is moved at high speed. Since the very thin stagnant layer 7 was formed on the wafer 6 by placing it on the rotatable susceptor 6 and performing the buried growth, the raw material species should reach the wafer 6 without being decomposed. As a result, the decomposition efficiency of PH3 is lowered, the substantial V / III ([PH3] / [TMI]) ratio is reduced, and the III group is stabilized on the (111) B plane, which is the group V stabilization plane.
The surface migration length of the group raw material species becomes long, and (11
1) As a result of suppressing the growth on the B surface, the buried growth layer 11
Forms a (111) B surface 9a extending from the end of the mask 10, and the (111) B surface extends upward while the growth to the (111) B surface is suppressed, and covers the mask 10. The overgrown growth is suppressed, and good selective buried growth can be performed.

The optical waveguide thus formed has neither a chlorine-based gas introduced nor a growth temperature raised, so that it does not adversely affect the device characteristics and a semiconductor laser and an optical waveguide integrated circuit exhibiting excellent characteristics. The device can be provided.

[0026]

As is evident from the foregoing description, according to the compound semiconductor crystal growth how according to the present invention, by dry-etching the semiconductor laminated structure, the mask eaves by the mask
Forming a semiconductor mesa stripe structure without causing
High-speed rotation of a wafer having the semiconductor mesa stripe structure
By performing vapor phase crystal growth while forming the buried growth layers on both sides of the semiconductor mesa structure, the thickness of the stagnant layer of the material gas on the wafer surface becomes thin, and the raw material species are not decomposed. As it reaches the wafer, the wafer on the mask
The growth of the effluent on the (111) B plane is selectively suppressed, and as a result, the crystal growth in the direction of the upper surface of the mask is selectively suppressed, whereby the optical characteristics without adversely affecting the device characteristics. There is an effect that a waveguide integrated device can be realized.

[Brief description of drawings]

FIG. 1 is an external view of a susceptor high-speed rotary MOCVD growth apparatus used in a method for manufacturing a semiconductor device by a compound semiconductor crystal growth method according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of an embedded shape when a dry etch mesa is embedded by using the susceptor high-speed rotation type MOCVD growth device in the above-mentioned Example 1.

FIG. 3 is a diagram showing the relationship between the quality of the embedding shape with respect to the rotation speed of the susceptor and the growth temperature when embedding the dry etch mesa in the first embodiment.

FIG. 4 is a cross-sectional view of a buried shape when a dry-etch mesa is buried by using the lateral MOCVD growth apparatus in the first embodiment.

FIG. 5 is a schematic view of a stagnant layer formed on a growing wafer in the first embodiment.

FIG. 6 is a diagram showing a manufacturing process of an optical waveguide using the compound semiconductor crystal growth method according to the present invention.

[Explanation of symbols]

1 Reactor, 2 Susceptor, 3,4 Nozzle, 5 Flow Rate Control Valve, 6 Wafer, 6a Mesa Etched InP Substrate, 7,8 Stagnation Layer, 9a (111) B Surface,
9b (111) B plane imaginary line, 10 SiO2 mask, 11 embedded growth layer, 12 (111) B plane growth portion, 20 p-InP substrate, 21 p-InP
Clad layer, 22 undoped InGaAsP active layer,
23 n-InP clad layer, 24 SiO2 mask,
25 p-InP first current blocking layer, 26 n-In
P current blocking layer, 27 p-InP second current blocking layer, 28 n-InP contact layer.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-1-179486 (JP, A) JP-A-1-189187 (JP, A) JP-A-3-270126 (JP, A) JP-A-2- 279589 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/205 H01L 21/3065 H01S 5/30

Claims (3)

(57) [Claims] 1. In the compound semiconductor crystal growth method, a wafer having a semiconductor laminated structure to be an active layer is dry-etched using a mask patterned into a predetermined shape to generate a mask eaves by the mask.
And forming a semiconductor mesa stripe without supplies each source gas on the susceptor while rotating the susceptor was placed on the wafer at a high speed higher than a predetermined rotational speed, a thin stagnant layer on the wafer By doing so, a step of forming buried growth layers on both sides of the semiconductor mesa structure while selectively suppressing crystal growth on the (111) B plane of the wafer in the mask is provided. Compound semiconductor crystal growth method. 2. A compound semiconductor crystal growth method according to claim 1 wherein the step of forming a buried growth layer on both sides of the mesa structure is formed
A compound semiconductor crystal growth method, characterized in that the long temperature is performed at a temperature of 580 to 660 ° C. 3. A method for growing a compound semiconductor crystal according to claim 2.
Method, a buried growth layer is formed on both sides of the mesa structure.
The process of rotating the susceptor is 200 to 1000 rpm (time /
Min)), the method for growing a compound semiconductor crystal is characterized in that