JP3530269B2 - Dynamic circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to dynamic circuits.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit device,
In order to suppress the power consumption, a CMOS circuit including a CMOSFET has become mainstream instead of a circuit including an NMOSFET. Generally, a CMOS circuit includes a static circuit and a dynamic circuit (dy
There is a dynamic circuit), and the static circuit and the dynamic circuit are used as needed.

A static circuit is a circuit in which a logic level of a circuit terminal is connected to a fixed potential through a conducting transistor or a resistance element in a steady state and is not left as a floating potential in principle. In the static circuit, 1) the logic level of the circuit terminal is held as long as the driving power is supplied.

2) The signal input can be changed at any timing. And so on. However, since the static circuit needs a circuit for holding the logic level of the circuit terminal, it requires a large number of elements and increases the area of the semiconductor integrated circuit.

On the other hand, a dynamic circuit is a circuit having as its constituent elements circuit terminals that are separated from other fixed potentials for a certain period of time during a circuit operation to be in a floating state. In the dynamic circuit, 1) a highly functional circuit can be realized by using a small number of circuit elements. Therefore, the integration density on the same chip area can be further increased, and at the same time, the cost per function can be reduced.

2) Low power consumption can be achieved by using a ratioless circuit. And so on. However, a precharge operation for setting a floating circuit terminal to a constant voltage is required, and a control signal (clock signal) is required for this. Therefore, it may be called a clock type CMOS circuit. As its dynamic circuit,
For example, there is a full adder 50 shown in FIG.

The full adder 50 adds the input signal A as the addend, the input signal B as the augend, and the carry signal Ci in synchronism with the clock signal φ and bar φ which are input complementary signals. , And outputs the result as a sum signal So and a carry signal Co.

The full adder 50 is a carry signal generation circuit section 5
1, sum signal generation circuit section 52, and output circuit sections 53 and 54
It is composed by. Input signals A and B, a carry signal Ci, and a clock signal bar φ are input to the carry signal generation circuit unit 51. The carry signal generation circuit unit 51
When the clock signal bar φ is at L level, each signal A, B,
A carry is calculated based on Ci, and the result of the calculation is output to the outside as a carry signal Co via the output circuit section 53.

The operation result of the carry signal generation circuit unit 51, the input signals A and B, the carry signal Ci, and the clock signal φ are input to the sum signal generation circuit unit 52. When the clock signal φ is at the H level, the sum signal generation circuit unit 52 adds the signals A, B and Ci based on the signals A, B and Ci and the calculation result of the carry signal generation circuit unit 51. The calculation is performed, and the calculation result is output to the outside as the sum signal So via the output circuit section 54.

The carry signal generation circuit section 51 includes PMOS transistors TP1 to TP6 and an NMOS transistor TN.
1 and 1. The node N1 of the carry signal generation circuit unit 51 is connected to the low potential side power source Vss via the NMOS transistor TN1 which is turned on by the clock signal bar φ at the H level, and becomes the L level. Next, when the clock signal φ becomes L level, the NMOS transistor TN
1 is turned off, and the node N1 is separated from the low-potential-side power supply Vss and enters a floating state. The PMOS transistors TP2 to TP6 are turned on / off based on the input signals A and B and the carry signal Ci. Then, at least two of the signals A, B, and Ci are
If one is at the L level, the node N1 is connected to the PMOS transistor T via the PMOS transistors TP2 to TP6.
Connected to P1. At this time, the PMOS transistor TP
1 is turned on by the clock signal bar φ of L level. Therefore, the PM which has been turned on is supplied to the node N1.
Electric charges are supplied from the high potential side power source V _DD through the OS transistors TP1 to TP6, and the electric charges are accumulated (charged) in the node N1 and become H level.

At least two of the signals A, B, Ci
When one is at H level, the node N1 is not connected to the PMOS transistor TP1. Therefore, the node N1 remains at the L level.

Next, when the clock signal bar φ becomes the H level again, the node N1 inputs the clock signal bar φ to its gate terminal and is turned on to the NMOS transistor T.
It is connected to the low potential power source Vss by N1. At this time, if the electric charge is stored in the node N1 and is at the H level,
The accumulated charges are discharged (discharged) to the low potential side power source Vss.

The sum signal generation circuit section 52 comprises a PMOS transistor TP7 and NMOS transistors TN2 to TN9. Node N2 of the sum signal generation circuit unit 52
Is a PMO that is turned on by an L level clock signal φ.
It is connected to the high-potential-side power supply V _DD via the S transistor TP7, and electric charges are accumulated in the node N2 and become H level.

Next, when the clock signal φ becomes H level, the PMOS transistor TP7 is turned off, and the node N2 is separated from the high potential side power source V _DD and enters a floating state. The NMOS transistors TN3 to TN9 are turned on / off based on the input signals A and B, the carry signal Ci, and the logic level of the node N1. Then, when all the signals A, B, and Ci are at the H level, or when the node N1 is at the H level and the signals A, B, and Ci are at the H level,
When at least one of B and Ci is at H level, the node N2 is connected to the NMOS transistor TN2 via the NMOS transistors TN3 to TN9. At this time, the NMOS transistor TN2 is turned on by the H-level clock signal φ. Therefore, node N
2, NMOS transistors TN2 to T that are turned on
It is connected to the low potential side power source Vss via N9, and the accumulated charges are discharged (discharged) to the low potential side power source Vss to become the L level.

When all the signals A, B, and Ci are at the L level, or when the node N1 is at the L level, the signals A, B, and Ci are
When at least one of B and Ci is at L level, the node N2 is not connected to the NMOS transistor TN2. Therefore, the node N2 remains at H level.

Next, when the clock signal φ becomes L level again, the node N2 is connected to the high potential side power source V _DD by the PMOS transistor TP7 which is turned on by inputting the clock signal φ to its gate terminal. At this time, the node N2
When the charges are discharged to the L level, the charges are supplied from the high potential side power source V _DD , and the charges are accumulated in the node N2 to become the H level.

The output circuit section 53 comprises PMOS transistors TP8 and TP9 and an NMOS transistor TN10 which are connected in series between the high potential side power source V _DD and the low potential side power source Vss. PMOS transistor TP8 and NMO
The gate terminals of the S transistors TN10 are commonly connected and also connected to the node N1. The clock signal bar φ is input to the gate terminal of the PMOS transistor TP9, and PM is generated when the clock signal bar φ is at the L level.
The OS transistor TP9 is turned on, and the PMOS transistor TP9 is turned off when the clock signal bar φ is at the H level. Then, the carry signal Co which is the inversion of the logic level of the node N1 is output from the connection point between the turned-on PMOS transistor TP9 and the NMOS transistor TN10.

On the other hand, when the clock signal φ is at H level, the PMOS transistor TP9 is turned off. Also,
Since the node N1 is at the L level by the NMOS transistor TN2 which is turned on when the clock signal φ is at the H level, the NMOS transistor TN10 is turned off. As a result, the PMOS transistors TP9 and N
The connection point with the MOS transistor TN10 becomes floating, and the carry signal Co is transmitted to both MOS transistors TP.
9, held by the parasitic capacitance at the connection point of TN10.

The output circuit section 54 includes a PMOS transistor TP10 and NMOS transistors TN11, TN1 connected in series between a high potential side power source V _DD and a low potential side power source Vss.
2 and. The gate terminals of the PMOS transistor TP10 and the NMOS transistor TN12 are commonly connected and also connected to the node N2. NMOS
A clock signal φ is supplied to the gate terminal of the transistor TN11.
Is input, and when the clock signal φ is at H level, NM
The OS transistor TN11 is turned on. Then, the sum signal So obtained by inverting the logic level of the node N2 is output from the connection point between the turned-on NMOS transistor TN11 and the PMOS transistor TP10.

On the other hand, when the clock signal φ is at L level, N
The MOS transistor TN11 is turned off. Further, since the node N2 is at the H level by the PMOS transistor TP7 which is turned on when the clock signal φ is at the L level, the PMOS transistor TP10 is turned off. As a result, the PMOS transistor TP10 and NMO
The connection point with the S transistor TN11 becomes floating, and the sum signal So is transmitted to both MOS transistors TP10 and T.
It is held by the parasitic capacitance at the connection point of N11.

That is, when the clock signal φ is at the L level (clock signal bar φ is at the H level), the carry signal generation circuit section 51 discharges the node N1 to the L level, and the sum signal generation circuit section 52 discharges the node N2. Charge to H level. The output circuit units 53 and 54 are connected to the nodes N3 and N4.
Float each. This time is called a standby state.

When the clock signal φ is at the H level (clock signal bar φ is at the L level), the carry signal generation circuit section 51 sets the node N1 to the L level in accordance with the input signals A and B and the carry signal Ci. Set to level or H level. Also, the sum signal generation circuit unit 52 sets the node N2 to the L level or the H level according to the input signals A and B, the carry signal Ci, and the logic level of the node N1. Then, the output circuit section 53
Carries the carry signal C by inverting the logic level of the node N1.
Then, the output circuit unit 54 inverts the logic level of the node N2 and outputs the sum signal So. This time is called an active state.

[0023]

By the way, in a dynamic circuit, a circuit terminal (floating node) which is in a floating state is set to a predetermined potential (high potential side power supply _VDD or low potential side power supply Vss) in a standby state. I need. Therefore, when the potential changes to a potential different from the set potential in the active state, it is necessary to charge or discharge the floating node in order to set the changed potential to a predetermined potential in the next active state. There is. Therefore, when the number of times the floating node changes to a potential different from the set potential in the active state increases, the number of times of charge / discharge increases accordingly.

For example, as shown in FIG. 5, full adder 50
In the standby state (clock signal φ is at L level and clock signal bar φ is at H level), node N1 is set to L level (low potential side power supply Vss) and node N2 is at H level (high potential side power supply V _DD ). Next, the clock signal φ becomes H level (clock signal bar φ becomes L level) and becomes active, and the input signal A becomes H level,
When the input signal B changes to the L level and the carry signal Ci changes to the L level, the node N1 is charged and changes from the L level to the H level.
It changes to the level, the node N2 is discharged and H
Change from level to L level. Then, when the clock signal φ becomes L level (clock signal bar φ becomes H level) and the standby state is resumed, the node N1 is discharged and set to L level, and the node N2 is charged and set to H level. .

[0025] At this time, from the node N1, charges corresponding from the high potential side power supply V _DD to the supply voltage V _DD flows to the low-potential power source Vss, charge supply corresponding to the power supply voltage V _DD is the node N2 And stored. Therefore, in the full adder 50, the charges corresponding to the power supply voltage V _DD move from the high potential side power supply V _DD toward the low potential side power supply Vss. And
Assuming that the capacity of the full adder 50 (capacity of the nodes N1 and N2) is C, electric power proportional to the moving charge amount Q (= C · V _DD ) is consumed. In this case, the low potential power source Vss = 0V.

FIG. 6 shows the power consumption for each logic level of the input signals A and B and the carry signal Ci.
Since power consumption is proportional to the amount of electric charge that moves,
The amount of electric charge that moves as power consumption is shown. Further, as the logic levels of the nodes N1 and N2, the levels changed by the signals A, B and Ci in the active state are shown.

In FIG. 6, a carry signal Co and a sum signal S
If both o are H level (both nodes N1 and N2 are L level), the node N2 is L level when returning to the standby state.
Level is set to H level, but node N1 is set to L
Since it is a level, it does not change. Therefore, the full adder 50
As a result, only the amount of electric charge corresponding to the voltage V _DD flows from the high-potential-side power source V _DD , so the power consumption (moving amount of electric charge) is Q / 2. Similarly, the carry signal Co and the sum signal So are both at the L level (the nodes N1 and N2 are both at the H level).
Level), the node N1 is set from the H level to the L level, but the node N2 remains at the H level and does not change. Therefore, the power consumption (moving charge amount) is Q / 2.

When the carry signal Co is at H level and the sum signal So is at L level (node N1 is at L level and node N2 is at H level), the levels of the nodes N1 and N2 have not changed, so that the standby state is achieved. When entering the state, the electric charge does not move and the power consumption becomes 0.

Therefore, since the input signals A and B and the carry signal Ci have eight logical levels, the full adder 50 averages every time the clock signal φ and the bar φ change and the standby state is entered. The electric charge amount of Q / 2 is the power consumption. Then, when the node N1 changes to the H level and the node N2 changes to the L level based on the input signals A and B and the carry signal Ci, the power consumption becomes proportional to the charge amount Q every time the standby state is entered. Therefore, if the number of times the node N1 is discharged to the L level and the node N2 is charged to the H level increases, there is a problem that the power consumption increases accordingly.

The present invention has been made to solve the above problems, and an object thereof is to provide a dynamic circuit capable of suppressing an increase in power consumption.

[0031]

The invention according to claim 1
Sets multiple nodes to a predetermined voltage and
Signal to the level corresponding to the input signal in synchronization with the signal.
In the dynamic circuit to be added, depending on the input signal
Switch to connect nodes that have been changed to different voltages.
The point is to have a switch.

According to the second aspect of the invention, the clock signal is
Based on the
Set to a specified voltage, and when active, the node
To the voltage according to the input signal, and
In a dynamic circuit that outputs a corresponding output signal,
A control signal is input and based on the control signal and the output signal.
Based on having a switch to connect multiple nodes
Make a summary.

According to a third aspect of the present invention, a clock signal is applied.
Based on the
Set to different voltage, and when active, the node
To the voltage according to the input signal, and
In a dynamic circuit that outputs a corresponding output signal,
Input a control signal, and set the standby state based on the control signal.
The first switch that is turned on for a certain period of time before
Equipped with a second switch that is turned on in response to the output signal
The first switch and the second switch between the nodes.
The point is that H and H are connected in series.

The invention as defined in claim 4 is as set forth in claim 3.
In the dynamic circuit of, the second switch is
At least one of the plurality of nodes is in a standby state
When changed to a voltage different from the voltage that was set
Only turned on, and tried to connect the node
Make a summary.

[0035]

[0036]

Therefore, according to the invention described in claim 1, the input
Nodes that change to different voltages depending on the signal
It is connected by the switch and equalized.

According to the second aspect of the invention , the plurality of nodes are connected and equalized by the switch based on the control signal and the output signal.

According to the third aspect of the invention, the first switch and the second switch are connected in series between the nodes. The first switch is turned on for a certain period of time before the standby state based on the control signal, and the second switch is turned on according to the output signal. And the node is the first
It is connected and equalized by the second switch.

According to the invention described in claim 4 , the second switch is turned on only when at least one of the plurality of nodes is changed to a voltage different from the voltage set in the standby state. , Nodes are connected and equalized.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment embodying the present invention will now be described with reference to FIGS.
It will be described with reference to FIG. In the present embodiment, the same components as those in the conventional example shown in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 1, NMOS transistors 2 and 3 are connected in series between the nodes N1 and N2 of the full adder 1 which are in a floating state. The control signal φo is input to the gate terminal of the NMOS transistor 2. NMOS transistor 2
Turns on when the control signal φo is at H level, and turns off when the control signal φo is at L level.

As shown in FIG. 2, the control signal φo is a pulse signal that is at H level for a certain period of time before the clock signal bar φ falls from H level to L level.
It is generated and supplied by an external device (not shown). Then, when the clock signal bar φ becomes L level, the full adder 1 enters the standby state. Therefore, the NMOS transistor 2 is turned on for a certain period of time before the clock signal bar φ falls from the L level to the H level, that is, before entering the standby state.

The sum signal So is input to the gate terminal of the NMOS transistor 3. The NMOS transistor 3 turns on when the sum signal So is at the H level, and turns off when the sum signal So is at the L level. The sum signal So is output by inverting the logic level of the node N2 by the output circuit unit 54. The sum signal So becomes H level when the node N2 is at L level, and becomes L level when the node N2 is at H level. Therefore, the NMOS transistor 3 is turned on when the sum signal So is at H level (node N2 is at L level).

That is, both NMOS transistors 2 and 3 are
Before the full adder 1 is in the standby state, when the sum signal So is at the H level (node N2 is at the L level), they are connected to each other for a fixed time. At this time, when the node N1 is at the H level (node N2 is at the L level), a current flows from the H level node N1 to the L level node N2 through both NMOS transistors 2 and 3, and both nodes are N
1 and N2 have the same voltage (= V _DD / 2). The operation of connecting the nodes N1 and N2 to each other and setting them to a predetermined voltage (in the case of the present embodiment, a voltage intermediate between the high-potential-side power supply V _DD and the low-potential-side power supply Vss) is called an equalizing operation. The current flowing in this equalizing operation is the node N1 (or N2)
The electric charge is stored in the full adder 1 and is not supplied from outside the full adder 1. Therefore, the current flowing in the equalizing operation does not become the power consumption of the full adder 1.

On the other hand, when the node N1 is at L level,
Since the node N2 is at the L level, both nodes N1 and N2
Remain at the same voltage (= 0V). Next, when the clock signal φ becomes L level (clock signal bar φ becomes H level) and the full adder 1 enters the standby state, both nodes N1, N
2 is precharged. That is, the NMOS transistor TN1 is turned on by the clock signal φ at the H level,
The PMOS transistor TP1 is turned off. Further, the PMOS transistor T is generated by the clock signal φ of L level.
P7 is turned on and the NMOS transistor TN2 is turned off. Then, as shown in FIG. 2, the node N1 is discharged to the L level by the turned-on NMOS transistor TN1. Node N2 is turned on P
It is charged to the H level by the MOS transistor TP7.

Next, the full adder 1 configured as described above.
The action of will be explained. When the full adder 1 is in the standby state, that is,
When the clock signal φ input from the outside is at L level and the clock signal bar φ is at H level, the clock signal φ,
An NMOS transistor TN1 and a PMOS are provided by a bar φ.
The transistor TP7 is turned on. By the both MOS transistors TN1 and TP7 being turned on, the node N
1 is precharged to L level and node N2 is precharged to H level.

Next, when the clock signal φ becomes H level and the clock signal bar φ becomes L level, the full adder 1 becomes active. Then, the clock signal φ and the bar φ cause N
MOS transistor TN1 and PMOS transistor TP
7 is turned off, and the nodes N1 and N2 are in a floating state. The nodes N1 and N2 have logic levels based on the input signals A and B input to the full adder 1 and the carry signal Ci.

As shown in FIG. 3, one of the input signals A and B and the carry signal Ci is at the H level (the other two).
In the case of the L level), the node N1 becomes the H level and the node N2 becomes the L level. The logic levels of the nodes N1 and N2 are inverted by the output circuit units 53 and 54, respectively.
The level sum signal So and the L level carry signal Co are output. The NMOS transistor 3 is turned on because the sum signal So is at H level. Then, the control signal φo
Goes high, the NMOS transistor 2 is turned on, and the nodes N1 and N2 are connected to each other. Then, a current flows from the H-level node N1 to the L-level node N2 via both the NMOS transistors 2 and 3, and the nodes N1 and N2 have the same voltage (= V _DD / 2). N2 is equalized.

Next, when the clock signal φ becomes L level (clock signal bar φ becomes H level) and the full adder 1 enters the standby state, the H level clock signal bar φ causes N.
The MOS transistor TN1 is turned on and the PMOS transistor TP1 is turned off. Further, the PMOS transistor TP7 is turned on by the clock signal φ of the L level, and the NMO
The S transistor TN2 is turned off. Then, as shown in FIG. 2, the node N1 is discharged to the L level by the turned-on NMOS transistor TN1. The node N2 is charged to the H level by the turned-on PMOS transistor TP7.

At this time, the nodes N1 and N2 have the same voltage (V _DD / 2) due to the equalizing operation. Therefore, the node N1 is connected to the high potential side power source V _DD from V _DD /
An electric charge corresponding to 2 is supplied and stored, and then the H level (= V
_DD ). On the other hand, a charge corresponding to V _DD / 2 is stored in the node N2, and the charge is stored in the low potential side power supply Vss.
To the L level (= 0V). Therefore, due to the current flowing from the high potential side power source V _DD to the low potential side power source Vss, the power consumption of the full adder 1 is Q / 2 (= C · V).
_DD / 2). This charge amount is 1/2 that in the conventional case of the same logic level.

Next, the input signals A and B and the carry signal Ci
When any one of them is at L level (the other two are at H level), the node N1 becomes at L level and the node N2 becomes at H level. Since the logic levels of the nodes N1 and N2 are inverted and output by the output circuit sections 53 and 54, respectively, the sum signal So becomes L level and the carry signal Co becomes H level. Then, the NMOS transistor 3 receives the sum signal S
Since o is at the L level, it is turned off. As a result, the nodes N1 and N2 are not connected to each other.

The node N1 is at the L level, which is the same as the logic level discharged by the turned-on NMOS transistor TN1. Further, the node N2 is at the H level, which is the same as the logic level charged by the PMOS transistor TP7 which is turned on. That is, when any one of the input signals A and B and the carry signal Ci is at the L level (the other two are at the H level), the equalizing operation of the nodes N1 and N2 is not necessary, and the movement of the charges does not occur. Absent. Therefore, the power consumption of the full adder 1 is 0 (zero).

FIG. 3 shows the input signals A,
Power consumption for each logic level of B and carry signal Ci is shown. In the figure, nodes N1 and N2
Shows the logic level changed by each signal A, B, Ci on the left side, and the equalized potential on the right side.
The "-" written on the right side shows the case where the nodes N1 and N2 are not equalized.

When all the signals A, B and Ci are at L level,
The nodes N1 and N2 both become H level, and the sum signal So,
Both carry signals Co become L level. Then, since the sum signal So is at the L level, the NMOS transistor 3 is turned off and the equalizing operation is not performed. Then, when the full adder 1 enters the standby state, the NMOS transistor TN1 is turned on by the H-level clock signal φ. Since the node N1 is at H level, it is discharged to L level by the turned-on NMOS transistor TN1. On the other hand, the node N2 is at the H level, which is the same as the logic level charged by the turned-on PMOS transistor TP7. Therefore, the electric charge corresponding to the power supply voltage V _DD flows from the node N1 to the low-potential-side power supply Vss and becomes L level. On the other hand, no charge is supplied to the node N2. As a result, full adder 1
The power consumption of is equal to the amount by which the node N1 is discharged from the H level to the L level, that is, the charge corresponding to the power supply voltage V _DD flows to the low potential side power supply Vss, that is, Q / 2.

When all the signals A, B and Ci are H level, both nodes N1 and N2 are L level. In this case, since the sum signal So is at H level, the NMOS transistor 3 is turned on and the equalizing operation is performed. However, since the nodes N1 and N2 are both at the L level, the charges do not move even if the nodes N1 and N2 are connected to each other. Next, when the full adder 1 enters the standby state, the L-level clock signal φ turns on the PMOS transistor TP7. Then, the node N2 is L
Since it is at the level, it is charged to the H level by the turned-on PMOS transistor TP7. On the other hand, the node N1 is at L level, which is the same as the logic level discharged by the turned-on NMOS transistor TN1. Therefore, the electric charge corresponding to the power supply voltage V _DD is supplied to the node N2 and becomes the H level. as a result,
The power consumption of the full adder 1 is from the L level to the H level at the node N2.
It becomes the amount charged to the level, that is, the amount to which the electric charge corresponding to the power supply voltage V _DD is supplied, and becomes Q / 2.

That is, the input signals A and B and the carry signal C
The power consumption of the full adder 1 in all cases of i is 5Q.
/ 2, and the average power consumption in each logic level state is 5Q / 16. Since this average power consumption is 5/8 of the conventional average power consumption (= Q / 2), the average power consumption can be reduced as compared with the conventional full adder 50. Further, when the node N1 is at the H level and the node N2 is at the L level, the power consumption in the standby state can be reduced to 1/2 of the conventional power consumption. Therefore, the node N1 is discharged to the L level and the node N2 is discharged. Even if the number of times of charging to the H level increases, the increase in power consumption can be suppressed.

As described above, according to this embodiment,
The NMOS transistors 2 and 3 are connected in series between the floating nodes N1 and N2 of the full adder 1. NM
To the gate terminal of the OS transistor 2, a control signal φo that is at H level for a certain period of time before the full adder 1 is in a standby state is input, and when the control signal φo is at H level, N
The MOS transistor 2 is turned on. The sum signal So is input to the gate terminal of the NMOS transistor 3, and the NMOS transistor 3 is turned on when the sum signal So is at the H level. Then, when the NMOS transistors 2 and 3 are turned on, the nodes N1 and N2 are connected to each other, and have an intermediate voltage between the high potential side power source V _DD and the low potential side power source Vss.

As a result, the full adder 1 enters the standby state, the node N1 is discharged from the intermediate voltage to the L level, and the node N2 is charged from the intermediate voltage to the H level. Since the charge amount of 2 moves, power consumption can be suppressed even if the number of times of charging or discharging the nodes N1 and N2 increases.

The present invention is not limited to the above embodiment, but may be carried out as follows. 1) In this embodiment, the NM turned on by the sum signal So
Both nodes N1 and N2 are connected by the OS transistor 3 and the NMOS transistor 2 which is turned on by the control signal φo.
Was precharged, the NMOS transistor 3 is turned on by a signal obtained by inverting the carry signal Co by the inverter circuit to precharge both nodes N1 and N2. According to this configuration, the area increases as the number of inverter circuits increases, but power consumption can be suppressed as in the above-described embodiment.

2) In the above embodiment, the control signal φo,
Node N based on sum signal So and carry signal Co
1 and N2 are connected to each other. For example, NMO
A PMOS transistor is further connected in series to the S transistors 2 and 3, and a carry signal Co is input to the gate terminal of the PMOS transistor. According to this structure, the equalizing operation of both nodes N1 and N2 can be performed only when the node N1 is at the H level and the node N2 is at the L level.

3) In this embodiment, at least one of the NMOS transistors 2 and 3 is changed to a PMOS transistor, and a signal obtained by inverting the control signal φo and the sum signal So is input to the gate terminal of the changed PMOS transistor. To do.

Further, the NMOS transistor 3 is replaced by a PMOS
Instead of a transistor, carry signal Co is applied to its gate terminal.
Enter. With these configurations as well, an increase in power consumption can be suppressed as in the above embodiment.

Further, as switches, in addition to the NMOS transistors 2 and 3, bipolar transistors, MIS type transistors, IGFETs, and FETs including JFETs are also included.
You may carry out using.

4) In the above embodiment, the full adder 1 is embodied, but it may be applied to an arbitrary dynamic circuit such as a half adder. In those cases, the power consumption is similarly reduced. It becomes possible to suppress.

5) In the above embodiment, the PMOS transistor TP1 is omitted and the PMOS transistors TP2 and
This is performed by directly connecting the source terminals of TP4 and TP6 to the high potential side power supply V _DD . In addition, the NMOS transistor TN2
Is omitted, and the NMOS transistors TN5 and TN7 are directly connected to the low-potential-side power source Vss for implementation. Also in this case, the power consumption can be suppressed as in the above embodiment.

6) In the above embodiment, two nodes N
Although 1 and N2 are connected to each other, a plurality of floating nodes may be connected to each other depending on the dynamic circuit.

7) It may be embodied in a semiconductor device (chip) provided with the adder 1 of the above embodiment. Although the respective embodiments of the present invention have been described above, technical ideas other than the claims that can be understood from the respective embodiments will be described below together with their effects.

(A) An adder constituted by the dynamic circuit according to any one of claims 1 to 4 , which connects the nodes based on the control signal and the sum signal. With this configuration, it is possible to suppress an increase in power consumption of the adder.

(B) In the adder of the above (a), the adder further connects the nodes based on the carry signal. According to this configuration, both nodes can be connected only when the voltages of the nodes are different from each other, and it is possible to suppress an increase in power consumption of the adder.

[0070]

As described above in detail, according to the present invention, it is possible to provide a dynamic circuit capable of suppressing power consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a full adder circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the full adder circuit according to the embodiment.

FIG. 3 is an explanatory diagram showing logic levels of a full adder circuit according to an embodiment.

FIG. 4 is a circuit diagram of a conventional full adder circuit.

FIG. 5 is a timing chart showing the operation of a conventional full adder circuit.

FIG. 6 is an explanatory diagram showing logic levels of a conventional full adder circuit.

[Explanation of symbols]

2 NMOS transistor as (first) switch 3 NMOS transistor as (second) switch φ, bar φ clock signal φo control signal So sum signal Co carry signal Input signal as A addend B Input signal as augend Ci carry signal Node as N1, N2 circuit terminal

Claims (4)

(57) [Claims] 1. Setting a plurality of nodes to a predetermined voltage,
A dynamic circuit for changing the node to a level according to an input signal in synchronization with a clock signal, the dynamic circuit including a switch for connecting the nodes changed to different voltages according to the input signal. 2. A plurality of nodes are respectively set to a predetermined voltage in a standby state based on a clock signal,
In the active state, in the dynamic circuit that changes the node to a voltage according to the input signal and outputs an output signal according to the changed voltage, input a control signal, and based on the control signal and the output signal, A dynamic circuit with a switch that connects multiple nodes. 3. The nodes are set to different voltages in the standby state based on the clock signal,
Before inputting a control signal in the dynamic circuit that changes the node to a voltage according to the input signal in the active state and outputs an output signal according to the changed voltage, and before entering the standby state based on the control signal A first switch that is turned on only for a certain period of time and a second switch that is turned on according to the output signal, and the first switch and the second switch are connected in series between the nodes. Dynamic circuit. 4. The dynamic circuit according to claim 3 , wherein the second switch is changed to a voltage different from a voltage set when at least one of the plurality of nodes is in a standby state. A dynamic circuit that only turns on and connects the nodes.