JP3530346B2 - Semiconductor integrated circuit device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a synchronizing circuit technique for generating an internal clock signal synchronized with an external clock signal such as a synchronous DRAM (dynamic random access memory). It is related to effective technology.

[0002]

2. Description of the Related Art As a synchronizing circuit for forming an internal clock signal synchronized with a clock signal supplied from an external terminal, an ISSC DIGIST OF TECHNI
CAL PAPERS) Feb. 10, 1996, pp. 72-73, and I-E-E-Journal of Solid-State Circuits (IEEE JOURNAL OF SOLID-S).
TATE CIRCUITS) Vo29, No.1, January 1994, 67th
There are DLL circuits described on pages 70 to 70, and for the synchronous mirror delay (SMD) circuit,
I S S C C Digest of
Technical Papers (ISSCC DIGIST OF TECHNICAL P
APERS) February 10, 1996, pp. 374-375.

[0003]

In the DLL circuit described in the first document, the phase comparison circuit, NAND (NAND) is used.
It is composed of a delay gate circuit and a shift register circuit in which circuits and the like are connected in cascade, and an internal clock signal generated by delaying the nth external clock signal through the delay gate circuit and an (n + 1) th external clock signal are phased. The comparator is used for comparison, and the delay time is controlled by the shift register circuit. In the second DLL circuit described above, the delay time is controlled by an up / down circuit, and the delay circuit uses a cascade-connected gate circuit similar to that of the first document.

Therefore, in order to reduce the clock-in cycle until the internal clock signal synchronized with the external clock signal is obtained, it is necessary to reduce the number of continuous stages of the delay gate circuit. There is a problem that if the number of clocks is reduced, the clock frequency width becomes narrow under the condition that the delay time is constant, and the delay time increases (deterioration of the phase accuracy of the internal clock) under the condition that the lockable frequency width is constant. Occurs. Since the SMD circuit also uses the above-mentioned delay gate circuit, the circuit scale is increased and the SMD circuit responds to noise and the like, resulting in a problem that the operation is not stable.

An object of the present invention is to provide a semiconductor integrated circuit device provided with a synchronizing circuit which can widen the operating frequency range with a relatively simple circuit scale and which operates stably. Another object of the present invention is to provide a semiconductor integrated circuit device having a synchronizing circuit which can shorten the lock-in cycle and operates stably. Another object of the present invention is to provide a semiconductor integrated circuit device provided with a synchronizing circuit capable of forming an internal clock signal synchronized with the external clock signal and having a frequency doubled. Especially. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, using a variable delay circuit to perform to the signal delay corresponds to a first control signal having binary weights it receives the clock signal supplied from the terminal,
The phase comparator compares the phases of the clock signal supplied from the first terminal with the delay signal of the clock signal passed through the variable delay circuit, supplies the output signal to the delay control circuit, and starts the operation thereof. In the order from the most significant bit of the delay control signal, and if the delay signal is delayed with respect to the clock signal supplied from the first terminal by the output of the phase comparator, reset the bit and proceed. If so, that bit is set to form the delay control signal supplied to the variable delay circuit.

The outline of another typical one of the inventions disclosed in the present application will be briefly described as follows. That is, a variable delay circuit that receives a clock signal supplied from the first terminal and delays it in response to a control signal having a binary weight is used, and the phase comparator is used to perform the first delay. The clock signal supplied from the terminal and the delay signal of the clock signal passed through the variable delay circuit are phase-compared, and the counter circuit is controlled by the comparison output to obtain the clock signal supplied from the first terminal. On the other hand, if the delay signal is delayed, the down counting operation of -1 is performed so as to reduce the delay amount, and if it is advanced, the up counting operation of +1 is performed so as to increase the delay amount.

[0008]

1 is a block diagram of an embodiment of a synchronizing circuit according to the present invention. The synchronizing circuit of this embodiment is mounted on a semiconductor integrated circuit device that forms an internal clock signal synchronized with an external clock signal supplied from an external terminal, such as a synchronous DRAM described later, and is mounted by a known semiconductor integrated circuit technique. It is formed on a single semiconductor substrate such as single crystal silicon.

Clock signal EC supplied from an external terminal
LK is not particularly limited, but is set to 1 by the frequency dividing circuit DV1.
It is divided by 2 and transmitted to the first terminal. This first
The clock signal ECLKT-2R at the terminal of is transmitted to one input of the phase comparator PD and the input of the variable delay circuit VDL1 and is further divided by 1/2 through the frequency dividing circuits DV5 and DV6 to obtain the external clock signal. A clock signal ECLKT-8R obtained by dividing the ECLK by 1/8 is transmitted to the delay control circuit VDLC. The output signal ICLKT-2R of the variable delay circuit VDL is supplied to the other input of the phase comparator PD through constant delay circuit DL1.

The variable delay circuit VDL1 has a delay amount set corresponding to a control signal DCBi having a binary weight, and the control signal DCBi is generated by the delay control circuit VDLC. As described above, the external clock ECLK supplied from the external terminal is divided by the frequency dividing circuit DV.
Clock signal ECLKT-2 divided by 2 by 1
The phase comparator PD compares R with the delay signal ICLKT-2R delayed by the variable delay circuit VDL1. With this configuration, the clock signal ECL obtained by dividing the external clock signal ECLK in one cycle period is used.
Since the KT-2R and the delay signal ICLKT-2R do not change, the change in the delay time due to the change in the pulse width duty of the clock pulse can be reduced.

That is, since the delay circuit delays the signal by the integrating circuit, the same delay circuit is used when delaying a pulse signal having a narrow pulse width and when delaying a pulse signal having a wide pulse width. Even if used, the former delay time will be shortened. A pulse E obtained by dividing the input pulse (ECLK) by 1/2 as in this embodiment.
When CLKT-2R is used, the pulse width changes to a high level and a low level corresponding to one cycle if the cycle is constant even if the pulse width duty of the input pulse (ECLK) changes, and the pulse duty changes. Is 50%.
Therefore, the variable delay circuit VDL1 is not affected by the fluctuation of the pulse width of the input pulse ECLK,
Since the pulse duty generated by the frequency dividing circuit DV1 is 50% and the stable pulse ELCKT-2R is delayed, a stable delay operation can be performed.

In this embodiment, synchronization is performed using the clock signal ECLKT-2R divided by 1/2 as described above, and the necessary internal clock signal ICLK is the clock divided by 1/2. It is not a signal but the same frequency as the clock signal ECLK supplied from the external terminal.
Therefore, the frequency dividing circuit DV2 similar to the frequency dividing circuit DV1 is used.
To DV4, and variable frequency dividing circuits VDL2 to VDL4 similar to the variable delay circuit VDL1 are provided.

The frequency dividing circuit DV1 forms the clock signal ECLKT-2R which changes in response to the rising edge of the external clock signal ECLK. The frequency divider circuit DV2 forms the frequency-divided clock signal ECLKB-2R whose phase is opposite to that of the frequency divider circuit DV1.
The frequency divider circuit DV3 changes the clock signal ECLKT corresponding to the falling edge of the external clock signal ECLK.
Ru der to form a -2F. The frequency dividing circuit DV4 has a frequency-divided clock signal EC that has a phase opposite to that of the frequency dividing circuit DV3.
It forms LKB-2F.

Clock signals ECLKB-2R and ECLKT- formed by the frequency dividing circuits DV2, DV3 and DV4.
2F and ECLKB-2F are variable delay circuits VD
Delayed by L2, VDL3 and VDL4. The variable delay circuits VDL2, VDL3, and VDL4 are supplied with the same delay control signal DCBi as that of the variable delay circuit VDL1, and by the delay control operation described below,
Each of the clock signals ICLKB-2R and ICLKT has the same delay amount as the delayed clock signal ICLKT-2R.
-2F, ICLKTB-2F are formed.

The clock generation circuit CLKG has four clock signals ICLKT-2R and ICLKB- as described above.
Clock signal ECLK supplied from an external terminal by combining 2R, ICLKT-2F, and ICLKTB-2F
To form an internal clock signal ICLK synchronized with and at the same frequency.

The frequency dividing circuits DV5 and DV6 output the output signal ECL by dividing the external clock signal ECLK by eight.
It forms a KT-8R and is used for sequence control of the delay control circuit VDLC. That is, the delay control circuit generates the delay control signal DCBi by the successive approximation method in order to shorten the clock-in cycle. For this control, in the delay control circuit VDLC, the variable delay circuit VD
It is necessary to perform a reset operation for switching the delay amount of L1, a set operation, a phase comparison determination based on the set delay amount, and a series of operations for storing the determination result. By such a series of operations, the delay control signal DCBi having a binary weight is determined bit by bit.

For example, when the delay control signal DCBi consists of 10 bits, the delay time that can be designated by this is 1
There are 024 ways. In this case, the most significant bit is 10
By repeating the procedure of setting the delay time in order from the bit number, invalidating (resetting) the bit if the delay amount is large, and validating (setting) the bit if the delay amount is small, by repeating 10 times, The optimum delay time can be obtained from the above 1024 kinds of delay times.
Assuming that 1 bit is determined by the signal ECLKT-8R divided by 8 as described above, the external clock signal ECLK and the internal clock signal ICLK are 8 × 10 = 80 cycles in terms of the external clock signal ELCK. Can be synchronized.

That is, the delay amount of the variable delay circuit VDL1 is determined by the delay control circuit VDLC, and the delay signal ICLKT-2R corresponding to one cycle before is compared with the input clock signal ECLKT-2R by the phase comparator PD. When the delay amount is insufficient due to the comparison result PHASE, the bit is validated, and when the delay amount is large, the bit is invalidated so that the most significant bit to the least significant bit are sequentially determined. is there.

However, according to the series of phase comparison results, the external clock signal ECLK and the internal clock signal IC
Synchronize with LK, but after that, external clock signal EC
If the phase of LK changes, it cannot follow it. In this embodiment, the delay control circuit VDL is not particularly limited.
The C, up-and-down mosquito-down capacitor circuit is provided. The up / down counter circuit performs up / down counting operation by the output of the phase comparator PD and corrects the delay control signal DCBi. Therefore, the delay control signal DCBi based on the result of the successive comparison is taken into the counter circuit as an initial value, and thereafter the output signal of the counter circuit is supplied to the variable delay circuits VDL1 to VDL4 as the delay control signal DCBi. .

The delay control circuit VDLC has a reset signal DRES corresponding to the successive approximation mode and the counter mode.
ET1 and DRESET2 are generated. Since the variable delay signal BCDi is formed in the successive approximation mode, it is necessary to control only the variable delay circuit VDL1. Therefore, the reset signal DRESET1 for that purpose is generated. In the counter mode, the internal clock signal is actually used. Since the operation is to generate ICLK, the reset signal D
RESET2 is generated to cause the variable delay circuits VDL2 to
After resetting VDL4, the variable delay signal BCDi formed in the successive approximation mode is applied.

The fixed amount delay circuit DL1 is for compensating the signal delay in the clock generating circuit CLKG and the signal delay in the frequency dividing circuit DV1. That is, as described above, the clock signal ECLKT- that has passed through the frequency dividing circuit DV1.
Even if 2R is used and synchronized, it is delayed by the signal propagation delay time in the frequency dividing circuit DV1, and the phase is delayed by the signal propagation delay time. Similarly, since the internal clock signal ICLK is generated from the synchronization signal by the clock generation circuit CLKG, the internal clock signal ICLK is delayed by the signal propagation delay time.

Therefore, the clock signal IC obtained by delaying the delay signal ICLKT-2R by the constant delay circuit DL1.
When the LKD-2R and the ECLKT-2R are synchronized, the delay signal ICLKT- of the variable delay circuit VDL1.
The phase of 2R can be advanced by the delay time of the constant delay circuit DL1. As a result, the fixed amount delay circuit D
When the delay time of L1 is matched with the signal propagation delay time of the frequency dividing circuit DV1 and the clock generating circuit CLKG, an internal clock signal ICLK accurately synchronized with the clock signal ECLK supplied from the external terminal is created. If the delay amount is increased, the external clock E
An internal clock ICLK whose phase is advanced with respect to CLK can also be generated.

FIG. 2 shows a timing chart for explaining an example of the operation of the synchronizing circuit of FIG. When the reset signal RESET is changed from the high level to the low level, the reset is released, the synchronizing circuit is activated, and the successive approximation mode is entered. That is, the clock signals ECLKT-2R, ECLKB-2R, and EC that are frequency-divided by ½ as described above with respect to the external clock signal ECLK.
LKT-2F and ECLKB-2F are generated respectively. A reset signal DRESET1 is generated by the rise of the 1/8 frequency division output ECLKT-8R, the variable delay circuit VLD1 is reset, and each node of the variable delay circuit is initialized. In response to the ECLKT-8R, the delay control circuit VDLC sequentially generates the delay control signal DCBi from the most significant bit in accordance with the successive approximation result PHASE per bit as described above.

In the successive approximation mode, the delay control signal D
When all the bits of CBi are prepared, the counter mode is entered, and the reset of the variable delay circuits VCL2 to VDL4 is released by the change of the reset signal DRESET2 to the low level, and the four delay signals ICLKT-2R, I
CLKB-2R, ICLKT-2F and ICLKB-2
The combination of F generates the internal clock signal ICLK in synchronization with the external clock signal ECLK. For example, it rises in synchronization with the rising edge of the delay signal ICLKT-2R, falls in synchronization with the rising edge of ICLKT-2F, rises again with the rising edge of the delay signal ICLKB-2R, and rises in synchronization with the rising edge of ICLKB-2F. To be In this counter mode, the counter circuit performs an up / down counting operation by the output PHASE of the phase comparator PD, and the delay time is finely adjusted corresponding to 1 bit (1/1024).

FIG. 3 shows a block diagram of an embodiment of the delay control circuit VDLC. Delay control circuit VD
LC is a successive approximation circuit COMP and an up-down counter circuit COUNT, an output signal DCBSi of the successive approximation circuit COMP and an output DC of the counter circuit COUNT.
It is composed of a selector SEL for switching between BCi and a reset signal generating circuit.

The phase comparison output PHASE of the phase comparator PD is supplied to the input terminal PHASE. The input terminal CLK1 is fed to the clock signal E divided by 1/8.
CLKT-8R is supplied. The reset signal RESET is supplied to the input terminal RESET. This reset signal RESET is set to high level at the time of initial setting such as power-on. Alternatively, it is set to a high level when the synchronous DRAM in which the synchronizing circuit is mounted is in an information holding state such as auto refresh, and the operation of the synchronizing circuit is stopped to enter the low power consumption mode. The frequency-divided clock signal ECLKT-2R formed by the frequency dividing circuit DV1 is supplied to the input terminal CLK2.

In the successive approximation circuit COMP, the reset terminal RESET is activated in response to the low level, and the clock signal CLK and the phase comparison output PHA are activated.
Delay control signal DCB in order from the most significant bit by SE
Si is generated. The delay control signal DCBSi formed by the successive approximation circuit COMP is supplied to the counter circuit CO
It is supplied to the initial value input terminal of UNT. Counter circuit C
Also in the OUNT, the reset signal RESET, the phase comparison output PHASE and the clock signal ECKT-8R are supplied similarly to the successive approximation circuit COMP. Reset signal RESET supplied to the counter circuit COUNT
Is the successive approximation completion signal CC of the successive approximation circuit COMP.
Is supplied, and the reset is released when the successive approximation of all bits is completed in the successive approximation circuit COMP.

The selector SEL is the successive approximation circuit CO.
MP output signal DCBSi and the counter circuit COUNT
The output DCBCi of T is switched by the successive approximation completion signal CC. That is, the successive comparison completion signal C
In the successive approximation operation before C is generated, the delay control signal DCBi formed by the successive approximation circuit COMP is supplied to the variable delay circuit VDL1.
When the successive approximation operation is completed and the successive approximation completion signal CC is generated, the delay control signal DCBCi formed by the counter circuit COUNT is output as the variable delay circuit V.
The delay control signal DCBi supplied to DL1 to VDL4 is output.

The reset signal generating circuit forcibly sets the reset signal DRESET1 to the high level when the reset signal RESET of the synchronizing circuit is at the high level. The high level of the reset signal RESET also sets the successive approximation circuit COMP to the reset state, so that the successive approximation completion signal CC also enters the reset state and the reset signal RESET2.
Is also brought to a high level. When the reset signal RESET is at a low level, the reset signal DRESET1 is combined with the clock signals CLK1 and CLK2 and the successive approximation completion signal CC so that the reset signal DRESET1 is one cycle of the 1/8 divided clock signal ECLKT-8R in the successive approximation circuit COMP. It is generated each time a delay control signal of 1 bit is generated, and the reset signal RESET2 is generated at the timing when the successive approximation completion signal CC is generated.

FIG. 4 shows a circuit diagram of an embodiment of the selector SEL. The selector in this embodiment is 1
Bits are exemplarily shown, and the output terminals of two clocked inverter circuits (three-state output circuits) CN1 and CN2 are connected in common to output an output signal DCBi of one bit through the buffer circuit. The successive approximation circuit CO is input to the input of the clocked inverter circuit CN1.
The output signal DCBSi of MP is supplied, and the counter circuit COU is supplied to the input of the clocked inverter circuit CN2.
The output signal DCBCi of NT is supplied. The clocked inverter circuits CN1 and CN2 are supplied with the successive approximation completion signal CC at their clock terminals, and their operations are complementarily controlled.

When the successive approximation completion signal CC is at the low level, the clocked inverter circuit CN1 is activated and the output signal DCBSi of the successive approximation circuit COMP is output. At this time, the clocked inverter circuit CN
2 is put in the output high impedance state. When the successive approximation completion signal CC changes to the high level, the clocked inverter circuit CN1 is set to the output high impedance state, the clocked inverter circuit CN2 is set to the operating state, and the output signal DCBCi of the counter circuit COUNT is set.
Is output. That is, in the successive approximation mode, the delay control signal DCBSi generated by the successive approximation circuit COMP.
Is output as the delay control signal DCBi, and in the counter mode, the delay control signal DCBCi generated by the counter circuit COUNT is output as the delay control signal DCBi.

FIG. 5 shows a circuit diagram of an embodiment of the successive approximation circuit COMP, and FIG. 6 shows an operation waveform diagram thereof. In the same figure, an example of a successive approximation circuit for generating a 4-bit delay control signal is shown for easy understanding of the invention. When the delay control signal of 10 bits is formed as described above, 10 stages of similar circuits may be provided.

Phase comparison output PHASE and clock signal C
LK is alternately input via the multiplexer using the clocked inverter circuit as described above. The reset signal RESET is set to the low level, and the successive approximation operation is started. During the high level period of the clock signal CLK, the most significant bit DCBS [3] is set to the low level to set the delay time which is half the maximum variable delay time of the variable delay circuit VDL1 as described above. Clock signal CL
When K is set to the low level, the multiplexer is switched and the phase comparison output PHASE of the delay signal by the delay time set by the delay control signal DCBS [3] and the clock signal supplied from the external terminal is input. .

If the phase comparison output PAHSE is at the high level at the rising edge of the second clock signal CLK, the most significant bit DCBS [3] is returned to the high level because the delay amount is too large, and Bit DCBS [2] is set to a low level to set a delay time of 1/4 of the maximum variable delay time of the variable delay circuit VDL1. When the clock signal CLK is set to the low level, the multiplexer is switched and the phase comparison output PHASE of the delay signal by the delay time set by the delay control signal DCBS [2] and the clock signal supplied from the external terminal is input. To be done.

At the rising edge of the third clock signal CLK, if the phase comparison output PAHSE is at a low level, it is determined that the delay amount is small and the second bit D
CBS [2] is kept set to the low level and the next bit DCBS [1] is set to the low level. As a result, the delay time of the variable delay circuit VDL1 is set to ¼ + 1/8 of the maximum variable delay time. When the clock signal CLK is set to the low level, the multiplexer is switched and the phase comparison output PHASE of the delay signal by the delay time set by the delay control signal DCBS [1] and the clock signal supplied from the external terminal is input. To be done.

If the phase comparison output PAHSE is at the high level at the rising of the fourth clock signal CLK, the third bit DCBS [1] is set to the high level because the delay amount is large. With the next bit DCBS

[0] is set to low level.
Accordingly, the delay time of the variable delay circuit VDL1 is
The delay time is set to 1/4 + 1/16 of the maximum variable delay time. When the clock signal CLK is set to low level,
The multiplexer is switched so that the delay control signal DCBS

The phase comparison output PHASE of the delay signal by the delay time set in [0] and the clock signal supplied from the external terminal is input.

At the rising edge of the fifth clock signal CLK, if the phase comparison output PAHSE is at a low level, the delay amount is small and the fourth-order bit DCBS is small.

[0] is kept set to the low level and sets the successive approximation completion signal CC to the high level.
As a result, binary information such as 0101 is generated as the delay control signal DCBS by four successive comparison operations. When the successive approximation completion signal CC is generated, the successive approximation mode is switched to the counter mode.

FIG. 7 shows a circuit diagram of an embodiment of the counter circuit COUNT, and FIG. 8 shows an operation waveform diagram thereof. In the figure, an example of a counter circuit for generating a 4-bit delay control signal corresponding to the successive approximation circuit is shown in order to facilitate understanding of the invention. When the delay control signal of 10 bits is formed as described above, 10 stages of similar circuits may be provided.

The counter circuit is composed of a full adder circuit AU and a D-type flip-flop DFF. The input of the flip-flop circuit DFF is
A delay control signal DCB generated by the successive approximation circuit is provided with a multiplexer including a CMOS switch.
S [3] ~

[0] is input. The multiplexer is controlled by a preset signal PRESET generated by the successive approximation completion signal CC, and each of the flip-flop circuits DFF has a delay control signal DCBS [3] ...

[0] is taken as an initial value.

When the fetching of the initial value is completed, the multiplexer supplies the output of the full adder circuit AU to the input of the flip-flop circuit DFF. Then, the phase comparison output P
HASE is taken in by the clock signal CLK, and the full adder circuit AU is caused to perform an operation of +1 or -1, and an up or down counting operation is performed.

As shown in the waveform diagram of FIG. 8, while the preset signal PRESET is at the low level, the delay control signal DCBS [3: 0] formed by the successive approximation circuit, for example, 11
00 is taken into the counter circuit and the counter output DCB
C [3: 0] is set to 1100. When the preset signal PRESET is set to the high level, the phase comparison output P
Up / down counting operation corresponding to HASE is started. For example, if the phase comparison output PHASE is at a low level at the rising timing of the clock signal CLK, -1
Of the delay control signal DCBC [3: 0]
Becomes 1011 and the phase of the delayed signal is advanced. If the phase comparison output PHASE is at the high level at the next rising timing of the clock signal CLK, the counting operation of +1 is performed, the delay control signal DCBC [3: 0] becomes 1100, and the phase of the delay signal is delayed.

Thus, in synchronization with the clock signal CLK, the least significant bit is increased or decreased by one bit in accordance with the phase comparison output PHASE at that time, whereby the clock signal ECL supplied from the external terminal at each time.
By synchronizing K with the internally generated clock signal ICLK, it is possible to form the internal clock signal ICLK that follows the external clock signal ECLK even if the external clock signal ECLK slightly changes.

FIG. 9 shows a circuit diagram of an embodiment of the variable delay circuit. Also in this embodiment, the delay amount is controlled by the 5-bit delay control signal in order to facilitate understanding of the invention. When the delay control signal of 10 bits is formed as described above, ten capacitors having binary weights may be provided in the same manner.

In this embodiment, the delay time is controlled by using the pass transistor (switch MOSFET) and the time constant of the capacitor connected thereby. In other words, the delay control signals DCB0 to DCB4 are used to control the switching of the pass transistor, and the time constant is set by the ON resistance value and the capacitance value of the capacitor connected thereby.

When the minimum unit of the gate width of the pass transistor is W, it is constructed with binary weights such as 2 ^N × W (N = 0, 1, ...). Similarly, when the minimum unit of the capacitor is C, it is configured with a binary weight such as 2 ^N × C (N = 0, 1, ...). When a gate circuit consisting of four stages is used as shown in the figure, the least significant bit DC
B0 is connected to the output of the gate in the second stage, and the next bit DCB1 is in the first and third stages. Next DCB2 to D
The CB4 is provided in all gates. The reset signal RESET sets the output of each gate circuit to the initial state.

FIG. 10 is a characteristic diagram showing the relationship between the delay time of the variable delay circuit and the delay control signal. In the variable delay circuit of this embodiment, the variable delay time is set digitally, but the delay time is formed using the gate circuit as described above, and the minimum delay time and the maximum delay time are It will be appreciated that the variable delay time range between can vary substantially linearly in response to the delay amount control signal.

FIG. 11 is a circuit diagram of an embodiment of the internal clock generating circuit. As shown in the operation waveform diagram of FIG. 2, it rises in synchronization with the rising edge of the delay signal ICLKT-2R, falls in synchronization with the rising edge of ICLKT-2F, rises again with the rising edge of the delay signal ICLKB-2R, and ICLKB- The external clock signal EC is set so as to rise in synchronization with the rise of 2F.
Internal clock signal I having the same cycle (frequency) as LK
When forming the CLK, the input signal ICLK1 corresponding to the ICLKT-2R and the input signal ICLK3 corresponding to the ICLKT-2F are inverted and input to the NAND gate circuit, and the input signal corresponding to the ICLKB-2R. ICLK2 and an inverted signal of the input signal ICLK4 corresponding to ICLKB-2F are input to a NAND gate circuit, and outputs of these two NAND gate circuits are output through a NAND gate circuit that performs an OR output operation.

FIG. 12 shows a circuit diagram of an embodiment of the constant delay circuit. In this embodiment, the external clock signal ECLK as described above is input through an input buffer, and the divided external clock signal ECL is used as a reference.
Used as KT-2R, while internal clock signal ICLK
Then, since the delay signal ICLKT-2R to be compared with the external clock signal ECLKT-2R is further formed through the clock generation circuit CLKG and the output buffer,
In order to compensate for these delay times, an input buffer replica composed of a circuit equivalent to the input buffer, a divide-by-2 circuit replica composed of a circuit equivalent to the divider circuit DV1, and a circuit equivalent to the internal clock generation circuit CLKG. The internal clock generating circuit replica and the output buffer replica including a circuit equivalent to the output buffer are respectively configured as signal transmission circuits, and are connected in cascade to configure the constant delay circuit DL1. By using such a replica circuit, the internal clock signal IC accurately phase-synchronized with the external clock signal ECLK.
LK can be generated.

FIG. 13 shows a DD of a synchronous DRAM.
A waveform diagram for explaining the R specification is shown. In the figure (a), double data rate (DDR) specifications 1
Is a waveform diagram corresponding to, the clock signal CLKDQ is generated in synchronization with the rising and falling of the clock signal CLK, and the output signal DQ is output in synchronization with it.
With this configuration, data output can be performed twice during one cycle of the clock signal, so that high-speed output operation can be realized.

FIG. 6B is a waveform diagram corresponding to the double data rate (DDR) specification 2, which is a specification for outputting at the timing of the rising edge of the clock signal CLK and half the cycle. In other words, according to this specification, the clock signal CLK is not output at the falling edge but is output at the timing of one half of one clock cycle.
Since it is not affected by the pulse width duty of, the timing margin can be increased.

FIG. 14 shows a circuit diagram of an embodiment of the clock pulse generation circuit corresponding to the DDR specification 1. In this embodiment, the input signal ICLK1 corresponding to the ICLKT-2R, the input signal ICLK3 corresponding to the ICLKT-2F, and the ICLKB-2R.
Input signal ICLK2 corresponding to
An input signal ICLK4 corresponding to 2F and an inverted delay signal formed by an inverter circuit that receives the input signal ICLK4 are supplied to a NAND gate circuit, and a clock signal is generated in synchronization with the change timing of the signal. Each signal ICLK1
~ ICLK4 is synchronized with the rising and falling edges of the external clock signal ECLK, and can form the clock signal OCLK of the DDR specifications as described above.

FIG. 15 shows an operation waveform diagram of the synchronization circuit when the clock pulse generation circuit corresponding to the DDR specification 1 is used. That is, a circuit as shown in FIG. 14 is used as the clock pulse generation circuit CLKG of the embodiment circuit of FIG. Similarly to the above, from the variable delay circuits V D L1 to VDL4 generated when the counter mode is set through the successive approximation mode, ICLK
T-2R, ICLKB-2R, ICLKT-2F and I
CLKB-2F is formed, and the internal clock signal ICLK is formed in synchronization with the rising edge of each pulse.

FIG. 16 shows a block diagram of another embodiment of the synchronizing circuit corresponding to the DDR specification 1. In this embodiment, the internal clock signal I of the clock system generated from the rising edge of the external clock signal ECLK
CLKT-2R and ICLKB-2R and the phase comparison operation of ICLKT-2F and ICLKB2-F of the clock system generated from the fall of the external clock signal ECLK can be independently performed.

That is, the phase comparator PD1, the variable delay control circuit VDLC1, the frequency dividing circuits DV51 and DV61, and the constant delay circuit DL11 are assigned to correspond to the clock system generated from the rise of the external clock signal ECLK, and the variable delay is assigned. The circuits VDL1 and VDL2 are controlled, and a phase comparator PD2, a variable delay control circuit VDLC2, frequency dividing circuits DV52 and DV62, and a constant delay circuit DL12 are added corresponding to the clock system generated from the fall of the external clock signal ECLK. The variable delay circuits VDL3 and VDL4 are controlled by them. In this configuration, the delay signals ICLKT-2R and ICLKB-2R synchronized with the rising edge of the external clock signal ECLK are used.
And a delay signal ICLKT-2F synchronized with the falling edge,
Since each of ICLKB-2F and ICLKB-2F is formed by being controlled by the phase comparison output, it is advantageous in terms of clock accuracy.

Although not particularly limited, the clock generation circuit CLKG generates a low-level one-shot pulse in synchronization with the rising edges of the four input clock signals ICLK1 to ICLK4 as in the embodiment of FIG. It is output through a NAND gate circuit.

FIG. 17 shows an operation waveform diagram of the synchronizing circuit of FIG. External clock signal ECL
Corresponding to the clock system generated from the rise of K,
The phase comparator PD1, the variable delay control circuit VDLC1, the frequency dividing circuits DV51 and DV61, and the constant delay circuit DL11 generate the delay control signal DCBRi to generate the variable delay circuit VD.
By controlling L1 and VDL2, ICLKT-2R and ICL
Generate KB-2R. External clock signal ECL
Phase comparator PD2 and variable delay control circuit VDLC provided corresponding to the clock system generated from the fall of K
2. Divider circuits DV52 and DV62 and constant delay circuit DL
A delay control signal DCBFi is generated from 12 to control the variable delay circuits VDL3 and VDL4 to generate ICLKT-2F and ICLKB-2F.

In the clock generation circuit CLKG, ICLKT-2R, ICLKB-2R and ICLKT formed by the variable delay circuits VDL1 to VDL4.
-2F and ICLKB-2F are input signals ICLK1 to IC
This is taken in as LK4, a low-level one-shot pulse is generated in synchronization with its rising edge, and this is sequentially output through a NAND gate circuit.

FIG. 18 shows a block diagram of an embodiment of the synchronizing circuit corresponding to the DDR specification 2. In this embodiment, for the clock system generated from the rising edge of the external clock signal ECLK as described above, the phase comparator PD1 and the variable delay control circuit VDLC are provided as described above.
1. Divider circuits DV51 and DV61 and constant delay circuit DL
A delay control signal DCBRi is generated by 11 to control the variable delay circuits VDL1 and VDL2, and ICLKT-2R
And ICLKB-2R are generated.

Phase comparator PD3 and delay control circuit VDLC
3 and the variable delay circuits VDLa1 and VDLa2 form a delay signal corresponding to a half cycle of the external clock signal ECLK. That is, the phase comparator PD3, the delay control circuit VDLC3, and the variable delay circuit VDLa1 form a synchronization loop, but the variable delay circuit VDLa1
It has a midpoint delay output and generates a signal delayed by a half cycle. The variable delay circuit VDLa2 is also a delay circuit corresponding thereto, and the signals ECLT-2F and ECL delayed by a half cycle are used.
Output KB-2F.

Signals ECLT-2F and E delayed by the above half cycle
CLKB-2F as an input, and the external clock signal E
Phase comparator PD2 and variable delay control circuit VD provided corresponding to a clock system with a timing delayed by a half cycle of CLK
LC2, the frequency dividers DV52 and DV62, and the constant delay circuit DL12 generate a delay control signal DCBFi to control the variable delay circuits VDL3 and VDL4, and ICLKT-2
F and ICLKB-2F are generated.

FIG. 19 shows a circuit diagram of an embodiment of the variable delay circuit VDLa having the above-mentioned midpoint delay output.
In this embodiment, a delay circuit is formed by combining two identical circuits centering on the midpoint output OCLK1.
That is, with respect to the above-mentioned midpoint output, the front-stage circuit and the rear-stage circuit are composed of logic gates and circuits having the same configuration of pass transistors and capacitors provided at the outputs. As a result, a delay signal OCLK delayed by one cycle with respect to the external clock signal ECLK is formed, and a signal with a delay time of half the delay time is extracted from the midpoint output OCLK1 to form a timing signal with a half cycle delay. You can

FIG. 20 shows an operation waveform diagram of the synchronizing circuit corresponding to the DDR specification 2. T1 is ECL
KT-2F and ECLKB-2F generation sequence, T2 is ICLKT-2R, ICLKB-2R, IC
It is a LKT-2F and ICLKB-2F generation sequence. A delay signal ECLKT-2F delayed by a half cycle with respect to the external clock signal ECLKT-2R is generated. Based on this delay signal, the clock system ICLKT-2R and IC
LKB-2R and ICLKT-2F and ICLKB-2F
Generate. Then, the above four clock signals I
CLKT-2R, ICLKB-2R, ICLKT-2F
And ICLKB-2F generate the internal clock signal ICLK corresponding to the DDR specification 2 in synchronization with each rising edge.

FIG. 21 is a block diagram showing another embodiment of the synchronizing circuit according to the present invention. In this embodiment, the frequency dividing circuits DV3 and DV4 and the variable delay circuits DLV3 and DLV4 of the first embodiment are omitted. That is,
In the internal clock generation circuit CLKG, by generating one shot pulse at the rising timing of the delay signal ICLKT-2R and the rising timing of ICLKB-2R, the clock system circuit generated from the falling edge of the external clock signal ECLK can be omitted. The circuit can be simplified and the power consumption can be reduced.

FIG. 22 is a block diagram showing still another embodiment of the synchronizing circuit according to the present invention. In this embodiment, the clock generation circuit CLKG is 1 as described above.
Instead of using the shot pulse generation circuit, an exclusive OR circuit (match / mismatch circuit) is used. In this case, the frequency divider circuit DV3 and the variable delay circuit VD
By using L3, one signal of the rising system of ECLK and one signal of the clock system generated from the falling are combined to simplify the circuit and reduce power consumption, while achieving the same frequency as the external clock signal ECLK. The internal clock signal ICLK can be generated.

FIG. 23 is a circuit diagram of another embodiment of the variable delay circuit used in the synchronizing circuit of the present invention. The variable delay b circuit of this embodiment is used as the variable delay circuits VDL1 to VDL4 of the synchronizing circuit shown in FIG. The difference from the variable delay circuit of FIG. 9 is that the delay time is delayed by two cycles of the external clock signal ECLK. The delay time of 2 cycles is advantageous in speeding up the clock cycle.

FIG. 24 shows an operation waveform diagram when the variable delay b circuit is used. The variable delay b circuit is the same as the above-mentioned operation waveform diagram except that the delay time is delayed by two cycles. For example, for the divided external clock signal ECLKT-2R,
The delay signal ICLKT-2R is the external clock signal ELC.
The signal is delayed by two K cycles.

FIG. 25 is a block diagram for explaining the power down mode of the synchronizing circuit according to the present invention. When a power down signal PWDN is added to set the power down mode such that the input of the external clock signal ECLK is prohibited and the ICLK is not changed as shown in FIG. Clock ECLK and I
CLK is set to a fixed level. As a result, theoretically no current is consumed in the internal circuit, and low power consumption can be achieved. Such a power down mode can be used for a refresh operation or the like in the synchronous DRAM. In the non-synchronous DRAM, a power down command may be provided to generate the signal PWDN.

FIG. 26 shows an overall block diagram of an embodiment of a synchronous DRAM (hereinafter, simply referred to as SDRAM) to which the present invention is applied. Although not particularly limited, the SDRAM shown in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The SDRAM of this embodiment has a memory array 200A forming a memory bank 0 and a memory bank 1A.
Is provided with a memory array 200B. Each of the memory arrays 200A and 200B includes dynamic memory cells arranged in a matrix. According to the drawing, the selection terminals of the memory cells arranged in the same column are coupled to word lines (not shown) for each column, Data input / output terminals of memory cells arranged in the same row are coupled to complementary data lines (not shown) for each row.

One word line (not shown) of the memory array 200A is driven to the selection level according to the decoding result of the row address signal by the row (row) decoder 201A. The complementary data line (not shown) of the memory array 200A is an I / O line 2 including a sense amplifier and a column selection circuit.
Bound to 02A. The sense amplifier in the I / O line 202A including the sense amplifier and the column selection circuit is an amplifier circuit that detects and amplifies a minute potential difference appearing in each complementary data line by reading data from the memory cell. The column switch circuit therein is a switch circuit for individually selecting complementary data lines and bringing them into conduction with the complementary I / O lines. The column switch circuit is selectively operated according to the decoding result of the column address signal by the column decoder 203A.

Similarly, a row decoder 201B, an I / O line 202B including a sense amplifier and a column selection circuit, and a column decoder 203B are also provided on the memory array 200B side. The complementary I / O lines are write buffers 214A, B
Of the main amplifiers 212A and 212B and the input terminals of the main amplifiers 212A and 212B. The output signals of the main amplifiers 212A and 212B are transmitted to the input terminal of the latch / register 213, and the output signal of the latch / register 213 is output from the external terminal via the output buffer 211. In addition, the write signal input from the external terminal is input to the input buffer 210.
Is transmitted to the input terminals of the write buffers 214A and 214B via. The external terminal is not particularly limited, but 1
These are data input / output terminals for outputting 6-bit data D0-D15.

The address signals A0 to A9 supplied from the address input terminals are fetched in the column address buffer 205 and the row address buffer 206 in the address multiplex format. The supplied address signal is held in each buffer. In the refresh operation mode, the row address buffer 206 takes in the refresh address signal output from the refresh counter 208 as a row address signal. The output of the column address buffer 205 is supplied as preset data of the column address counter 207, and the column address counter 207 outputs the column address signal as the preset data, or the column address signal as the preset data according to an operation mode specified by a command or the like described later. A value obtained by sequentially incrementing the column address signal is output to the column decoders 203A and 203B.

Controller 2 shown by a dotted line in FIG.
09 is not particularly limited, but includes clock signal CLK, clock enable signal CKE, chip select signal / C.
S, column address strobe signal / CAS (symbol / means that the signal with this is a row enable signal), row address strobe signal / RAS,
And an external control signal such as a write enable signal / WE and control data from the address input terminals A0 to A9 are supplied, and the operation mode of the SDRAM and the above-mentioned circuit block are controlled based on the level change and timing of these signals. It forms an internal timing signal for controlling the operation, and includes a mode register 10 and a command decoder 2.
0, a timing generation circuit 30, a clock buffer 40, and a synchronous clock generation circuit 50.

The clock signal CLK is input to the synchronous clock generation circuit via the clock buffer 40 and is synchronized with the internal clock as described above.
This internal clock is used as the timing signal int.CLK that activates the output buffer 211, although not particularly limited, and the signal passed through the clock buffer is transmitted to other circuits as it is. If the delay with the external clock becomes a problem, the synchronized clock signal is supplied to the timing generation circuit 30, and the signal is used. The other external input signals are made significant in synchronization with the rising edge of the internal clock signal. The chip select signal / CS instructs the start of a command input cycle by its low level. Chip select signal / CS
When is high level (chip unselected) and other inputs have no meaning. However, a selected state of a memory bank and an internal operation such as a burst operation, which will be described later, are not affected by the change to the chip non-selected state. / RAS, / CA
Each of the S and / WE signals has a different function from the corresponding signal in a normal DRAM, and is a significant signal when defining a command cycle described later.

The clock enable signal CKE is a signal for instructing the validity of the next clock signal.
When E is high level, the next rising edge of the clock signal CLK is valid, and when it is low level, it is invalid. Although not shown, in the read mode,
When the external control signal / OE for controlling the output enable for the output buffer 211 is provided, the signal / OE is also supplied to the controller 209, and when the signal is, for example, high level, the output buffer 211 is in the high output impedance state. To be

The row address signal is the clock signal C.
It is defined by the levels of A0 to A8 in a row address strobe / bank active command cycle described later that is synchronized with the rising edge of LK (internal clock signal).

The address signal A9 is regarded as a bank selection signal in the row address strobe / bank active command cycle. That is, when the input of A9 is low level, the memory bank 0 is selected, and when it is high level, the memory bank 1 is selected. The selection control of the memory bank is not particularly limited, but only the row decoder on the selected memory bank side is activated, all the column switch circuits on the unselected memory bank side are not selected, the input buffer 210 and the output buffer on the selected memory bank side only. This can be performed by processing such as connection to 211.

An address signal A8 in a precharge command cycle, which will be described later, indicates a mode of precharge operation for a complementary data line or the like, and its high level indicates that the precharge targets are both memory banks. The low level indicates that one memory bank designated by the address signal A9 is to be precharged.

The column address signal is defined by the levels A0 to A7 in the read or write command (column address read command, column address write command described later) cycle which is synchronized with the rising edge of the clock signal CLK (internal clock). To be done.
The column address thus defined is used as the start address for burst access.

Next, the SDR designated by the command
The main operation modes of the AM will be described. (1) Mode register set command (Mo) This is a command for setting the mode register 30 and is data specified by / CS, / RAS, / CAS, / WE = low level, and data to be set (register set data). ) Is given via A0-A9. The register set data is not particularly limited,
Burst length, CAS latency, write mode, etc. Although not particularly limited, the burst lengths that can be set are 1, 2, 4, 8 and full page, the CAS latencies that can be set are 1, 2 and 3, and the write modes that can be set are burst write. It is a single light.

The above CAS latency is output buffer 21 from the fall of / CAS in the read operation instructed by the column address read command described later.
This is to instruct how many cycles of the internal clock signal are spent until the output operation of 1. An internal operation time for reading data is required until the read data is determined, and this is for setting it according to the frequency used of the internal clock signal. In other words, the CAS latency is set to a relatively large value when the high frequency internal clock signal is used, and the CAS latency is set to a relatively small value when the low frequency internal clock signal is used. To do.

(2) Row address strobe / bank active command (Ac) This is a command for validating the row address strobe instruction and the memory bank selection by A9.
Instructed by S, / RAS = low level and / CAS, / WE = high level, the addresses supplied to A0 to A8 at this time are fetched as row address signals, and the signal supplied to A9 is fetched as a memory bank selection signal. .
The fetching operation is performed in synchronization with the rising edge of the internal clock signal as described above. For example, when the command is designated, the word line in the memory bank designated by the command is selected, and the memory cells connected to the word line are electrically connected to the corresponding complementary data lines.

(3) Column address read command (Re) This command is a command necessary for starting the burst read operation and a command for giving a column address strobe instruction, / CS, / CAS =
Instructed by low level, / RAS, / WE = high level, and the column address supplied to A0 to A7 at this time is fetched as a column address signal. The column address signal thus fetched is supplied to the column address counter 207 as a burst start address. Before the burst read operation instructed by this, the memory bank and the word line in the memory bank are selected in the row address strobe / bank active command cycle, and the memory cell of the selected word line has the internal clock signal. In synchronism with, the column address counter 207 sequentially selects according to an address signal output from the column address counter 207 and continuously reads. The number of data read continuously is the number specified by the burst length. The data reading from the output buffer 211 is started after waiting for the number of cycles of the internal clock signal defined by the CAS latency.

(4) Column address write command (Wr) When burst write is set in the mode register 10 as a mode of the write operation, it is regarded as a command necessary to start the burst write operation, and the write operation As a mode, when single write is set in the mode register 10, it is a command necessary for starting the single write operation. Further, the command gives an instruction of the column address strobe in single write and burst write. The command is / C
Instructed by S, / CAS, / WE = low level and / RAS = high level, the addresses supplied to A0 to A7 at this time are fetched as column address signals.
The column address signal thus fetched is supplied to the column address counter 207 as a burst start address in burst write. The procedure of the burst write operation instructed by this is performed similarly to the burst read operation. However, for the write operation, CAS
There is no latency, and the acquisition of write data is started from the column address / write command cycle.

(5) Precharge command (Pr) This is a start command of the precharge operation for the memory bank selected by A8 and A9, and / C
Instructed by S, / RAS, / WE = low level and / CAS = high level.

(6) Auto-refresh command This command is a command required to start auto-refresh and is / CS, / RAS, / CA.
Instructed by S = low level and / WE, CKE = high level.

(7) Burst stop in full page command This command is necessary to stop the burst operation for full pages for all memory banks, and is ignored in burst operations other than full page. This command is / CS, / WE = low level, / RAS, / CA
S = Indicated by high level.

(8) No operation command (No
p) This is a command instructing not to perform a substantial operation, and / CS = low level, / RAS, / CAS, / W
Indicated by the high level of E.

In the SDRAM, when a burst operation is being performed in one memory bank, another memory bank is designated and a row address strobe / bank active command is supplied in the middle of the burst operation. It is possible to operate the row address system in the other memory bank without affecting the operation in the other memory bank. For example, the SDRAM has means for internally holding data, an address and a control signal supplied from the outside, and the held contents, particularly the address and the control signal are not particularly limited, but may be held for each memory bank. It has become. Alternatively, the data for one word line in the memory block selected by the row address strobe / bank active command cycle is held in the latch / register 213 for the read operation in advance before the column-related operation. There is.

Therefore, as long as data D0-D15 do not collide at a data input / output terminal consisting of 16 bits, for example, the command being executed is different from the memory bank to be processed while the command whose processing is not completed is being executed. It is possible to start the internal operation in advance by issuing a precharge command and a row address strobe / bank active command for the memory bank.

Since the SDRAM can input / output data, address, and control signal in synchronization with the clock signal CLK (internal clock signal), it is possible to operate a large capacity memory similar to the DRAM at a high speed comparable to that of the SRAM. ,
In addition, by designating how many data are to be accessed for one selected word line by the burst length, the built-in column address counter 207 sequentially switches the selected state of the column system so that a plurality of data can be accessed. It will be appreciated that can be continuously read or written.

In this embodiment, the output buffer is controlled by the internal clock signal int.CLK formed by the synchronizing circuit as described above. As a result, as shown in the operation waveform diagram (b) of FIG. 27, the output signal DO is delayed by the operation delay time tDO in the output buffer from the rise of the internal clock signal int.CLK which is phase-synchronized with the external clock signal ext.CLK. Can be output. In this way, the operation delay time tDO becomes as fast as the time tAC from the clock signal to the data output.

That is, in the conventional circuit not provided with the synchronizing circuit as described above, as shown in FIG. 27A, the delay time td consumed by the clock buffer and the clock driver from the external clock signal ext.CLK is increased. And the operation delay time tDO of the output buffer is added to
Will be lengthened. Therefore, the delay time td cannot be ignored at a high frequency in which one cycle tCK of the clock signal CLK is shortened, which hinders the speedup. Incidentally, if the frequency of the clock signal CLK is set to 250 MHz, one cycle thereof becomes 4 nsec. Therefore, unless the above-described synchronous clock generating circuit is used, the read operation with such clock signal becomes impossible. The synchronized internal clock signal int.CLK is used as a timing signal for latching an address signal such as a row address signal or a column address signal in addition to the timing control of the output buffer as described above. Good.

The synchronizing circuit may form the internal clock signal int.CLK synchronized with the rising and falling edges of the external clock signal or the timing of a half cycle of the rising edge. In this case, it can be applied to the DDR specification 1 and the DDR specification 2, respectively.

The functions and effects obtained from the above-mentioned embodiment are as follows. That is, (1) a variable delay circuit that receives a clock signal supplied from the first terminal and delays it in response to a control signal having a binary weight is used, and Phase comparison between the clock signal supplied from the first terminal and the delay signal of the clock signal passed through the variable delay circuit, and the output signal thereof is supplied to the delay control circuit. The bits are set in order from the most significant bit, and if the delay signal is delayed with respect to the clock signal supplied from the first terminal by the output of the phase comparator, the bit is reset, and if it is advanced, the bit is set. By forming a delay control signal to be supplied to the variable delay circuit by using the internal clock signal, the internal clock signal has a simple structure and is phase-synchronized with the external clock signal in a relatively short time. Effect that can be formed.

(2) Since the clock signal supplied from the external terminal is divided by 1/2 by the frequency dividing circuit to form the clock signal to be supplied to the first terminal, the duty of the external clock signal is not affected. With this, it is possible to obtain an effect that a stable and highly accurate synchronous operation can be performed.

(3) As the delay control circuit, a series of sequence operations for forming the delay control signal per bit by the clock signal obtained by dividing the clock signal supplied from the first terminal by 4 or more. by causing the line, effect that can also form a securely delay control signal only with a simple configuration.

(4) The first frequency divider circuit divides the frequency of the clock signal supplied from the external terminal by 1/2 in synchronization with the rising edge of the clock signal and supplies it to the first terminal.
Form a clock signal having a phase opposite to that of the clock signal at the first terminal, and the third frequency divider circuit sets it to 1 in synchronization with the falling edge of the clock signal supplied from the external terminal. Divided by 2 and supplied to the third terminal,
The frequency divider circuit forms a clock signal having a phase opposite to that of the clock signal at the third terminal and supplies the clock signal to the fourth terminal, and the clock signal supplied from the second to fourth terminals is converted into the binary signal. A second variable delay circuit which is configured to perform signal delay corresponding to a control signal having a weight and which receives the delay control signal formed by the delay control circuit in common with the first variable delay circuit. The external clock signal is delayed by the variable delay circuit No. 4 and combined with the output signals of the first to fourth variable delay circuits to form an internal clock signal synchronized with the clock signal supplied from the external terminal. have the the it is possible to perform the synchronous operation of the same frequency internal clock signal with stable, yet clock signal supplied from a precision external terminal without being affected by the duty Effect can be obtained.

(5) The clock signal supplied from the external terminal is divided by two to form a clock signal having a phase opposite to that of the clock signal supplied to the first terminal and supplied to the second terminal. And a second frequency dividing circuit for receiving a clock signal supplied from the second terminal, delaying the signal corresponding to the control signal having the binary weight, and forming the delay control circuit. A second variable delay circuit that receives the delay control signal in common and is configured of the same circuit as the first variable delay circuit, and a rising edge or a falling edge of the output signals of the first and second variable delay circuits. By further providing an internal clock signal generation circuit that generates a one-shot pulse in synchronization with an edge and forms an internal clock signal synchronized with the clock signal supplied from the external terminal, the circuit is simplified. The effect that the internal clock signal of the same frequency as the clock signal supplied from the external terminal is stable and highly accurate without being affected by the duty of the external clock signal while achieving low power consumption Is obtained.

(6) The clock signal supplied from the external terminal is frequency-divided by 1/2 and a clock signal shifted by a half cycle of the clock signal supplied to the first terminal is formed to form the third terminal. And a clock signal supplied from the third terminal,
A third circuit configured to perform a signal delay corresponding to a control signal having a progressive weight, commonly receive the delay control signal formed by the delay control circuit, and which is configured by the same circuit as the first variable delay circuit. Variable delay circuit and an internal clock signal generation circuit that forms an internal clock signal synchronized with the clock signal supplied from the external terminal by the exclusive OR of the output signals of the first and third variable delay circuits. By further providing the circuit, while simplifying the circuit and reducing the power consumption, the internal clock signal of the same frequency as that of the clock signal supplied from the external terminal that is stable and highly accurate without being affected by the duty of the external clock signal is provided. The effect that the synchronous operation can be performed is obtained.

(7) The clock signal supplied from the external terminal is divided by two to form a clock signal having a phase opposite to that of the clock signal supplied to the first terminal and supplied to the second terminal. A second frequency dividing circuit for dividing the clock signal supplied from the external terminal by ½ and
Of the clock signal supplied from the external terminal to the third frequency divider circuit which forms a clock signal shifted by a half cycle of the clock signal supplied to
A fourth frequency divider circuit that divides the frequency and forms a clock signal having a phase opposite to that of the clock signal supplied to the third terminal and supplies the clock signal to the fourth terminal, and the second frequency dividing circuit supplies the clock signal from the second to fourth terminals. The first variable delay circuit, which receives the respective clock signals, delays the signals corresponding to the control signals having the binary weights, and commonly receives the delay control signals formed by the delay control circuits. Second to fourth variable delay circuits formed of the same circuit as the above, and the first to fourth
The internal clock signal having a double frequency synchronized with the rising and falling edges of the clock signal supplied from the external terminal by generating one shot pulse in synchronization with the rising edge or falling edge of the output signal of the variable delay circuit By further providing the internal clock signal generating circuit for forming the clock signal, it is possible to form an internal clock signal that is synchronized with the external clock signal and that is doubled in frequency.

(8) A variable delay circuit that receives the clock signal supplied from the first terminal and delays the signal in response to a control signal having a binary weight is used, and the phase comparator is used to perform the above-mentioned operation. The clock signal supplied from the first terminal is phase-compared with the delayed signal of the clock signal passed through the variable delay circuit, the counter circuit is controlled by the comparison output, and the counter signal is supplied from the first terminal. If the delay signal is behind the clock signal, perform a -1 down counting operation to reduce the delay amount, and if it is advancing, perform a +1 up counting operation to increase the delay amount. Thus, it is possible to form an internal clock signal that is phase-synchronized with the external clock signal with a simple configuration.

(9) By dividing the clock signal supplied from the external terminal by 1/2 to form the clock signal supplied to the first terminal, the clock signal is stable without being affected by the duty of the external clock signal. An effect that a highly accurate synchronous operation can be performed is obtained.

(10) As the delay control circuit, the delay control signal is sequentially generated from the most significant bit by the successive approximation operation, the delay control signal generated thereby is preset in the counter circuit, and the delay control signal is output by the phase comparator. performed on SL-down counting operation of -1 so as to reduce the delay amount if the delay signal is delayed relative to the clock signal supplied from the first terminal, willing to increase the amount of delay you are +1 By providing a counter circuit for performing the up-counting operation of 1., an internal clock signal having a simple configuration, which is phase-synchronized with the external clock signal in a relatively short time, and which is made to follow the frequency deviation of the external clock signal is also formed. The effect that can be obtained is obtained.

(11) The delay control circuit includes the first
The clock signal supplied from the terminal of 4 can perform a series of sequence operations for forming the above-mentioned delay control signal per bit by a clock signal obtained by dividing the clock signal by 4 or more. It is possible to obtain an effect that the delay control signal can be reliably formed with a small number of signals, and the internal clock signal that can follow the fluctuation of the frequency of the external clock signal can be formed.

(12) One shot pulse is generated in synchronization with the rising edge or the falling edge of the output signals of the first to fourth variable delay circuits to rise and rise the clock signal supplied from the external terminal. 17. The semiconductor integrated circuit device according to claim 16, further comprising an internal clock signal generation circuit which forms an internal clock signal having a doubled frequency in synchronization with the falling.

(13) By mounting the above-mentioned synchronizing circuit in the synchronous dynamic RAM, it is possible to obtain the effect that high speed operation can be achieved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the variable delay circuit may be any one as long as the variable delay time is controlled with a binary weight. The successive approximation circuit
It may be configured by a combination of a timing generation circuit and a storage circuit. That is, the clock signal may be formed by the counter circuit, the storage circuits may be sequentially selected by the decode signal, and the delay control signal as described above may be stored in the storage circuit.

The clock signal supplied from the external terminal is
As described above, the frequency may be directly supplied to the phase comparator and the variable delay circuit without being divided by 1/2. That is,
This is because, if the pulse duty of the external clock signal does not change, it is less meaningful to provide the 1/2 frequency dividing circuit as described above. The delay control signal may be fixedly set by the output of the successive approximation circuit as described above. For example, in a synchronous DRAM, synchronization may be performed each time the power is turned on or other initial settings are made.

If the lock-in cycle may be long, the delay control signal may be formed by a counter circuit. In this case, in order to shorten the lock-in cycle as much as possible, set the most significant bit of the initial value of the counter and set it to half the maximum value of the variable delay time. A signal can be formed.

The present invention can be applied to various semiconductor integrated circuit devices having a synchronizing circuit for generating an internal clock signal synchronized with a clock signal supplied from an external terminal.
For example, in addition to the synchronous DRAM described above, a synchronous SRAM (static RAM), a dynamic RAM of a Rambus specification, or a microcomputer system is used to input / output data in synchronization with a system clock. It can be widely used for various peripheral devices.

[0112]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a variable delay circuit that receives a clock signal supplied from the first terminal and delays the signal in response to a control signal having a binary weight is used, and a phase comparator is used to output the signal from the first terminal. Phase comparison between the clock signal supplied and the delay signal of the clock signal passed through the variable delay circuit, the output signal is supplied to the delay control circuit, from the most significant bit of the delay control signal at the start of operation. Set in order and reset the bit if the delay signal is delayed with respect to the clock signal supplied from the first terminal by the output of the phase comparator,
If it is progressing, by setting that bit and forming the delay control signal to be supplied to the variable delay circuit, it is possible to form an internal clock signal that is phase-synchronized with the external clock signal in a relatively short time with a simple configuration. You can

To briefly explain the effects obtained by the other typical inventions among the inventions disclosed in this application,
It is as follows. That is, a variable delay circuit that receives a clock signal supplied from the first terminal and delays it in response to a control signal having a binary weight is used, and the phase comparator is used to perform the first delay. The clock signal supplied from the terminal and the delay signal of the clock signal passed through the variable delay circuit are phase-compared, and the counter circuit is controlled by the comparison output to obtain the clock signal supplied from the first terminal. On the other hand, if the delay signal is delayed, the down counting operation of -1 is performed so as to reduce the delay amount, and if the delay signal is advanced, the up counting operation of +1 is performed so as to increase the delay amount. With such a configuration, it is possible to form the internal clock signal that is phase-locked with the external clock signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronizing circuit according to the present invention.

FIG. 2 is a timing chart for explaining an example of the operation of the synchronization circuit of FIG.

3 is a block diagram showing an embodiment of the delay control circuit VDLC of FIG.

FIG. 4 is a circuit diagram showing an embodiment of the selector SEL of FIG.

5 is a circuit diagram showing an embodiment of the successive approximation circuit COMP of FIG.

6 is an operation waveform diagram of the successive approximation circuit of FIG.

7 is a circuit diagram showing an embodiment of the counter circuit COUNT of FIG.

8 is an operation waveform diagram of the counter circuit of FIG.

FIG. 9 is a circuit diagram showing an embodiment of the variable delay circuit of FIG.

10 is a characteristic diagram showing the relationship between the delay time and the delay control signal of the variable delay circuit of FIG.

11 is a circuit diagram showing an embodiment of the internal clock generation circuit CLKG of FIG.

12 is a circuit diagram showing an embodiment of the constant delay circuit DL1 of FIG.

FIG. 13 is a waveform chart for explaining DDR specifications of a synchronous DRAM.

14 is a circuit diagram showing an embodiment of a clock pulse generation circuit corresponding to the DDR specification 1 of FIG.

15 is an operation waveform diagram of the synchronization circuit when the clock pulse generation circuit corresponding to the DDR specification 1 of FIG. 13 is used.

16 is a block diagram showing another embodiment of the synchronizing circuit corresponding to the DDR specification 1 of FIG.

17 is an operation waveform diagram of the synchronization circuit of FIG.

FIG. 18 is a block diagram showing an embodiment of a synchronization circuit corresponding to the DDR specification 2 of FIG.

19 is a variable delay circuit V having the midpoint delay output of FIG.
It is a circuit diagram which shows one Example of DLa.

20 is an operation waveform diagram of the synchronization circuit corresponding to the DDR specification 2 of FIG.

FIG. 21 is a block diagram showing another embodiment of the synchronizing circuit according to the present invention.

FIG. 22 is a block diagram showing still another embodiment of the synchronizing circuit according to the present invention.

FIG. 23 is a circuit diagram showing another embodiment of the variable delay circuit used in the synchronizing circuit of the present invention.

24 is an operation waveform diagram when the variable delay b circuit of FIG. 23 is used.

FIG. 25 is a configuration diagram for explaining a power down mode of the synchronization circuit according to the present invention.

FIG. 26 is a synchronous DRAM to which the present invention is applied.
It is a whole block diagram which shows one Example.

27 is a waveform diagram for explaining an outline of the operation of the synchronous DRAM of FIG.

[Explanation of symbols]

PD, PD1 to PD3 ... Phase comparator, DV1 to DV62
... Frequency divider circuit, VDLC, VDLC1 to VDLC3 ... Delay control circuit, VDL1 to VDL4, VDLa1, VDLa
2 ... Variable delay circuit, DL1, DL11, DL12 ... Constant delay circuit, CLKG ... Clock generation circuit, SEL ... Selector, COMP ... Successive comparison circuit, COUNT ... Counter circuit, AU ... Full addition circuit, DFF ... D flip-flop circuit 10 ... Mode register, 20 ... Command decoder, 30 ... Timing generating circuit, 30 ... Clock buffer, 50 ... Synchronous clock generating circuit, 200A, 200B
... memory array, 201A, 201B ... row decoder,
202A, 202B ... Sense amplifier and column selection circuit, 203A, 203B ... Column decoder, 205 ... Column address buffer, 206 ... Row address buffer, 207 ... Column address counter, 208 ... Refresh counter, 209 ... Controller, 210 ... Input buffer, 211 ... Output buffer, 212A, B ... Main amplifier, 213 ... Latch / register, 214A, B ...
Write buffer.

Continuation of the front page (56) References JP-A-8-97715 (JP, A) Avner Efendovich et al. , Multifrequency zero-Jitter Delay-Locked Loop, IE EE JOURNAL OF SOLI D-STATE CIRCUITS, USA, January 1994, Vol. 29, No. 1, p. 67-70 (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 1/10

Claims (6)

(57) [Claims] 1. A first variable delay circuit for receiving a clock signal supplied from a first terminal and performing a signal delay corresponding to a control signal having a binary weight, and the first variable delay circuit. A delay control circuit for supplying a delay control signal having a binary weight to the clock signal, a clock signal supplied from the first terminal, and a delay signal of the clock signal passed through the first variable delay circuit. And a phase comparator for transmitting the comparison result to the delay control circuit, and the delay control circuit sets the delay control signal in order from the most significant bit at the start of operation. If the delay signal is delayed with respect to the clock signal supplied from the first terminal by the output of the controller, the bit is reset, and if it is advanced, the bit is set to form the delay control signal. A semiconductor integrated circuit device characterized by the following. 2. A first frequency dividing circuit for dividing a clock signal supplied from an external terminal by ½ to form a clock signal supplied to the first terminal. The semiconductor integrated circuit device according to claim 1. 3. The delay control circuit performs a series of sequence operations for forming the delay control signal per bit by a clock signal obtained by dividing the clock signal supplied from the first terminal by four or more. The series of sequence operations are performed by comparing the operation of resetting the first variable delay circuit with a reset signal generated in synchronization with the clock signal supplied from the first terminal and the phase comparison. 3. The semiconductor integrated circuit device according to claim 1, further comprising a variable delay amount setting operation for 4. The first frequency divider circuit sets the clock signal to 1 in synchronization with the rising edge of a clock signal supplied from an external terminal.
A second frequency dividing circuit which divides the frequency by 2 and supplies it to the first terminal, forms a clock signal having a phase opposite to that of the clock signal of the first terminal and supplies the clock signal to the second terminal. , A third frequency divider circuit which divides the frequency of the clock signal supplied from the external terminal by ½ in synchronization with the falling edge of the clock signal and supplies the clock signal to the third terminal, A fourth frequency divider circuit which forms a phase clock signal and supplies it to the fourth terminal, and a control which receives the clock signals supplied from the second to fourth terminals and has the binary weight. Second to fourth variable delay circuits configured to perform the signal delay corresponding to the signal and commonly receive the delay control signal formed by the delay control circuit, and configured by the same circuit as the first variable delay circuit. And output signals of the first to fourth variable delay circuits An internal clock signal generating circuit that forms an internal clock signal in synchronization with the clock signal supplied from the external terminal, and outputs the output signals of the first variable delay circuit to a first frequency dividing circuit and the internal clock signal generating circuit. 4. The semiconductor integrated circuit device according to claim 2, further comprising a constant delay circuit which delays the signal corresponding to a signal delay in the circuit and transmits the signal to the phase comparator. 5. A first variable delay circuit for receiving a clock signal supplied from a first terminal and performing a signal delay corresponding to a control signal having a binary weight, and the first variable delay circuit. A delay control circuit for supplying a delay amount control signal having a binary weight to the clock signal, a clock signal supplied from the first terminal, and a delay of the clock signal through the first variable delay circuit. A phase comparator for performing a phase comparison with a signal and transmitting the comparison result to the delay control circuit, wherein the delay control circuit sets the most significant bit of the delay amount control signal in sequence from the most significant bit at the start of operation. If the delay signal is delayed from the clock signal supplied from the first terminal by the output of the phase comparator, the bit is reset, and if it is advanced, the bit is set to set the delay control signal. The first counting circuit and the output of the phase comparator cause the delay amount to be reduced if the delay signal is delayed with respect to the clock signal supplied from the first terminal. And a delay control signal formed by the first circuit and a second circuit including a counter circuit that performs an up-counting operation of +1 so as to increase the delay amount if A multiplexer for supplying the delay control signal formed by the second circuit to the first variable delay circuit after all bits have been determined by the first circuit supplied to the circuit. Semiconductor integrated circuit device. 6. A first frequency dividing circuit that divides a clock signal supplied from an external terminal by ½ to form a clock signal supplied to a first terminal, and a clock signal supplied from the external terminal. A second frequency divider circuit that forms a clock signal having a phase opposite to that of the clock signal that is divided by ½ and that is supplied to the first terminal, and that is supplied to the second terminal, supplied from the first terminal Received a clock signal
A first variable delay circuit for delaying a signal corresponding to a control signal having a progressive weight, and a clock signal supplied from the second terminal
A second variable delay circuit for delaying a signal corresponding to a control signal having a binary weight; and a first delay control signal having a binary weight for the first and second variable delay circuits. A first delay control circuit for supplying a phase difference between the clock signal supplied from the first terminal and the delay signal of the clock signal passed through the first variable delay circuit, and the comparison result To the first delay control circuit, and a first phase comparator which receives the clock signal supplied from the first terminal and is configured by the same circuit as the first variable delay circuit. A fifth variable delay circuit having an output terminal and a second output terminal forming a delayed output of half the output terminal, and a clock signal supplied from the second terminal, and receiving a clock signal from the first variable delay circuit. A sixth with an output terminal forming a half delayed output A variable delay circuit, a second delay control circuit that supplies a second delay control signal having a binary weight to the fifth and sixth variable delay circuits, and a second delay control circuit that is supplied from the second terminal. And a second phase comparator for transmitting the comparison result to the second delay control circuit, and comparing the phase of the clock signal with the delay signal of the clock signal passed through the fifth variable delay circuit, and transmitting the comparison result to the second delay control circuit. A third variable delay circuit for receiving an output signal of the fifth variable delay circuit and performing signal delay corresponding to a control signal having a binary weight; and an output signal of the sixth variable delay circuit, A fourth variable delay circuit for performing signal delay corresponding to a control signal having a binary weight, and a third delay control having a binary weight for the third and fourth variable delay circuits. A third delay control circuit for supplying a signal, and the fifth variable delay circuit A third phase comparator for performing phase comparison between the output signal and the delayed signal of the clock signal passed through the third variable delay circuit, and transmitting the comparison result to the third delay control circuit; Each of the first, second, and third delay control circuits is set from the most significant bit of the delay amount control signal at the start of operation, and is supplied from the first terminal by the output of the phase comparator. If the delayed signal is delayed with respect to the clock signal, the bit is reset, and if it is advanced, the first circuit that sets the bit to form the delay control signal and the output of the phase comparator If the delay signal is delayed with respect to the clock signal supplied from the first terminal, a down counting operation of -1 is performed so as to reduce the delay amount, and if it is advanced, the delay amount is increased. A second circuit including a counter circuit for performing a +1 up-counting operation, and first to sixth variable delay circuits respectively corresponding to the first to third delay control signals formed by the first circuit. To all the bits are determined by the first circuit, and then the first to the third delay control signals formed by the second circuit are respectively supplied to the corresponding first to sixth delay control signals.
1. A semiconductor integrated circuit device comprising: a first to a third multiplexer for supplying to the variable delay circuit of FIG.