JP3530371B2 - Image processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus including a storage unit for storing an image signal, and particularly, in an image pickup apparatus such as a digital still camera, an image signal used for image compression processing represented by JPEG. The present invention relates to an image processing device including a memory for storing.

[0002]

2. Description of the Related Art The JPEG standard is Joint Photographic E
One of the international standards created by xperts Group,
Specifies compression and decompression algorithms for color still images.

In the field of a digital still camera that converts an optical image of a subject into a digital color still image through a CCD mounted inside and processes it, an image processing LSI conforming to the above international standard, that is, an image processing apparatus. Is being developed.

Here, the configuration of an image processing apparatus in a conventional digital still camera will be described with reference to FIG.

FIG. 8 is a schematic block diagram showing a configuration of a main part of an image processing apparatus 200 in a conventional digital still camera.

In FIG. 8, the image processing apparatus 200 has a C
CD circuit 10, A / D conversion circuit 20, image compression circuit 3
0, a video encoder 35, a memory 40, a timing generation circuit 50, and a CPU 150.

The timing generation circuit 50 controls the operation of a CCD circuit 10 and an A / D conversion circuit 20, which will be described later, on the basis of a clock signal internally generated.
It outputs LK, horizontal sync signal HS, and vertical sync signal VS.

The CCD circuit 10 is a solid-state image pickup device which converts an incident optical image of a subject into a one-dimensional electric signal, and is composed of a plurality of two-dimensionally arranged photoelectric conversion elements (photodiodes, etc.). Composed. The photoelectric conversion element accumulates electric charges according to the amount of incident light and outputs the accumulation result in the form of an electric signal. One photoelectric conversion element forms one pixel of a captured image.

The configuration of the pixels included in the CCD circuit 10 will be briefly described with reference to FIG.

FIG. 9 is a schematic diagram showing an array of pixels included in the CCD circuit 10. In FIG. 9, I represents a pixel position in the horizontal direction and J represents a pixel position in the vertical direction (hereinafter, this pixel array is referred to as a pixel array 11). The pixel array 11 is composed of a plurality of pixels arranged in the horizontal direction and the vertical direction. Symbol G (I, J) in the figure
Represents the pixel at position (I, J). When the number of pixels in the horizontal line direction of the pixel array 11 is 640 and the number of pixels in the vertical line direction is 480, I is 0 to 639 and J is 0 to 479.
Take a natural number of. In the following description, the number of pixels in the horizontal direction is 640 and the number of pixels in the vertical direction is 480 unless otherwise specified.

The CCD circuit 10 responds to the pixel clock CLK, the horizontal synchronizing signal HS, and the vertical synchronizing signal VS output from the timing generating circuit 50 after accumulating electric charges according to the amount of incident light from the subject in each photoelectric conversion element. Then, the electrical signal S (I, J) corresponding to each pixel G (I, J) is output in the raster scan order.

More specifically, the CCD circuit 10
Is a horizontal pixel position 0 (I
= 0), one pixel at a time in the horizontal line direction (I is fixed for J
(Increment by 1) to output the corresponding electric signal S (I, J). Further, the CCD circuit 10 increases the horizontal line to be output by 1 (increases J by 1) in synchronization with the horizontal synchronization signal HS, and responds to the horizontal pixel direction from the horizontal pixel position 0 (I = 0) one pixel at a time. The electric signal S (I, J) is output.
Further, in synchronization with the vertical synchronization signal VS, the head position (I =
The output starts from 0, J = 0).

The A / D conversion circuit 20 converts each of the electric signals S (I, J) received from the CCD circuit 10 into image signals D (I, J) which are digital signals. Each of the image signals D (I, J) is transferred to the data bus DB in raster scan order. The pixel G (I, J) and the image signal D (I, J) have a one-to-one correspondence.

The CPU 150 outputs an address to the address bus AB. A memory cell (not shown) included in the memory 40 described later is brought into a selected state in response to an address supplied from the CPU 150. In the write operation, data is written in the selected memory cell. In the read operation, data is read from the selected memory cell. The image signal D (I, J) output from the A / D conversion circuit 20 to the data bus DB is stored in the corresponding memory cell in response to the address supplied from the CPU 150.

The image compression circuit 30 reads out the image signal D (I, J) stored in the memory 40 and then performs compression processing. Each of the image signals D (I, J) in the memory 40 is replaced with the result of compression processing. The video encoder 35 reads the compressed image signal D (I, J) from the memory 40 and performs a decompression process.

The unit of compression processing and the pixel array 11
The relationship with and will be briefly described with reference to FIG.

FIG. 10 shows a unit of compression processing and the pixel array 1.
2 is a schematic diagram showing an example of the relationship with 1. As shown in FIG. 10, the compression process is performed for each corresponding image signal D (I, J) with a total of 64 pixels consisting of 8 pixels in the horizontal direction and 8 pixels in the vertical direction as one unit. Hereinafter, this one unit and a collection of the corresponding image signals D (I, J) are referred to as compression blocks, respectively, and as shown in FIG. 10, compression blocks 0, 1,
It is called ...

In such an image processing apparatus, a dynamic random access memory (hereinafter referred to as DRAM for simplicity) is usually adopted as the memory 40. A DRAM (not shown) has a plurality of memory cells arranged in a two-dimensional matrix, and each memory cell is connected by word lines in the row direction and by bit lines in the column direction.

Now, the relationship between the image signal D (I, J) and the position (address) designated by the CPU 150 when the memory 40 is a DRAM will be described.
Note that in the following, for simplification, a continuous address space using the positions of memory cells continuous in the row direction as an index will be described.

The CPU 150 sets the memory cell corresponding to the image signal D (I, J) to the selected state by the following equation (1).
The address indicated by is output.

MADR (I, J) = I + 640 × J (1) where MADR (I, J) is the image signal D (I, J)
Of the image signal D (0,0). As shown in Expression (1), the CPU 150 assigns an address in the order of raster scan (hereinafter, this address is referred to as a raster scan address). In a writing operation, the image signal D (I, J) is expressed by Expression (1). ) Is stored in the memory cell corresponding to. Further, in the read operation, when the address corresponding to the equation (1) is designated, the corresponding image signal D (I, J) is read.

When a DRAM is used as the memory 40, high speed page mode access can be used for data transfer due to the structure of the DRAM. The high-speed page mode access is a function that enables high-speed access to the memory cells located in the same row of the DRAM. By using this function, the data of a plurality of memory cells can be read at high speed. Specifically, when the fast page mode access is used in the read operation, one row address is designated and the column address is sequentially changed.

In high-speed page mode access, a group of memory cells that are selected by designating one row address is called a page, and the number of the memory cells is called a page size. In order to effectively realize this high-speed page mode access, it is necessary that all the data to be read are in the same page.

[0024]

However, when the memory cell is selected based on the raster scan address as described above, the following problems occur.

FIG. 11 is a diagram showing the relationship between the storage position and the page when the image signal D (I, J) is stored in the DRAM according to the raster scan address. Where DR
The page size of AM is 256. Further image signal D
It is assumed that (0, 0) is stored at the position of the start address of page 0 (address A).

In this case, the page where the image signal D (I, J) is located is obtained by the following equation (2) using equation (1). In the following formula, int (x /
y) is the integer part of the value obtained by dividing x by y, and mod (x /
y) indicates the value of the remainder when x is divided by y.

Page number = int [(I + 640 × J) / 256] (2) According to the equation (2), for example, for page 0 where the image signal D (0,0) belonging to the compressed block 0 exists. , The image signal D (0,1) is stored in page 2.

That is, 64 constituting compressed block 0
The individual image signals D (0,0) to D (7,7) are distributed and stored in a plurality of pages. Therefore, when performing compression processing, pages are switched and the corresponding image signal D
It becomes necessary to read (I, J). This is the probability of accessing the same page (hereinafter called the page hit rate)
Is extremely low. This means that page switching occurs even when the video encoder 35 performs the decompression processing for each compressed block.

As one of means for solving this problem, when the image signal D (I, J) is stored in the memory 40, it is conceivable to perform a memory mapping process suitable for the compression process. In this case, when the CPU 150 is operated with the raster scan address that is the easiest to process, if the address is sequentially changed by software, the specific image signal D (I, J) stored in the memory 40 is processed and the specific image signal D (I, J) is processed. The image signal D (I, J) can be read and transferred to the internal circuit. However, this method has a problem that the transfer speed is reduced.

Therefore, the present invention has been made in order to solve the above problems, and performs compression processing using a stored image signal, and also performs processing and transfer processing on a stored specific image signal. In the image processing device to perform,
An object of the present invention is to provide an image processing device having a high page hit rate and capable of performing image processing at high speed.

[0031]

According to the present invention, an image
The processing device is an image processing device of an imaging device that converts incident light from a subject into a digital image signal, and is a horizontal direction.
And arranged vertically, and in multiple blocks.
Corresponding to the incident light incident on the multiple pixels
Digital image signal that is a block unit of multiple blocks
In the horizontal line direction, and multiple
Each lock has a block that follows the raster scan order.
Storage means for storing based on lock scan address
Corresponding to the digital image signal stored in the storage means
Outputs the raster scan address and outputs the digital image signal.
Control means for instructing reading, and output from the control means
Receives the raster scan address and receives the raster scan address.
To the corresponding block scan address and convert
The generated block scan address to the storage means
Address conversion means, and the storage means converts the address
The block scan address received from the
Output digital image signal.

Preferably, the image processing device is a storage means.
Read out digital image signal for each specified compression block
To perform compression processing and transfer the compression result to the storage means.
Compression means and a storage device that is compressed by the compression means.
Encoding for recovering digital image signals stored in columns
Means for each of the predetermined compressed blocks
Included in any of the number blocks, the encoding means
Blocks from the storage means according to the block scan address
Compression of digital image signals transferred in units of blocks.
Restore processing is performed in lock units.

Preferably, the image processing device pairs the incident light.
Corresponding digital image signal and convert the digital image signal
Image signal generator that outputs to storage means in raster scan order
And a digital image signal output from the image signal generating means.
Generate and store block scan address corresponding to
And an address generating means for outputting to the means.
The means outputs from the image signal generating means in raster scan order.
Received digital image signal from address generation means
It is stored in association with the block scan address.

Preferably, the storage means is a dynamic type
Dynamic randomizer including random access memory
Multiple memory cells included in memory access memory
Memorize the digital image signal and use dynamic random access
Memory uses the fast page mode for digital image
Signal read operation.

Preferably, each of the plurality of blocks is high
Included on any page in fast page mode, multiple pages
Each signal of the digital image signal in each of the locks is
Each of the memory cells that make up the corresponding page
Paid.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIG. 1 is a schematic block diagram showing a configuration of a main part of an image processing apparatus 100 according to a first embodiment of the present invention. The same components as those of the conventional image processing apparatus 200 shown in FIG. 8 are designated by the same reference numerals and symbols, and the description thereof will be omitted.

The image processing apparatus 100 shown in FIG. 1 differs from the conventional image processing apparatus 200 shown in FIG. 8 in that in addition to the conventional image processing apparatus 200, an address generating circuit 60 is further provided.
And including the address conversion circuit 70, and particularly adopting the DRAM 41 as the memory 40. The DRAM 41 includes a plurality of memory cells (not shown).

The address generation circuit 60 responds to the pixel clock CLK, the horizontal synchronization signal HS and the vertical synchronization signal VS received from the timing generation circuit 50 to sequentially generate block scan addresses described later. In response to the block scan address, each of the image signals D (I, J) is stored in the corresponding memory cell included in the DRAM 41. The address conversion circuit 70 includes the CPU 150.
The raster scan address output by is converted into a block scan address. The address generation circuit 60 and the address conversion circuit 70 output the block scan address to the address bus AB. In response to the address supplied from the address bus AB, the corresponding memory cell is selected.

Next, the basic concept of the block scan address according to the first embodiment of the present invention will be described with reference to FIGS. 2 and 3.

FIG. 2 is a diagram showing an example of a divided state of the pixel array 11 according to the first embodiment of the present invention. As shown in FIG. 2, when allocating the block scan address,
The pixel array 11 is divided into a plurality of blocks. Each block includes a plurality of pixels. For example, the number of pixels arranged in the horizontal direction (block horizontal size) is 32 pixels, and the number of pixels arranged in the vertical direction (block vertical size) is 8 pixels.
Therefore, each block is composed of a set of 256 pixels in total. Hereinafter, a set of corresponding image signals D (I, J) will also be referred to as a block, and as shown in FIG. 2, will be referred to as a block 0, a block 1, ... In the order of raster scanning along the horizontal line direction.

FIG. 3 is a diagram showing the relationship between the blocks of the pixel array 11 shown in FIG. 2 and the compressed blocks, and block 0 is representatively shown. Each of the blocks is
Contains multiple compressed blocks. More specifically, as shown in FIG. 3, each block includes four compressed blocks (block 0 is compressed blocks 0, 1, 2 and 3).

Next, the block scan address according to the first embodiment of the present invention will be described with reference to FIGS. 4 and 5.

FIG. 4 is a diagram for explaining the block scan address in the first embodiment of the present invention. FIG. 4 shows pixels forming the pixel array 11 and relative addresses (numbers shown for each pixel in FIG. 4) assigned to each pixel. Further, FIG. 5 is a diagram expressing the relationship between the block scan address and the block shown in FIG. 4 in a continuous address space.

As shown in FIGS. 4 and 5, when viewed in block units by block scan address, the blocks are arranged in the horizontal line direction (blocks 0, 1, 2, ...).
, And within each block, addresses are assigned according to the raster scan.

In this case, in the continuous address space shown in FIG. 5, the image signals D (I, J) forming one block
(For example, in FIG. 5, image signals D (0,0) to D (31,0) and D (0,1) to D (3
1, 1), ..., D (0,7) to D (31,7)) are present in the same page. Therefore, the image signals D (I, J) forming one compressed block are all present on the same page.

The address generation circuit 60 shown in FIG.
The block scan address shown in FIG. 4 is assigned to each of the image signals D (I, J) output from the D conversion circuit 20 in the order of raster scan.

The image compression circuit 30 shown in FIG.
The image signal D (I, J) stored in 41 is read for each compressed block. Specifically, in the first transfer, D
Image signal D corresponding to compression block 0 from RAM 41
Upon receiving (I, J), compression processing is performed on these. Further, in the second transfer, the image signal D (I, J) corresponding to the compression block 1 is received from the DRAM 41 and these compression processes are performed.

In this case, as described above, each compressed block exists within one page. As a result, the image signal D (I, J) to be compressed can be read from the DRAM 41 at high speed using the high speed page mode access.

Further, the video encoder 35 shown in FIG.
Performs decompression processing for each compressed block on the image signal D (I, J) transferred from the DRAM 41 in block units. Also in this case, it is possible to use the fast page mode access. Reconstructed image signal D (I, J)
Are transferred to a display device (not shown).

Next, the operation and configuration of the address conversion circuit 70 shown in FIG. 1 will be described. Generally, in an image processing apparatus, a specific image signal (I, J) stored in the DRAM 41 may need to be processed or transferred to an internal circuit. When selecting a specific memory cell, the CPU 150 supplies the raster scan address (see the equation (1)), but in reality, the address mapping circuit (conversion to the block scan address) is performed by the address generation circuit 60 as described above. Has been done. Therefore, the address conversion circuit 70 according to the first embodiment of the present invention converts the raster scan address into the block scan address. As a result, the CPU 150
It is possible to read out the specific image signal D (I, J) stored in the specific memory cell designated by, and process the stored contents of the specific memory cell.

Here, the address conversion circuit 70 shown in FIG.
An example of the configuration will be described with reference to FIG.

FIG. 6 is a schematic block diagram showing an example of a specific configuration of address conversion circuit 70 in the first embodiment of the present invention. As shown in FIG. 6, the address conversion circuit 7
0 is division circuits 101, 102, 106 and 107,
Coupling circuits 103, 104, and 108, multiplication circuit 10
5, 109, 110, and 111, and an adder circuit 112.

The address conversion circuit 70 includes the pixel array 11
The number of horizontal pixels XSZ included in one horizontal line, the block size BSZ, the block horizontal size BX, the block vertical size BY, and the address A output by the CPU 150.
Receives DR (hereinafter referred to as CPU address ADR).
These default values are, for example, the number of horizontal pixels XS
Z is 640, block size BSZ is 256, block horizontal size BX is 32, and block vertical size BY is 8. The CPU address ADR is the image signal D
For (I, J), MADR (I,
J).

The division circuit 101 receives the number of horizontal pixels XSZ and the block horizontal size BX as inputs, and calculates the number of blocks XBLKS arranged in the horizontal line direction according to the equation (3).

XBLKS = int (XSZ / BX) (3) In the division circuit 107 and the division circuit 103, which block of the CPU address ADR corresponds to the horizontal line direction (denoted as XBNUM). To calculate. Specifically, the adder circuit 103 receives the CPU address ADR and the horizontal pixel number XSZ as inputs, and outputs the value X1 of the remainder obtained by dividing the address ADR by the horizontal pixel number XSZ (see formula (4)). . Further, the division circuit 107 is the division circuit 1
The output X1 of 03 and the block horizontal size BX are received as inputs, and the value XBNUM is output according to the equation (5).

X1 = mod (ADR / XSZ) (4) XBNUM = int (X1 / BX) (5) The division circuits 102 and 106 have the CPU address ADR.
, Which block corresponds to the vertical line direction (denoted as YBNUM) is calculated. Specifically, the division circuit 102 receives the address ADR and the horizontal pixel number XSZ as inputs, and outputs a value Y1 obtained by dividing the address ADR by the horizontal pixel number XSZ (see formula (6)). Further, division circuit 106 receives output Y1 of division circuit 102 and block vertical size BY as inputs, and outputs value YBNUM according to equation (7).

Y1 = int (ADR / XSZ) (6) YBNUM = int (Y1 / BY) (7) The adder circuit 104 receives the address A received from the CPU 150.
The DR calculates and outputs which pixel (XNUM) in the block in the horizontal line direction. Specifically, the adder circuit 104 receives the CPU address ADR and the block horizontal size BX as input, and outputs the value of the remainder obtained by dividing the CPU address ADR by the block horizontal size BX according to the equation (8). .

XNUM = mod (ADR / BX) (8) In the division circuit 102 and the division circuit 108, the pixel address of the CPU address ADR in the corresponding block along the vertical line direction ( YNUM) is calculated and output. More specifically, the division circuit 108 is the division circuit 1
The output Y1 of 02 and the block vertical size BY are received as inputs, and the output Y of the division circuit 102 is calculated according to the equation (9).
The remainder value obtained by dividing 1 by the block vertical size BY is output.

YNUM = int (Y1 / BY) (9) The multiplication circuit 105 outputs the output (XBLK) of the division circuit 101.
S) and block size BSZ are multiplied.

The multiplication circuit 109 outputs the multiplication circuit 105 (BSZ × XBLKS) and the division circuit 106 outputs (YB).
NUM). The multiplication circuit 110 is the division circuit 1
The output (XBNUM) of 07 and the block size BSZ are multiplied. The multiplication circuit 111 multiplies the output (YNUM) of the subtraction circuit 108 by the block horizontal size BX.

When one block is moved in the horizontal line direction, the block scan address is increased by BSZ. When one block is moved in the vertical line direction, the block scan address increases by (BSZ × XBLKS). If one pixel is moved in the horizontal line direction within the block, the block scan address is incremented by 1. Further, when moving one pixel in the vertical line direction within the block, the block scan address increases by BX.

Therefore, the addition circuit 112 outputs the output (XNUM) of the multiplication circuit 104, the multiplication circuit 109, and
By adding the outputs of 110 and 111,
For the image signal D (I, J), the block scan address BMADR (I, J) shown in Expression (10) is output.

BMADR (I, J) = XBNUM × BSZ + YBNUM × (BSZ × XBLKS) + XNUM + YNUM × BX (10) As a result, processing of the specific image signal D (I, J) or specific image signal Even when the transfer process of D (I, J) is required, the raster scan address output by the CPU 150 can be converted into the block scan address at high speed.

An example of a concrete configuration of the address generation circuit 60 shown in FIG. 1 is as shown in FIG. Figure 7
Is the address generation circuit 6 according to the first embodiment of the present invention.
It is a schematic block diagram which shows an example of the specific structure of 0. As shown in FIG. 7, the address generation circuit 60 includes a counter 6
2 and 64, arithmetic unit 66 and address generating unit 68
including.

The counter 62 counts the pixel clock CLK received from the timing generation circuit 50 with the horizontal pixel number XSZ as the upper limit value. The count value of the counter 62 indicates the horizontal pixel position I in the horizontal line direction. The counter 62 is reset in response to the horizontal synchronizing signal HS.

The counter 64 counts the horizontal synchronizing signal HS received from the timing generating circuit 50 with the upper limit of the number of vertical pixels YSZ included in one vertical line. The count value of the counter 64 indicates the vertical pixel position J in the vertical line direction. The counter 64 is reset in response to the vertical synchronization signal VS.

The arithmetic unit 66 receives the outputs of the counters 62 and 64 and calculates the value represented by the equation (1). The address generation unit 68 has the same configuration as the address conversion circuit 70 shown in FIG. 6, and receives the output of the calculation unit 66 instead of the CPU address ADR. As a result, the address generation circuit 60 outputs the block scan address in response to the pixel clock CLK, the horizontal synchronization signal HS, and the vertical synchronization signal VS (horizontal pixel position I and vertical pixel position J).

[0068]

According to the present invention, in an image processing apparatus using a DRAM as a storage means for an image signal, a block scan address for scanning each block is supplied to a conventional CPU which supplies a raster scan address. By providing means capable of
D from internal circuits such as encoder circuit and CPU
It is possible to access the RAM at high speed.
More specifically, since the high-speed page mode, which is a function of the DRAM, can be effectively utilized, the page hit rate becomes high, and the speed of image signal processing can be increased as a whole.

[Brief description of drawings]

FIG. 1 is an image processing device 1 according to a first embodiment of the present invention.
It is a schematic block diagram which shows the structure of the principal part of 00.

FIG. 2 is a diagram showing an example of a divided state of the pixel array 11 according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a relationship between blocks of the pixel array 11 shown in FIG. 2 and compressed blocks.

FIG. 4 is a diagram for explaining a block scan address according to the first embodiment of the present invention.

5 is a diagram expressing the relationship between block scan addresses and blocks shown in FIG. 4 in a continuous address space.

FIG. 6 is a schematic block diagram showing an example of a specific configuration of an address conversion circuit 70 according to the first embodiment of the present invention.

FIG. 7 is a schematic block diagram showing an example of a specific configuration of an address generation circuit 60 according to the first embodiment of the present invention.

FIG. 8 is a schematic block diagram showing a configuration of a main part of an image processing apparatus 200 in a conventional digital still camera.

9 is a schematic diagram showing an array of pixels included in the CCD circuit 10. FIG.

FIG. 10 is a schematic diagram showing an example of a relationship between a compression processing unit and a pixel array.

FIG. 11 is a diagram showing a relationship between a storage position and a page when an image signal D (I, J) is stored in a DRAM according to a raster scan address.

[Explanation of symbols]

10 CCD circuit 11 pixel array 20 A / D conversion circuit 30 image compression circuit 35 video encoder 41 DRAM 50 Timing generation circuit 60 address generation circuit 62, 64 counter 66 arithmetic unit 68 Address generator 70 Address conversion circuit 100 image processing device 101, 102, 106, 107 division circuit 103, 104, 108 Computation circuit 105, 109, 110, 111 multiplication circuit 112 adder circuit 150 CPU

Claims (5)

(57) [Claims] 1. An image processing device of an image pickup device for converting incident light from a subject into a digital image signal, wherein the image processing device is arranged in a horizontal direction and a vertical direction and has a plurality of blocks.
Which is incident on a plurality of pixels divided into blocks
The digital image signal corresponding to incident light
In the block unit of block, the order in the horizontal line direction
And in each of the plurality of blocks
To block scan address according to the order of star scan
Corresponding to the digital image signal stored in the storage means and the storage means stored on the basis of
Output the raster scan address to
Control means for instructing the reading of the image signal, and the raster scan address output from the control means.
The raster scan address to the corresponding block.
Block scan address, and the converted block
Address for outputting scan scan address to the storage means
Translation means, and the storage means receives the block from the address translation means.
Output a digital image signal corresponding to the
Forces, the image processing apparatus. 2. The digital image signal from the storage means
Is read for each specified compression block and compression processing is performed.
A compression means for transferring the compression result to the storage means
And is compressed by the compression means and recorded in the storage means.
Encoding hand that restores the stored digital image signal
Anda stage, each of said predetermined compression block, the plurality of blocks
The encoding means is included in any one of
Transferred in block units according to the scan address
For the digital image signal
The image processing apparatus according to claim 1 , wherein the restoration processing is performed at a unit. 3. The digital image corresponding to the incident light.
Signal to the digital image signal to the storage means
Image signal generating means for outputting in raster scan order, and the digital image output from the image signal generating means
Generate the block scan address corresponding to the signal
And address generating means for outputting to the storage means.
The storage means includes a raster scan from the image signal generation means.
The digital image signal output in the order
To the block scan address received from the
The image processing device according to claim 1, wherein the image processing device stores the data in association with each other . 4. The storage means is a dynamic type lander.
Memory access memory, included in the dynamic random access memory
A plurality of memory cells store the digital image signal, and the dynamic random access memory stores a high speed packet.
Read out operation of the digital image signal by using the charge mode.
Performed, the image processing apparatus according to claim 2. 5. Each of the plurality of blocks is the high speed
The digital image signal in each of the plurality of blocks included in any page of the page mode.
Each signal of the signal is a plurality of the messages that make up the corresponding page.
The image processing device according to claim 4 , wherein the image processing device is stored in each memory cell .