JP3530403B2 - Video camera - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video camera used as a surveillance camera or the like.

[0002]

2. Description of the Related Art FIG. 1 shows a configuration of a video camera for performing iris control (electronic iris control) using an electronic shutter. This video camera includes a single-plate color CCD 1 provided with a color filter array on the light receiving surface side.

FIG. 2 shows a part of a color filter array provided on the light receiving surface side of the single plate type color CCD 1.

In this example, in odd-numbered rows, cyan (Cy) color filters and yellow (Ye) color filters are alternately arranged in the horizontal direction. In the even-numbered rows, magenta (Mg) color filters and green (G) color filters are alternately arranged in the horizontal direction.

Here, in the mixing of light colors, a so-called addition method is established, so that R (red) and G of the three primary colors are used.
Mg and Y that have a complementary color relationship with (green) and B (blue)
The relationship of the following formula 1 is established between e and Cy.

[0006]

[Equation 1]

CC equipped with such a color filter array
A method of reading a signal from D1 will be described.

In the odd number (ODD) field, the pixel values of the odd-numbered rows in the vertical direction and the pixel values of the even-numbered rows therebelow are added and output. That is, in the nth scanning line, D1 (= Cy + Mg), D2 (= Ye +)
G), D1, D2 ... In this order, D3 (= Cy + G), D4 (= Ye + Mg), D3, D on the (n + 1) th scanning line.
The signals are output in the order of 4 ...

In an even (EVEN) field,
The pixel values of the even-numbered rows in the vertical direction and the pixel values of the odd-numbered rows below it are added and output. That is, in the m-th scanning line, D1 (= Mg + Cy), D2 (= G + Y)
e), D1, D2 ... D3 (= G + Cy), D4 (= Mg + Ye), D3, D in the m + 1th scanning line.
The signals are output in the order of 4 ...

Signals D1 to D4 output from CCD1
In the CDS / AGC circuit 2 are AGC and CDS (Corr
After being subjected to elated double sampling, it is sent to an AD conversion circuit (ADC) 3 and converted into a digital signal.

Image data D1 to D for each field
4 is sent to the YC separation circuit 4 and also sent to the first line memory 11 for outputting the image data with a delay of one horizontal period. Further, the image data delayed by one horizontal period by the first line memory 11 is
It is sent to the YC separation circuit 4 and also sent to the second line memory 12 for outputting the image data with a delay of one horizontal period. The image data delayed by one horizontal period by the second line memory 12 is sent to the YC separation circuit 4. That is, the YC separation circuit 4 receives image data for three horizontal lines.

In the YC separation circuit 4, the luminance signal Y (= 2B + 2R + 3G) is obtained by adding image data of adjacent pixels on the same horizontal line for each pixel, that is, by calculating D1 + D2 or D3 + D4.
Is generated. Further, a color difference signal is generated for each pixel by taking the difference from the image data of the adjacent pixel on the same horizontal line. Cb (= 2
BG) and Cr {=-(2R-G)}, and the color difference signal Cb is calculated by D1-D2, and the color difference signal Cr is calculated by D3-D4. Desired. Note that the signs of these color difference signals are alternately inverted for each pixel on the same horizontal line.

Since the two types of color difference signals Cb and Cr alternately appear for each horizontal line, three horizontal lines of image data are used to obtain the two types of color difference signals Cb and Cr for each horizontal line. The synchronization process was performed. That is, 3
When the color difference signal obtained by the middle one horizontal line of the horizontal lines is Cb, the color difference signal Cr cannot be obtained from the middle horizontal line, so two horizontal lines sandwiching the middle horizontal line. The color difference signal Cr for the middle horizontal line is obtained by averaging the color difference signals Cr obtained from the above.

The luminance signal Y obtained by the YC separation circuit 4 is sent to the Y process circuit 5 and the integrating circuit 8. The luminance signal Y and the color difference signals Cb and Cr obtained by the YC separation circuit 4 are sent to the C process circuit 6.

In the Y process circuit 5, γ correction and the like are performed. The luminance signal Y output from the Y process circuit 5 is D
The A conversion circuit (DAC) 7 converts the analog signal and outputs the analog signal.

In the C process circuit 6, after γ correction is performed, R, G and B signals which are the three primary color signals are obtained from the luminance signal Y, the color difference signal Cb and the color difference signal Cr. Further, a color difference signal (RY) and a color difference signal (BY) are obtained from the R, G, B signals. And the phase difference is 90 °
The two color subcarriers (3.58 MHz) are balanced-modulated by the color difference signals (RY) and (BY), respectively, and the carrier color signal C is generated. The carrier color signal C obtained by the C process circuit 6 is converted into an analog signal by the DA conversion circuit (DAC) 7 and output.

The brightness integrated value obtained by the integrating circuit 8 is sent to the CPU 9. The CPU 9 controls the timing control circuit (TG) 10 based on the brightness integrated value.
Thereby, switching control of the shutter time (exposure time or charge accumulation period) is performed.

That is, when the screen is dark, the shutter time is lengthened, and when the screen is bright, the shutter time is shortened. The shutter time is 1/60 [sec]
It can't be longer, so even if you maximize the shutter time,
When the screen is dark, the CPU 9 increases the AGC gain.

FIG. 3 shows the exposure timing during electronic iris control.

The charge accumulated in each pixel of the CCD is moved to the vertical transfer CCD by the charge read pulse, and C
The data is sequentially output as the CD is scanned.

The charge sweep pulse is a pulse for sweeping the charge accumulated on each pixel of the CCD toward the substrate of the CCD. Therefore, only the charges accumulated in the period from the output of the last charge sweep pulse of each field to the output of the charge read pulse of the next field are output from the CCD.

An amplifier is provided in the CCD output stage. This amplifier is susceptible to noise, so
As indicated by Tr, the charge read pulse is output during the vertical blanking period, and as shown by Ts in FIG. 4, the charge sweep pulse is normally output during the horizontal blanking period. In FIG. 4, the area indicated by hatching A is the video valid period. The area indicated by hatching B indicates the exposure period. As shown in FIG. 4, normally, the charge sweep pulse is not output during the effective video period.

[0023]

Problem to be Solved by the Invention [1] Problem under illumination of fluorescent lamp of 50 Hz When a video camera for performing iris control (electronic iris control) using an electronic shutter is used under illumination of fluorescent lamp of 50 Hz In addition, flicker occurs when the shutter time becomes short.

FIG. 5 shows changes in the amount of incident light and the brightness of an image when the shutter time (exposure period) is T under illumination of 50 Hz. As can be seen from FIG.
It can be seen that the brightness of the screen changes in a 3-field cycle.

Therefore, a method for making the brightness of the screen constant by changing the shutter time for each field in a three-field cycle has already been developed (Japanese Patent Laid-Open No. HEI 2).
186883).

As described above, when the shutter time control is performed to prevent flicker, it is necessary to finely control the shutter time. Therefore, as shown in FIG.
The output timing of the last charge sweep pulse may be within the effective video period.

When the charge sweep pulse is output during the effective video period, noise is added to the CCD output of that portion. When the shutter time control is performed to prevent flicker, the exposure time is different in each field of the three-field cycle, and therefore, the noise is present at a maximum of three positions, and noise appears at the same position. Since the period is 3 fields, flicker occurs in the noise part. Further, in the single-plate color CCD, as described above, the color signal is generated from the signal of three horizontal lines, so that the influence of noise spreads vertically to the three horizontal lines.

[2] Problem under illumination of fluorescent lamp of 60 Hz When a video camera is used under illumination of fluorescent lamp of 60 Hz, flicker does not occur. However, when the shutter time becomes very short, in exposure control in units of one horizontal period, the degree of change in screen brightness with respect to changes in the exposure time increases, so the shutter time is controlled in units of one horizontal period or less. Will be required. When the shutter time is controlled in units of one horizontal period or less, the output timing of the charge sweep pulse is within the effective image period, so noise is added to the CCD output of that portion.

[3] Object of the Invention The present invention provides a video camera in which the noise generated by the charge sweeping pulse does not appear in the video output even when the output timing of the charge sweeping pulse is within the effective video period. The purpose is to do.

[0030]

A video camera according to the present invention is a video camera for performing electronic iris control using an electronic shutter of a CCD, wherein the output of the CCD is AD.
AD conversion circuit for conversion, connected in series with the AD conversion circuit
3 line memories, AD conversion circuit and each line memory
Signals for 4 horizontal lines output from memory
The horizontal line output from the AD conversion circuit is always
Select and output 3 consecutive horizontal line signals including
One of these 3 horizontal lines has a valid video period
Noise is generated by the charge sweep pulse output during
If the added signal is present, the noise
At the timing when the added signal is output,
Vertical with a horizontal line separated from the noise added signal
Signals that are adjacent to each other in the direction
Signal selection means to be output instead, and signal selection means
YC separation based on the signals for 3 lines output from
YC separation means for performing is provided.

As the video camera, for example, 5
Prevents flicker that occurs under 0 Hz fluorescent lighting
Therefore, the brightness of the image in each field will be constant.
As described above, the one equipped with means for controlling the shutter time is
Used.

[0032]

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, referring to FIG. 7, in order to prevent flicker generated under the illumination of a fluorescent lamp of 50 Hz, the brightness of an image in each field is made constant. An embodiment in the case of being applied to a video camera equipped with means for controlling shutter time will be described.

FIG. 7 shows the structure of the video camera. 7, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In the video camera of FIG. 7, the portion surrounded by the chain line is added to the video camera of FIG. That is, the third line memory 13 is provided, and the image data delayed by one horizontal period by the second line memory 12 is sent to the YC separation circuit 4 and is delayed by one horizontal period, and the image data is delayed. Third for outputting
Is also sent to the line memory 13. The image data delayed by one horizontal period by the third line memory 13 is Y
It is sent to the C separation circuit 4.

The three selection circuits 21, 22, 23 are also provided.
And a control circuit 20 for controlling them based on a command from the CPU 9.

The first selection circuit 21 includes an AD conversion circuit 3
And the output of the second line memory 12 are input. The output of the first line memory 11 and the output of the third line memory 13 are input to the second selection circuit 22. The third selection circuit 23 includes an AD conversion circuit 3
And the output of the second line memory 12 are input.

Since the CPU 9 determines the shutter time,
When the output timing of the charge sweep pulse is within the effective video period, it is possible to recognize which timing (which pixel position) in the CCD output signal the noise is on. The CPU 9 controls the control circuit 20 so that the signal containing noise is not sent to the YC separation circuit 4.
The switching timing of 1 to 23 is set. Control circuit 2
0 controls switching of the selection circuits 21 to 23 according to the timing set by the CPU 9.

The operations of the selection circuits 21 to 23 will be specifically described below.

In the following description, a signal for one horizontal line output from the AD conversion circuit 3 is referred to as a signal for the i-th line, and a signal for one horizontal line output from the first line memory 11 is referred to. Is referred to as a signal on the (i + 1) th line, a signal for one horizontal line output from the second line memory 12 is referred to as a signal on the (i + 2) th line,
The signal for one horizontal line output from the third line memory 13 will be referred to as the (i + 3) th line signal.

The first selection circuit 21 always selects the output of the AD conversion circuit 3. In addition, the second selection circuit 22
Always selects the output of the first line memory 11. Further, the third selection circuit 23 always selects the output of the second line memory 12.

(1) In the case where the signal for one horizontal line output from the AD conversion circuit 3 contains a signal with noise (a signal for one pixel).

At the timing when the signal containing noise is sent from the AD conversion circuit 3 to the first selection circuit 21 and the third selection circuit 23, the first selection circuit 21 is stored in the second line memory 12. Switched to select output. The second selection circuit 22 remains in the selected state of the output of the first line memory 11, and the third selection circuit 23 remains in the selected state of the output of the second line memory 12.

Therefore, in this case, the signal of the (i + 2) th line from the first selection circuit 21, the signal of the (i + 1) th line from the second selection circuit 22, and the signal from the third selection circuit 23 ( The signal of the (i + 2) th line is output. In the YC separation circuit 4, the signal of the (i + 2) th line output from the first selection circuit 21 is regarded as the signal of the ith line, and the YC separation processing is performed.

The signal of the pixel next to the noisy signal is transmitted from the AD conversion circuit 3 to the first selection circuit 21 and the third selection circuit 21.
The timing of transmission to the selection circuit 23 of
The selection circuit 21 is switched to select the output of the AD conversion circuit 3.

(2) In the case where the signal for one horizontal line output from the first line memory 11 contains a signal with noise (a signal for one pixel).

At the timing when the signal containing noise is sent from the first line memory 11 to the second selection circuit 22, the second selection circuit 22 selects the output of the third line memory 13. Is switched to. The first selection circuit 21 remains in the state of selecting the output of the AD conversion circuit 3, and the third selection circuit 23 remains in the state of selecting the output of the second line memory 12.

Therefore, in this case, the signal of the i-th line from the first selection circuit 21, the signal of the (i + 3) -th line from the second selection circuit 22, and the (i + 2) -th signal from the third selection circuit 23. The signals of the lines are output respectively.
In the YC separation circuit 4, the signal of the (i + 3) th line output from the second selection circuit 22 is regarded as the signal of the (i + 1) th line, and the YC separation processing is performed.

At the timing when the signal of the pixel next to the noisy signal is sent from the first line memory 11 to the second selection circuit 22, the second selection circuit 22 causes the first line memory 11 to operate. Is switched to select the output of.

(3) In the case where the signal for one horizontal line output from the second line memory 12 contains a signal with noise (a signal for one pixel).

At the timing when the signal containing noise is sent from the second line memory 12 to the first selection circuit 21 and the third selection circuit 23, the third selection circuit 23 causes the AD conversion circuit 3 to operate. Switched to select output. The first selection circuit 21 remains in the state in which the output of the AD conversion circuit 3 is selected, and the second selection circuit 23
Shows that the output of the first line memory 11 remains selected.

Therefore, in this case, the signal of the i-th line from the first selection circuit 21, the signal of the (i + 1) -th line from the second selection circuit 22, and the i-th line from the third selection circuit 23. Are output respectively. In the YC separation circuit 4, the signal of the i-th line output from the third selection circuit 21 is regarded as the signal of the (i + 2) -th line, and Y
C separation processing is performed.

At the timing when the signal of the pixel next to the noisy signal is sent from the second line memory 12 to the first selection circuit 21 and the third selection circuit 23, the third selection circuit 23 is selected. Are switched to select the output of the second line memory 12.

(4) In the case where the signal for one horizontal line output from the third line memory 13 includes a signal with noise (a signal for one pixel). In this case, the switching control of the selection circuits 21 to 23 is not performed.

As described above, in this video camera, even when noise is added to the CCD output due to the charge sweep pulse output within the effective image period,
Since the YC separation process is performed without using the noise-laden signal, noise does not appear in the video output signal output from the video camera.

[0056]

According to the present invention, even when the output timing of the charge sweeping pulse is within the effective video period, the noise generated by the charge sweeping pulse does not appear in the video output.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram showing a configuration of a conventional video camera.

FIG. 2 is a schematic view showing a part of a color filter array provided on the light receiving surface side of CCD 1.

FIG. 3 is a time chart showing exposure timing during electronic iris control.

FIG. 4 is a schematic diagram showing the output timing of a general charge sweep pulse.

FIG. 5 is a time chart showing changes in the amount of incident light and the brightness of an image when the shutter time (exposure time) is T under illumination of 50 Hz.

FIG. 6 is a schematic diagram showing a case where a charge sweep pulse is output during an effective video period.

FIG. 7 is an electric circuit diagram showing a configuration of a video camera that is an embodiment of the present invention.

[Explanation of symbols]

1 CCD 3 AD conversion circuit 4 YC separation circuit 8 integrating circuit 9 CPU 10 Timing control circuit 11-13 line memory 21-23 selection circuit 20 Control circuit

Front page continued (72) Inventor Haruhiko Murata 2-5-5 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd. (72) Inventor Naohiro Takehishi 1-1 Sanyo-cho, Daito-shi, Osaka Sanyo Electronic Components Within the corporation (56) Reference JP 2000-32353 (JP, A) JP 7-162766 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N ^9/ 04- 9/11

Claims (2)

(57) [Claims] 1. In a video camera for electronic iris control using an electronic shutter of a CCD, an AD conversion circuit for AD converting the output of the CCD, three line memories serially connected to the AD conversion circuit , an AD conversion circuit, and Output from each line memory
Of the four horizontal line signals that are stored, the AD conversion
3 horizontal lines including horizontal lines output from the road
Select the signal of the horizontal line and output it.
The electric charge sweep output during the effective video period on one horizontal line
There is a signal with noise added by the output pulse
, The signal with the noise is output.
At the timing when the noise is added,
Signals that are vertically adjacent to each other with one horizontal line
A signal to be output instead of the signal to which the noise is added
3 lines output from the selecting means and the signal selecting means
A video camera , comprising YC separation means for performing YC separation based on a minute signal . 2. A flux generated under the illumination of a fluorescent lamp of 50 Hz.
Image brightness in each field to prevent lickers
To control the shutter time so that
The video camera according to claim 1, which is provided .