JP3532676B2 - Abnormal input detection circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an abnormal input detection circuit for detecting an abnormal input that is out of the used standard.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, there is one disclosed in JP-A-2-154160.

Generally, in order to prevent malfunction of the circuit, there is an abnormal input detection circuit which takes a measure such as stopping the operation when there is an abnormal input which is out of a predetermined standard.

A technique relating to such a conventional abnormal power input will be described.

In the case of the power supply voltage, a low voltage detection circuit is often used because the circuit generally causes a malfunction.

FIG. 11 is a diagram of such a conventional low voltage detection circuit.

In FIG. 11, R1, R2 and R3 are resistors, V _REF is a reference voltage (no voltage dependence), LVO is a low voltage detection signal, and SW1 is a switch.

Reference numeral 1 denotes a voltage comparison circuit, which sets LVO to "L" when the voltage at the + input is higher than that at the-input, and vice versa.
When the input is lower than the − input, LVO becomes “H”.

The principle of this circuit is to detect a low voltage by comparing a voltage value obtained by dividing the power supply voltage by a resistor with a reference voltage V _REF which is always constant without depending on the power supply voltage. It is configured.

A low voltage detection value is obtained by actually inserting a value.
In this circuit, R1 = 10 (kΩ), R2 = 10 (k
Ω), R3 = 15 (kΩ), and V _REF = 1.0V.

First, when the switch SW1 is ON, the voltage at the + input of the voltage comparison circuit 1 is [R1 / (R1 + R
2)] _Can be represented by V _DD . When this voltage becomes lower than the negative input voltage V _{REF of the} voltage comparison circuit 1, a low voltage is detected and LVO becomes “H”.

Therefore, the low voltage detection value LV becomes the voltage of V _DD when the + input and the-input of the voltage comparison circuit 1 are equal. The low voltage detection value LV has the following value.

LV = [(R1 + R2) / R1] V _REF =
It becomes 2.0V.

When the switch SW1 is OFF, the + input of the voltage comparison circuit 1 is [R1 / (R1 + R2 + R3)].
Since it becomes V _DD, it becomes the following LV.

LV = [(R1 + R2 + R3) / R1] V
_REF = 3.5V.

Conventionally, the value detected as a low voltage is fixed with respect to the power supply specifications. For example, in the case of a power supply voltage of 5V, it is usually within 5V ± 10%.
The low voltage detection value was 3.5V. That is, this is the case where SW1 of the circuit shown in FIG. 11 is OFF.

When the power supply voltage is 3V, it is usually 3
Since it is within V ± 10%, for example, the minimum voltage standard of 2.7
A low voltage detection value of 2.0 V was provided with a margin of 0.7 V relative to V. This is the case where SW1 of the circuit shown in FIG. 11 is ON.

Conventionally, with the same device, 3V specification / 5V
Since the specifications were not guaranteed at the same time, S in FIG.
W1 was a fixed switch in terms of hardware. The hard fixed switch, for example, has been performed by changing the wiring mask to short or open the wiring in the IC.

[0019]

However, in the above-mentioned conventional apparatus, when 5V specifications / 3V specifications are simultaneously guaranteed in the same device, an abnormal voltage value corresponding to each specification cannot be set.

For example, in the circuit shown in FIG. 11, if the low voltage detection value of the 5V specification is set, the operation of the 3V specification cannot be performed. Further, when the operation is set to the 3V specification, a voltage up to a considerably low voltage value (low voltage detection value in the 3V specification) is input when the specification is set to 5V.

The above is the same for the circuit for detecting a high power supply voltage, that is, a high voltage.

Further, it is necessary to detect an abnormal input similarly not only with the above-mentioned power supply voltage but also at the input clock frequency.

In order to solve the above problems, the present invention provides
While the power supply voltage or frequency is stable, the power supply voltage or frequency is automatically detected as to what specifications the power supply voltage or frequency is, and the detected value is switched according to that value It is an object to provide an abnormal input detection circuit that can detect an input.

[0024]

SUMMARY OF THE INVENTION The present invention, in order to achieve the above object, (1) supply voltage, the abnormal input detection circuit having a plurality of specifications such as the input clock frequency, above or below the predetermined voltage A first voltage detecting circuit for detecting whether or not, a latch circuit for latching the output of the first voltage detecting circuit, and a second voltage detecting circuit capable of varying the voltage detection level according to the value latched by the latch circuit. A voltage detection circuit is provided.

Therefore, the voltage specification can be automatically detected to determine the abnormal voltage detection value, and one device can set a plurality of abnormal voltage detection values for a plurality of power supply voltage specifications.

[0026] (2) supply voltage, the abnormal input detection circuit having a plurality of specifications such as the input clock frequency, a first frequency detection circuit for detecting the above or below a predetermined frequency,
According to the latch circuit that latches the output of the first frequency detection circuit and the value latched by this latch circuit,
A second frequency detection circuit capable of varying the frequency detection level is provided.

Therefore, since the abnormal frequency detection value can be determined by automatically detecting the input clock frequency specifications, one device can set a plurality of abnormal frequency detection values for a plurality of input clock frequency specifications.

[0028] (3) supply voltage, the abnormal input detection circuit having a plurality of specifications such as the input clock frequency, and storing means for storing information of specifications such predetermined power supply voltage or the input clock frequency, the output of the storage means And a circuit capable of changing the power supply voltage of the circuit operation and the upper and lower limits of the operating limit of the input clock frequency according to the value latched by the latch circuit.

Therefore, as compared with the above (1) or (2), since the first voltage detecting circuit or the first frequency detecting circuit is not required, the circuit can be simplified and the scale can be reduced. .

[0030] (4) power supply voltage, the abnormal input detection circuit having a plurality of specifications such as the input clock frequency, or operating power supply potential is a first power supply specifications, which is the first power supply potential, wherein the operating power second power supply A first voltage detection circuit that detects whether the power supply is the second power supply specification that is a potential, latches the detected power supply specification with a latch circuit, and outputs the power supply voltage specification detection signal, and the operating power supply potential A second voltage detection circuit for detecting that the operating power supply potential is an abnormal value higher or lower than a predetermined level, wherein the predetermined level can be set in response to the power supply voltage specification detection signal. A certain second voltage detection circuit is provided.

[0031] (5) supply voltage, the abnormal input detection circuit having a plurality of specifications such as the input clock frequency, or the operating frequency is the first frequency specification is first frequency, the operating frequency is the second frequency A first frequency detection circuit that detects whether it is the second frequency specification, latches the detected frequency specification with a latch circuit, and outputs the operating frequency specification detection signal; Is a second frequency detection circuit for detecting an abnormal value larger or smaller than a predetermined value, wherein the predetermined value can be set in response to the operating frequency specification detection signal. A detection circuit is provided.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is an abnormal voltage detection circuit diagram showing a first embodiment of the present invention, FIG. 2 is an operation timing chart of the abnormal voltage detection circuit, and FIG. 2 exemplifies the rising time of the power supply.

In this embodiment, it is automatically detected whether the power supply voltage specification is the 5V specification (5V ± 10%) or the 3V specification (3V ± 10%), and according to the result, The detection value of the low voltage detection circuit is decided.

In the embodiment of FIG. 1, R11, R12,
R13, R14, and R15 are resistors, V _REF is a reference voltage that is always constant without depending on the power supply voltage, LVO is a low voltage detection signal, SPEC is a power supply voltage specification detection signal, and SW is an abnormal voltage detection value switching signal. is there.

Further, 11 and 12 are voltage comparison circuits,
If the + input is higher than the − input (reference input), “L” is output, and conversely, if the + input is lower than the − input (reference input), “H” is output. 13 is a D type latch, and when the LD input is “H”, the D input is taken in and Q
When the LD input is "L", the LD is "H"
At that time, the D input that was taken in is latched and output to Q. Further, 14 is a 2-input AND circuit, and 15 is an inverter circuit.

Tr1 is an N-channel type transistor, and when the gate input is "H", the transistor is turned on and becomes conductive, and when the gate input is "L", the transistor is turned off and opened.

The operation of this abnormal voltage detection circuit will be described below.

The first voltage detection circuit 21 surrounded by the dotted line in FIG. 1 is a circuit for detecting what voltage specifications the power supply voltage has. In this embodiment, 5V specifications (5V ± 10%: 4.
5V-5.5V) or 3V specification (3V ± 10%: 2.7
(V to 3.3V) is detected, a certain constant voltage within the voltage range 3.3V to 4.5V for distinguishing the power supply voltage specifications, for example, V _DD = 4.0V is set. Identify the power supply voltage specification based on whether it is high or low. As this first voltage detection circuit 21, the same one as the low voltage detection circuit described in the prior art is used.

The first voltage detection circuit 21 sets the low voltage detection value to 4.0V, and if the voltage is higher than that, recognizes the 5V specification and sets the SPEC signal to "L", and if the voltage is lower than that. Recognizing the 3V specification, the SPEC signal is set to "H".

The above-mentioned SPEC signal is used as D input, and LOA
Latch by the latch circuit that uses the D signal as the load input, and switch
The signal is Q output.

The second voltage detection circuit 22 surrounded by the dotted line in FIG. 1 is the same as that described in the prior art, but the transistor Tr1 (N-channel type transistor) is used instead of the conventional switch SW. ing.

When the 5V specification is detected, the SPEC signal becomes "L" and the SW signal also becomes "L". Therefore, T
The transistor of r1 is turned off, and the low voltage detection value of the 5V specification is obtained. If 3V specifications are detected, SP
The EC signal becomes "H", and the SW signal also becomes "H". Therefore, the transistor of Tr1 is turned on, and the low voltage detection value of the 3V specification is obtained. Further, when the 2-input AND circuit 14 and the inverter circuit 15 are detecting the power supply voltage specification,
This is a circuit for preventing the low voltage detection LVO from being erroneously output.

Using the time chart of FIG. 2, the power supply is turned on as an example and will be described in time series.

First, the period (1) in FIG. 2 is a period when the power supply voltage is unstable, and after this period, the stable period of the power supply voltage is entered. In addition, during the period (2), the first voltage detection circuit 21
This is a period with plenty of time to fully operate.
The period (3) is a normal operation period. The period (4) is a case where an abnormal low voltage occurs.

During the periods (1) and (2), the LOAD signal is set to "H", the low voltage detection output LVO remains "L", and there is a possibility of causing a malfunction during this period. Prohibit the whole circuit operation by signals.
During the period (2), the first voltage detection circuit 21 detects the power supply voltage specification and determines the low voltage detection value. From the period (3), the low voltage detection circuit can operate. In the period (4), an abnormal low voltage is detected and the LVO output is set to "H".

The low voltage detection circuit described above can also be applied to a high voltage detection circuit. The high voltage detection circuit is shown in FIG. The high voltage detection circuit can be realized by exchanging the + input and − input (reference input) of the voltage comparison circuit of the low voltage detection circuit and changing the resistance value (resistance ratio).

Therefore, as shown in FIG. 3, the resistors R16, R17, R18 and the voltage comparison circuit 1 are used as voltage dividing resistors.
9 is provided. Other than that is the same as that of FIG.

As shown in FIG. 3, the + input-input (reference input) of the voltage comparison circuit is replaced, and the resistance value (resistance ratio) is changed.
It can also be applied to a high voltage detection circuit by changing.

The operation is the same as that of the low voltage detection circuit, and will be omitted.

Next, a second embodiment of the present invention will be described.

Although the power supply voltage has been described above, the abnormality detecting circuit of the input clock frequency will be described here.

For example, according to the ISO specifications of smart cards, there are two input CLK frequencies, 5 MHz and 3.3 MHz, and it is necessary to satisfy both specifications.

The present invention has two inputs CLK frequencies such as this.
When there are one or more specifications, anomalies can be detected for each specification.

At present, even if there are specifications of a plurality of input CLK frequencies, only one specification of abnormality can be detected. For example, if there are specifications of 5.5 MHz and 3.3 MHz, 5
There was no choice but to set a frequency value higher than MHz as an upper limit and a frequency value lower than 3.3 MHz as a lower limit. Therefore, 5MHz
Abnormalities such as ± 10% and 3.3 MHz ± 10% could not be detected.

In order to solve such a problem, input CL
While the K frequency is stable, the input CLK frequency automatically detects what frequency value the specification has, and switches the abnormal frequency detection value.

FIG. 4 shows an abnormal frequency detection circuit diagram showing the second embodiment of the present invention (the result is output to the SPEC signal), FIG. 5 shows the first frequency detection circuit diagram, and FIG. 6 shows the first frequency detection circuit diagram. The figure which shows the output voltage VO of the integration circuit of a frequency detection circuit, FIG.
FIG. 4 is a second frequency detection circuit diagram thereof.

In FIG. 4, 30 is a first frequency detecting circuit and 40 is a second frequency detecting circuit for detecting an abnormality in the input CLK frequency. The abnormality detection value changes depending on the value of the SW signal (result is OUT. Output to the signal). Reference numeral 51 is a D-type latch, 52 is a 2-input AND circuit, and 53 is an inverter circuit.

Next, the first frequency detection circuit 30 will be described.

In FIG. 5, 31 and 33 are operational amplifiers, and 34 is a D type flip-flop which latches at the falling edge of the clock. CLK is clock input, S
PEC is an output and -V _REF 1 is a negative reference voltage [Note that the example of FIGS. 5 and 7 shows an example of using an analog active filter for the sake of easy understanding, but SCF (switch De-capacitor filter), digital filter may be used]. The circuit 32 surrounded by a dotted line is an integrating circuit.

The output voltage VO of the integrating circuit 32 can be expressed by the following equation (see FIG. 6).

VO =-[Vin / (CO.RO)]. T Vin is the peak value of the input clock, and t is its "H" period. Therefore, the output voltage VO has a value proportional to the cycle of the input clock. That is, when the cycle of the input clock is long (frequency is low), the output voltage VO also becomes low. The output voltage VO and the negative reference voltage (-V _REF 1) are compared by the operational amplifier 33. Further, the comparison result is latched by the D type latch 51 at the falling edge of the clock. When the output voltage VO becomes lower than the reference voltage, SP
EC becomes "H" and vice versa.

In this circuit, the value of CO.RO is selected so that the output voltage VO becomes -2 V when f = 4 MHz (250 ns). When the reference voltage is set to -2V, this circuit has a lower frequency than 4MHz (f =
3MHz ± 10%), SPEC becomes “H”, and 4
S when the specification is higher than MHz (f = 5MHz ± 10%)
PEC becomes “L”.

As shown in FIG. 7, in the second frequency detection circuit 40, 43 is a D type latch, and when the LD input is "H", the D input is taken in and output to Q,
When the LD input is "L", the previously input D input is latched and output to Q. This circuit is a circuit for taking in what kind of specification of the CLK input during the stable period of the frequency (the period when LOAD is "H").

The second abnormal frequency (for low frequency) detection circuit 40 shown in FIG. 7 has the same principle as FIG. 5 and is almost the same circuit as FIG. 5, but the value of the negative input V _N of the operational amplifier 42. Is different in that the value of the negative reference voltage (-V _REF 2) is divided by the resistors R2 to R4.

With this configuration, the low frequency detection value can be changed by changing the value of V _N by the SW signal. Reference numeral 41 is an operational amplifier.

[0067] For example, when SW = L is, V _N = [R2 / (R2 + R3 + R4 ) ] · (-V _REF 2) = - When 3V SW = H is, V _N = [R2 / (R2 + R3)] - (−V _REF 2) = − 4V If the values of R1 and C1 are made the same as those in FIG. 5 (it becomes −2V at 4 MHz), when SW = L, OUT becomes “H” at 3 MHz or less. When SW = H, 2MHz
OUT can be set to "H" in the following cases.

Therefore, when SW = L, f = 5 MHz ±
It is possible to detect an abnormal low frequency of 3 MHz for the 10% specification, and it is possible to detect an abnormal frequency of 2 MHz for the f = 3 MHz ± 10% specification when SW = H.

FIG. 8 is an operation timing chart of the abnormal frequency detection circuit showing the second embodiment of the present invention.

Here, the case where the low frequency detection value is set to 3 MHz by detecting the specification of f = 3 MHz ± 10% is taken as an example.

The period (1) in FIG. 8 (the period in which LOAD is "H") is a period in which the frequency is stable, and it is determined what specifications the clock frequency is in this period. The clock for this period is 3 MHz. This 3 MHz clock is 4 which is the judgment standard of the first frequency detection circuit 30 of FIG.
Since the frequency is lower than MHz, SPEC is "H".
Becomes

The SPEC input is latched at the falling edge of the LOAD signal of the D type latch 51 shown in FIG. Figure 8
The period (2) and after is a normal operation period, and when a low frequency occurs during this period, it is necessary to detect an abnormality.

The second frequency detection circuit 40 of FIG.
Is “H”, it is recognized that the specification is f = 3 MHz ± 10%, and the detected value of the abnormal low frequency is set to 2 MHz.

Next, when the frequency becomes abnormally low (1.5 MHz) in the period (3), OUT is set to "H" in the second frequency detection circuit 40 of FIG. 4, and LFO is also set to "H". Is output.

The 2-input AND circuit 52 and the inverter circuit 53 in FIG. 4 are circuits for not performing abnormality detection during LOAD.

Also, abnormal high frequencies can be detected by the same method. In that case, the second frequency detection circuit 40 of FIG. 4 becomes a circuit as shown in FIG.

The operation of this circuit will be described below with reference to FIG.

This circuit is 5 MH when SW is "L".
Considering the z ± 10% specification, the reference voltage of V _P is [R7 / (R5 + R6 + R7)] · (−V _REF 3) = −
Set to 1.5V.

When SW is "H", the reference voltage of V _P is [R6 / (R5
+ R6)] · (−V _REF 3) = − 2.0V.

Therefore, when SW is "L", f is 6 MH
When z or more, OUT is set to "H", and when SW is "H", OUT is set to "H" when f is 4 MHz or more.

Since the timing and the like are the same as those of the low frequency detection circuit, description thereof will be omitted.

Next, a third embodiment of the present invention will be described.

Up to now, the specifications of the power supply voltage or frequency were automatically detected. However, when the power supply voltage and frequency specifications are given as information in advance, it is not necessary to automatically detect them, and It only needs to have a flag that stores information.

FIG. 10 is a low voltage detection circuit diagram showing a third embodiment of the present invention.

This circuit is the same as that shown in FIG. 1 except that the first voltage detection circuit 21 in FIG. 1 is deleted and a control device 60 such as a microcontroller having a memory circuit 61 is substituted.
Is exactly the same as. That is, since the power supply voltage specification is given as information in advance and is stored in the storage circuit 61, it is not necessary to automatically detect it by the first voltage detection circuit 21 as in FIG.

The operation of this circuit will be described below.

First, in accordance with the power supply voltage specification of this device stored in the storage circuit 61 of the control device 60 such as a microcontroller, the SPEC signal is given a level of "H" or "L", and the LOAD signal is changed to " Set to "H" and input to D latch. For example, in the case of 5V specifications,
“L” is latched, and “H” is latched in the case of 3V specification. The subsequent operation is similar to that of the first embodiment.

Similarly, in the case of frequency detection, FIG.
The first frequency detection circuit 30 is unnecessary, and although not shown, a control device such as a microcontroller having a storage circuit can be substituted.

The present invention is not limited to the above embodiments, but various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention. .

[0090]

As described in detail above, according to the present invention, the following effects can be achieved.

[0091] According to the present invention of (A) according to claim 1 or 4, wherein the supply voltage, the abnormal input detection circuit having a plurality of specifications such as the input clock frequency, automatically detects the power supply voltage specification, specification Since the latch circuit for storing is stored, the abnormal voltage detection value can be determined, and one device can set a plurality of abnormal voltage detection values for a plurality of power supply voltage specifications.

[0092] (B) According to the present invention of claim 2 or 5, wherein the supply voltage, the abnormal input detection circuit having a plurality of specifications such as the input clock frequency, automatically detects the input clock frequency Specifications Since the latch circuit for storing the above is provided, the abnormal frequency detection value can be determined, so that one device can set a plurality of abnormal frequency detection values for a plurality of input clock frequency specifications.

(C) According to the present invention of claim 3, an abnormal input detection circuit having a plurality of specifications such as a power supply voltage and an input clock frequency is compared with the above (A) or (B). Moreover, since the first voltage detection circuit or the first frequency detection circuit is not required, the circuit can be simplified and the scale can be reduced.

[Brief description of drawings]

FIG. 1 is an abnormal voltage detection circuit diagram showing a first embodiment of the present invention.

FIG. 2 is an operation timing chart of the abnormal voltage detection circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a modified example (abnormal high voltage detection) of the abnormal voltage detection circuit according to the first embodiment of the present invention.

FIG. 4 is an abnormal frequency detection circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a first frequency detection circuit diagram of an abnormal frequency detection circuit showing a second embodiment of the present invention.

FIG. 6 is a diagram showing the output voltage VO of the integrating circuit of the first frequency detecting circuit of the abnormal frequency detecting circuit of the second embodiment of the present invention.

FIG. 7 is a second frequency detection circuit diagram of the abnormal frequency detection circuit showing the second embodiment of the present invention.

FIG. 8 is an operation timing chart of the abnormal frequency detection circuit showing the second embodiment of the present invention.

FIG. 9 is a circuit diagram showing a modified example (high frequency detection) of the abnormal frequency detection circuit according to the second embodiment of the present invention.

FIG. 10 is a low voltage detection circuit diagram showing a third embodiment of the present invention.

FIG. 11 is a conventional low voltage detection circuit diagram.

[Explanation of symbols]

11, 12, 19 Voltage comparison circuit 13,43,51 D type latch 14,52 2-input AND circuit 15,53 Inverter circuit 21 First Voltage Detection Circuit 22 Second voltage detection circuit 30 First Frequency Detection Circuit 31, 33, 41, 42 Operational amplifier 32 integrating circuit 34 D-type flip-flop 40 Second Frequency Detection Circuit 60 control device 61 Memory circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ identification code FI H02H 3/46 H02H 3/46 D (58) Fields investigated (Int.Cl. ⁷ , DB name) H02H 3/08-3 / 253 G01R 19/165

Claims (5)

(57) [Claims] 1. A power supply voltage, the abnormal input detection circuit having a plurality of specifications such as the input clock frequency, a first voltage detection circuit for detecting the above or below (a) a predetermined voltage, (b) the A latch circuit for latching the output of the first voltage detection circuit; and (c) a second voltage detection circuit capable of varying the voltage detection level according to the value latched by the latch circuit. Abnormal input detection circuit. 2. A supply voltage, the abnormal input detection circuit having a plurality of specifications such as the input clock frequency, a first frequency detection circuit for detecting the above or below a predetermined frequency (a), (b) the A latch circuit for latching the output of the first frequency detection circuit; and (c) a second frequency detection circuit capable of varying the frequency detection level according to the value latched by the latch circuit. Abnormal input detection circuit. 3. A supply voltage, the abnormal input detection circuit having a plurality of specifications such as the input clock frequency, and storing means for storing (a) information specifications such predetermined power supply voltage or the input clock frequency, (b) A latch circuit for latching the output of the storage means; and (c) a circuit capable of varying the power supply voltage of the circuit operation and the upper and lower limits of the operating limit of the input clock frequency according to the value latched by the latch circuit. An abnormal input detection circuit characterized by: 4. A power supply voltage, the abnormal input detection circuit having a plurality of specifications such as the input clock frequency, or operating power supply potential is a first power supply specifications, which is the first power supply potential, wherein the operating power second power supply potential The second power supply specification is detected, the detected power supply specification is latched by the latch circuit, and the power supply voltage specification detection signal is output.
And a second voltage detection circuit for inputting the operating power supply potential and detecting whether the operating power supply potential is an abnormal value higher or lower than a predetermined level, wherein the predetermined level is Second that can be set in response to the power supply voltage specification detection signal
An abnormal input detection circuit. 5. A supply voltage, the abnormal input detection circuit having a plurality of specifications such as the input clock frequency, or the operating frequency is the first frequency specification is first frequency, the said operating frequency is a second frequency 2 frequency specifications, the detected frequency specifications are latched by a latch circuit, and a first frequency detection circuit that outputs the operating frequency specification detection signal; A second frequency detection circuit for detecting an abnormal value that is larger or smaller than a predetermined value, wherein the predetermined value can be set in response to the operating frequency specification detection signal. And an abnormal input detection circuit.