JP3532873B2 - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a plurality of semiconductor elements formed on a substrate and an exposure method used for manufacturing the same.

[0002]

2. Description of the Related Art In manufacturing a semiconductor integrated circuit device,
A step-and-repeat type reduction projection aligner (hereinafter referred to as an optical stepper) is widely used.

In recent years, semiconductor integrated circuit technology has made remarkable progress, and the minimum design rule has been miniaturized to about 70% in a cycle of about three years, and the chip area has tended to double. In order to cope with such miniaturization and increase in chip area, in the optical stepper, in addition to a large aperture coefficient (large NA) and a short exposure wavelength for improving resolution, the exposure area (field ) Has been promoted toward a larger area, that is, a larger field. One field of the latest optical stepper is about 22 mm □ on the exposed material.

Further, in manufacturing a semiconductor integrated circuit device having an outer shape larger than one field of an optical stepper, a rectangular (including square in this specification) substrate serving as a semiconductor chip is provided with a plurality of small main surfaces. A method of partitioning into rectangular areas and forming functional blocks in each small rectangular area as one field, and connecting the functional blocks to each other by wiring crossing the boundaries between the small rectangular areas (see Japanese Patent Laid-Open No. 63-258042). ) Etc. have been used. In this method, the wiring that connects the functional blocks (hereinafter, referred to as global wiring) is formed by connecting the patterns transferred to each small rectangular area during exposure. For this reason, the global wiring is usually provided in a wiring layer having a wide wiring width that does not cause a connection error caused by joining the patterns.

FIG. 5 is an enlarged plan view of a part of a conventional semiconductor integrated circuit device formed by the above method.

As shown in FIG. 5, the main surface of the substrate 80 is 2
It is partitioned by a plurality of rectangular areas 81 (areas surrounded by broken lines) arranged in a dimension. When an optical stepper is used, exposure is performed with the rectangular area 81 as one field.

Further, as shown in FIG. 5, four adjacent rectangular areas 81, specifically, a first rectangular area 81a, a second rectangular area 81b, a third rectangular area 81c and a fourth rectangular area 81a. Inside each of the regions 81d, a first element group 82a, a second element group 82b, and a third element group 82a having a fine pattern are formed.
The element group 82c and the fourth element group 82d are arranged. Each element group 82 has at least one element formed on the substrate.
It is composed of individual semiconductor elements. In addition, the element group 82
The wirings 83 that connect each other are arranged so as to cross the boundary between the rectangular regions 81, that is, the field boundary indicated by a broken line.

That is, since each wiring 83 is formed by connecting the patterns transferred to each rectangular area 81 during exposure, a connection error occurs in the portion of each wiring 83 located at the field boundary. Therefore, the wiring layer in which each wiring 83 is formed needs to be formed as a pattern layer having a relatively large design rule such that disconnection or short circuit does not occur due to a connection error.

On the other hand, with the recent rapid miniaturization of the apparatus, an electron beam stepper (hereinafter referred to as EPL) using an electron beam having a higher resolution than light as an exposure light source.
Is being researched and developed.

In the electron lens used for the EPL, the aberration rapidly increases as the orbit of the electron moves away from the center of the optical axis, so that it is difficult to secure a large field (20 mm □ or more) like the optical lens. . Therefore, in the EPL, the main surface of the substrate to be exposed is 250
Small area of about μm □ (hereinafter referred to as subfield)
A method is being used in which the pattern is transferred to each subfield by partitioning into two parts and the patterns transferred to each subfield are connected to each other to form a pattern for the entire semiconductor chip.

[0011]

Increasing the NA and increasing the field in the optical stepper leads to an increase in the lens diameter of the imaging optical system, and as a result, the lens diameter reaches the limit of industrial manufacturing. Therefore, it is becoming difficult to achieve both larger field and higher NA than at present. Further, since the mask pattern is also miniaturized with the miniaturization of the device, it is becoming difficult to secure the dimensional accuracy of the mask pattern.

Therefore, in the optical stepper, it is considered to reduce the reduction ratio from the current 4-5 times to 6-10 times. On the other hand, if the reduction ratio is increased, it becomes difficult to fit the circuit pattern of the entire semiconductor chip into one exposure mask. Therefore, in the optical stepper as well, an exposure method has been studied in which the main surface of the substrate to be the semiconductor chip is divided into several fields and the pattern transfer is performed for each field to form the pattern of the entire semiconductor chip.

However, an optical stepper or EP
When the patterns transferred to the field or subfield are connected to each other by using L or the like, a connection error occurs at the connection portion between the patterns as described above. For example, when the EPL is used, a joint portion is generated for each subfield of about 250 μm □, and a connection error occurs in the joint portion.

FIGS. 6A to 6C are diagrams showing a connection error occurring at a joint portion between patterns in a conventional semiconductor integrated circuit device. In FIGS. 6A to 6C, 91a and 91b (regions surrounded by broken lines)
Is an exposure region (one field of the optical stepper or one subfield of the EPL) adjacent to each other, and 92 is a pattern formed by joining the patterns transferred to the exposure regions 91a and 91b, respectively. Is a connecting portion of the pattern 92.

As shown in FIG. 6A, the exposure area 91a
And 91b are located apart from each other, the joint portion 93 of the pattern 92 is locally thin.

Further, as shown in FIG. 6B, when the exposure areas 91a and 91b are positioned so as to partially overlap each other, the joint portion 93 of the pattern 92 becomes locally thick.

Further, as shown in FIG. 6C, when the exposure areas 91a and 91b are positioned so as to be displaced from each other, the joint portion 93 of the pattern 92 is constricted.

In an actual semiconductor integrated circuit device, a local variation in the pattern size shown in FIGS. 6A and 6B and a constriction of the pattern shown in FIG. 6C are combined to cause a connection error. As a result, the performance and reliability of the device is degraded. For example, if a connection error occurs in the gate electrode on the active region, a problem such as fluctuation of the threshold voltage is caused. Further, when a connection error occurs in the wiring layer, stress migration, electromigration, or the like occurs, and as a result, the reliability of the device is significantly deteriorated.

On the other hand, when the method disclosed in Japanese Patent Laid-Open No. 63-258042 (see the prior art) is applied to an EPL having a maximum size of one sub-field of about 250 μm □, a connection error does not matter. Since it is necessary to connect the wirings between the functional blocks using only the pattern layer having a relatively large design rule, the degree of freedom in designing the mask pattern layout of the integrated circuit is greatly limited.

In view of the above, it is an object of the present invention to form a circuit pattern larger than one field of an optical stepper or one subfield of an EPL without a connection error.

[0021]

In order to achieve the above object, a first semiconductor integrated circuit device according to the present invention is premised on a semiconductor integrated circuit device having a plurality of semiconductor elements formed on a substrate. , The main surface of the substrate is partitioned by a plurality of element placement areas, and is also partitioned by a plurality of wiring placement areas provided so as to cross the boundary between the plurality of element placement areas. Inside the region, an element group including at least one semiconductor element among a plurality of semiconductor elements and a local wiring connecting the semiconductor elements in the element group are arranged, and a plurality of wiring arrangement areas are provided. Global wiring for connecting the element groups to each other is arranged inside the.

According to the first semiconductor integrated circuit device, at least 1 is provided inside the element disposition region that partitions the main surface of the substrate.
An element group composed of individual semiconductor elements and local wirings for connecting the semiconductor elements in the element group are arranged. For this reason, the size of the element placement region is set to one field of the optical stepper used for forming the circuit pattern or EPL.
By setting the size to be equal to or smaller than the size of 1 subfield or the like, the element group and the local wiring can be formed in the element arrangement region without a connection error. As a result, it is possible to prevent the fluctuation or deterioration of the element characteristics due to the connection error. Further, it is possible to prevent disconnection or the like in the local wiring due to electromigration or stress migration due to a connection error. Therefore, it is possible to prevent the performance and reliability of the semiconductor integrated circuit device from deteriorating.

Further, according to the first semiconductor integrated circuit device, the global wiring for connecting the element groups is arranged inside the wiring arrangement area that partitions the main surface of the substrate and crosses the boundary between the element arrangement areas. ing. Therefore, by setting the size of the wiring arrangement region to be equal to or smaller than the size of one field of the optical stepper or one subfield of the EPL, global wiring crossing the boundary between the element arrangement regions, for example, adjacent ones. Global wirings that connect the element groups arranged in the pair of element arrangement regions can be formed without a connection error. Therefore, the element groups, that is, the functional blocks can be connected over a large area without reducing the reliability of the global wiring, and a semiconductor integrated circuit device having a large chip area can be realized.

Further, according to the first semiconductor integrated circuit device, since the size of each element arrangement area and each wiring arrangement area can be made variable, the degree of freedom in the mask pattern layout design of the integrated circuit is improved.

The second semiconductor integrated circuit device according to the present invention is premised on a semiconductor integrated circuit device having a plurality of semiconductor elements formed on a substrate, and the main surface of the substrate has a predetermined shape and has a predetermined shape. It is partitioned by a plurality of element placement areas that are two-dimensionally arranged with a shape as a repetition cycle, and has the same shape as the plurality of element placement areas and an array of a plurality of element placement areas with the shape as a repetition cycle. Are separated from each other by a plurality of wiring arrangement areas that are two-dimensionally arranged so as to be displaced from each other by a predetermined distance. Inside the plurality of element arrangement areas, at least one semiconductor among a plurality of semiconductor elements is provided. An element group composed of elements and local wirings that connect the semiconductor elements in the element group are arranged, and global wirings that connect the element groups are provided inside the plurality of wiring arrangement areas. It is location.

According to the second semiconductor integrated circuit device, at least one element is provided inside the element placement region that partitions the main surface of the substrate.
An element group composed of individual semiconductor elements and local wirings for connecting the semiconductor elements in the element group are arranged. For this reason, the size of the element placement region is set to one field of the optical stepper used for forming the circuit pattern or EPL.
By setting the size to be equal to or smaller than the size of 1 subfield or the like, the element group and the local wiring can be formed in the element arrangement region without a connection error. As a result, it is possible to prevent the fluctuation or deterioration of the element characteristics due to the connection error. Further, it is possible to prevent disconnection or the like in the local wiring due to electromigration or stress migration due to a connection error. Therefore, it is possible to prevent the performance and reliability of the semiconductor integrated circuit device from deteriorating.

According to the second semiconductor integrated circuit device, the wiring is arranged so as to partition the main surface of the substrate and to be displaced by a predetermined distance with respect to the arrangement of the element arrangement regions at the same repetition period as the element arrangement regions. Global wirings that connect the element groups to each other are arranged inside the arrangement region. For this reason, the size of the wiring arrangement area should be the same as that of the optical stepper.
By setting the size to be equal to or smaller than the size of one subfield of the field or EPL, global wirings crossing the boundary between the element arrangement regions, for example, element groups arranged in a pair of adjacent element arrangement regions are connected to each other. Global wiring can be formed without connection error. Therefore, the element groups, that is, the functional blocks can be connected over a large area without reducing the reliability of the global wiring, and a semiconductor integrated circuit device having a large chip area can be realized.

Further, according to the second semiconductor integrated circuit device, the element arrangement region and the wiring arrangement region have a predetermined shape and are two-dimensionally arranged with the shape as a repeating cycle. Therefore, it becomes easy to perform exposure by using the element arrangement area and the wiring arrangement area as one field of the optical stepper or one subfield of the EPL.

In the first or second semiconductor integrated circuit device, a wiring connection terminal that crosses the boundary between the plurality of wiring arrangement areas is arranged inside at least one element arrangement area of the plurality of element arrangement areas. Is preferably provided.

With this configuration, the wiring connecting terminals can relay the global wirings arranged in the pair of wiring arrangement regions adjacent to each other. For this reason, since it is possible to form a global wiring that substantially extends over three or more element arrangement regions, the degree of freedom in the mask pattern layout design of the integrated circuit is improved.

In the second semiconductor integrated circuit device, it is preferable that the predetermined distance is half the repeating period.

By doing so, the global wiring can be formed so as to extend in the same length in each of the pair of adjacent element arrangement regions, so that the degree of freedom in the mask pattern layout design of the integrated circuit is improved.

In the first exposure method according to the present invention, a corresponding pattern is formed in each of the plurality of first regions that partition the main surface of the substrate to be exposed by exposure using an electromagnetic wave or a charged particle beam. By repeating the process of forming a lower layer pattern on the substrate to be exposed, and exposing the corresponding pattern to each of the plurality of second regions partitioning the main surface of the substrate to be exposed using electromagnetic waves or charged particle beams. Forming the upper layer pattern on the substrate to be exposed so as to overlap the lower layer pattern, and each of the plurality of second regions includes a plurality of first regions.
It is provided so as to cross the boundary between the regions.

According to the first exposure method, the lower layer pattern is formed by repeating the formation of the corresponding pattern in each of the plurality of first regions partitioning the main surface of the substrate to be exposed, and then the exposure is performed. The upper layer pattern is formed by repeatedly forming the corresponding pattern in each of the plurality of second regions that partition the main surface of the substrate. Therefore, by setting the sizes of the first region and the second region to be equal to one exposure region such as one field of the optical stepper or one subfield of the EPL, the size of the first region and the second region is set to be smaller than that of the one exposure region. A large integrated circuit pattern can be reliably formed on the substrate to be exposed.

Further, according to the first exposure method, each of the plurality of second regions in which each pattern forming the upper layer pattern is formed is the plurality of first regions in which each pattern forming the lower layer pattern is formed. It is provided so as to cross the boundary of. Therefore, even when the upper layer pattern has a pattern that crosses the boundary between the first regions, the pattern can be formed without a connection error, whereby the integrated circuit pattern can be formed with high accuracy.

Further, according to the first exposure method, the size of each first region and each second region can be made variable, so that the degree of freedom in the mask pattern layout design of the integrated circuit is improved.

In the second exposure method according to the present invention, a corresponding pattern is formed by exposure using an electromagnetic wave or a charged particle beam in each of the plurality of first regions that partition the main surface of the substrate to be exposed. By repeating the process of forming a lower layer pattern on the substrate to be exposed, and exposing the corresponding pattern to each of the plurality of second regions partitioning the main surface of the substrate to be exposed using electromagnetic waves or charged particle beams. And a step of forming an upper layer pattern on the exposed substrate so as to overlap the lower layer pattern, the plurality of first regions have a predetermined shape and the shape is repeated. The plurality of second regions are arranged two-dimensionally as a cycle, and the plurality of second regions have the same shape as the plurality of first regions, and the shape is repeated as a repeating period to arrange the plurality of first regions. It is two-dimensionally arranged so as to be offset by a predetermined distance with respect to.

According to the second exposure method, the lower layer pattern is formed by repeating the formation of the corresponding pattern in each of the plurality of first regions partitioning the main surface of the substrate to be exposed, and then the exposure is performed. The upper layer pattern is formed by repeatedly forming the corresponding pattern in each of the plurality of second regions that partition the main surface of the substrate. Therefore, by setting the sizes of the first region and the second region to be equal to one exposure region such as one field of the optical stepper or one subfield of the EPL, the size of the first region and the second region is set to be smaller than that of the one exposure region. A large integrated circuit pattern can be reliably formed on the substrate to be exposed.

Further, according to the second exposure method, the plurality of second regions in which the respective patterns forming the upper layer pattern are formed are the same as the plurality of first regions in which the respective patterns forming the lower layer pattern are formed. The first regions are arranged so that they are displaced from each other by a predetermined distance in a cycle. Therefore, even when the upper layer pattern has a pattern that crosses the boundary between the first regions, the pattern can be formed without a connection error, whereby the integrated circuit pattern can be formed with high accuracy.

Further, according to the second exposure method, the first region and the second region have a predetermined shape and are two-dimensionally arranged with the shape as a repeating period. For this reason,
It becomes easy to perform exposure by using the first region and the second region as one field of the optical stepper or one subfield of the EPL.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) A semiconductor integrated circuit device according to a first embodiment of the present invention and an exposure method used for manufacturing the same will be described below with reference to the drawings. . The semiconductor integrated circuit device according to the first embodiment has a plurality of semiconductor elements formed on the substrate.

FIG. 1 is an enlarged plan view of a part of a semiconductor integrated circuit device (hereinafter sometimes simply referred to as a device) according to the first embodiment.

As shown in FIG. 1, the main surface of the substrate 10 has a predetermined shape such as a rectangle, and a plurality of element arrangement regions 11 arranged two-dimensionally with the shape as a repeating cycle.
It is divided by (region surrounded by a broken line), has the same shape as each element placement area 11, and is shifted by a predetermined distance from the array of the element placement areas 11 with the shape being a repeating cycle. It is partitioned by a plurality of wiring arrangement areas 12 (areas surrounded by thick solid lines) arranged two-dimensionally. Specifically, in the first embodiment, the arrangement of the wiring arrangement areas 12 is half the repetition cycle of the element arrangement area 11 (same as the repetition cycle of the wiring arrangement area 12) with respect to the arrangement of the element arrangement areas 11. It is off by the distance.

Further, as shown in FIG. 1, inside each element placement region 11, a functional block 13 which is a basic element circuit such as a logic gate is placed. In other words, the functional blocks 13 are arranged so as not to cross the boundaries between the element arrangement regions 11. Each functional block 13 includes an element group including at least one semiconductor element among a plurality of semiconductor elements (not shown) formed on the substrate 10 and local wiring (connecting semiconductor elements in the element group). (Not shown).

Specifically, the first element disposition region 11a, the second element disposition region 11b, the third element disposition region 11c, and the fourth element disposition region 11d, which are adjacent to each other, are respectively provided with the first The functional block 13a, the second functional block 13b, the third functional block 13c, and the fourth functional block 13d are arranged. When, for example, a MOS (metal oxide film semiconductor) type transistor is used as the semiconductor element, each functional block 13 includes the substrate 1
It has at least one MOS type transistor element including an active region formed of n-type and p-type diffusion region layers formed in 0 and a gate electrode formed on the active region. At this time, each functional block 13 may have a resistance element formed in the active region, a capacitance element formed of the active region and a gate electrode, a diode element formed of a pn junction, or the like. Good.

Further, each local wiring is formed on an interlayer insulating film (not shown) on the substrate 10 on which the semiconductor elements are formed, and the semiconductor elements are connected to each other via the contacts provided on the interlayer insulating film. Connect. However, when all the local wirings of the device cannot be provided in only one wiring layer, the laminated structure of the interlayer insulating film and the wiring layer is repeated until all the local wirings can be arranged. At this time, each local wiring is arranged inside each element arrangement region 11 in all wiring layers for local wiring. Since the local wiring is a wiring for connecting semiconductor elements provided in an extremely narrow area, there is no reduction in the degree of freedom in circuit design due to arranging each local wiring inside each element arrangement area 11. rare.

Further, as shown in FIG. 1, inside each wiring arrangement area 12, global wirings 14 for connecting the functional blocks 13 provided in a pair of adjacent element arrangement areas 11 are arranged. In other words, the global wirings 14 are arranged so as not to cross the boundary between the wiring arrangement areas 12. Specifically, each global wiring 14 is an interlayer insulating film (not shown) on the substrate 10 on which the functional block 13 (semiconductor element and local wiring) is formed.
The functional blocks 13 are connected to each other through the contacts provided on the interlayer insulating film. However, when all the global wirings 14 of the device cannot be provided in only one wiring layer, the laminated structure of the interlayer insulating film and the wiring layer is repeated until all the global wirings 14 can be arranged. At this time, each global wiring 14 is arranged inside each wiring arrangement area 12 in all wiring layers for global wiring.

The exposure method according to the first embodiment, specifically, the exposure method used for manufacturing the semiconductor integrated circuit device shown in FIG. 1 will be described below using an EPL as an example.

First, the size (all the same size) of each element arrangement area 11 and each wiring arrangement area 12 is set to a size equal to or smaller than the maximum subfield size of EPL. As a result, exposure can be performed with each element arrangement area 11 and each wiring arrangement area 12 as one subfield. The maximum subfield size in the EPL currently under development is about 250 μm □.

Next, the functional block 1 corresponding to each of the plurality of element disposition areas 11 partitioning the main surface of the substrate 10 is formed.
The gate electrode pattern of the entire device is formed on the substrate 10 by repeating the formation of the pattern constituting the element group of the third group, for example, the gate electrode pattern by the exposure using the electron beam. At this time, since each element group is provided inside each element placement region 11, the gate electrode pattern can be formed without a connection error.

Next, the local wiring pattern of the corresponding functional block 13 is repeatedly formed in each of the plurality of element arrangement regions 11 by exposure using an electron beam, and the entire device is formed on the substrate 10. Forming a local wiring pattern. At this time, since each local wiring is provided inside each element placement region 11, the local wiring pattern can be formed without a connection error.

Next, by repeatedly forming the pattern of the corresponding global wiring 14 in each of the plurality of wiring arrangement regions 12 that partition the main surface of the substrate 10 by exposure using an electron beam, the substrate 10 is formed. A pattern of the global wiring 14 of the entire device is formed on the top. At this time, each global wiring 14 is placed inside each wiring placement area 12.
Since the pattern is provided, the pattern of the global wiring 14 can be formed without a connection error.

As described above, according to the semiconductor integrated circuit device of the first embodiment, the functional block 1 is provided inside each element placement region 11 that partitions the main surface of the substrate 10.
3, that is, the element group and the local wiring are arranged.
Therefore, the size of each element placement region 11 is set to 1 of EPL.
By setting the size to be equal to or smaller than the size of the subfield, the element group and the local wiring can be formed in each element placement region 11 without a connection error. As a result, it is possible to prevent the fluctuation or deterioration of the element characteristics due to the connection error. Further, it is possible to prevent disconnection or the like in the local wiring due to electromigration or stress migration due to a connection error. Therefore, the performance and reliability of the device can be prevented from being deteriorated.

In addition, according to the semiconductor integrated circuit device of the first embodiment, the main surface of the substrate 10 is partitioned and only a predetermined distance from the arrangement of the element arrangement regions 11 is repeated at the same repetition period as the element arrangement regions 11. Global wirings 14 that connect the functional blocks 13 provided in the pair of adjacent element placement areas 11 are placed inside the respective wiring placement areas 12 that are arranged so as to be offset from each other. Therefore, by setting the size of each wiring arrangement region 12 to be equal to or smaller than the size of one subfield of the EPL, the global wiring 14 that crosses the boundary between the element arrangement regions 11 can be formed without a connection error. Therefore, the functional blocks 13 can be connected to each other over a large area without lowering the reliability of the global wiring 14, thereby realizing a device having a large chip area.

Further, according to the semiconductor integrated circuit device of the first embodiment, the element arrangement area 11 and the wiring arrangement area 1
2 has a predetermined shape and is two-dimensionally arranged with the shape as a repeating period. Therefore, it becomes easy to perform exposure by using the element arrangement area 11 and the wiring arrangement area 12 as one subfield of the EPL.

Further, according to the exposure method according to the first embodiment, a plurality of element arrangement regions 1 that partition the main surface of the substrate 10 are formed.
The gate electrode pattern or the local wiring pattern or the like of the corresponding functional block 13 is repeatedly formed on each of 1 to form the gate electrode pattern or the local wiring pattern or the like of the entire device, and then the main substrate 10 is formed. The pattern of the global wiring 14 corresponding to the entire device is formed by repeating the formation of the pattern of the corresponding global wiring 14 in each of the plurality of wiring arrangement regions 12 that partition the surface. Therefore, by setting the sizes of the element arrangement area 11 and the wiring arrangement area 12 to the same size as one subfield of the EPL,
An integrated circuit pattern larger than the one subfield can be reliably formed on the substrate 10.

Further, according to the exposure method of the first embodiment, the plurality of wiring arrangement regions 12 in which the patterns of the global wirings 14 are formed have a plurality of areas in which the respective gate electrode patterns or the local wiring patterns are formed. The element arrangement regions 11 are arranged so as to be displaced by a predetermined distance with respect to the arrangement of the element arrangement regions 11 at the same repetition period. Therefore, even when the pattern of the global wiring 14 crosses the boundary between the element arrangement regions 11, the pattern can be formed without a connection error, and thus the integrated circuit pattern can be formed with high accuracy.

In the semiconductor integrated circuit device according to the first embodiment, the local wiring is formed inside the element arrangement area 11 and the global wiring 14 is formed inside the wiring arrangement area 12. Alternatively, the local wiring may be formed so as to cross the boundary between the element placement regions 11 or the global wiring 1 may be formed.
4 may be formed so as to cross the boundary between the wiring arrangement regions 12. This is because the wiring layer of the semiconductor integrated circuit device has a multi-layered structure, and the wiring width used for the wiring layer becomes thicker as it becomes an upper layer, so that a wiring width that is thick enough to ignore a connection error is used. This is because the reliability of the wiring layer does not deteriorate even if the local wiring or the global wiring 14 is not formed inside the element arrangement area 11 or the wiring arrangement area 12. Further, when the local wiring is formed so as to cross the boundary between the element arrangement areas 11 or the global wiring 14 is formed so as to cross the boundary between the wiring arrangement areas 12, the integrated circuit The degree of freedom in mask pattern layout design is improved.

Further, in the semiconductor integrated circuit device according to the first embodiment, the boundary between the element arrangement regions 11 or the boundary between the wiring arrangement regions 12 may have a predetermined width.

Further, in the semiconductor integrated circuit device according to the first embodiment, the arrangement of the wiring arrangement regions 12 is such that the arrangement period of the element arrangement regions 11 is different from that of the element arrangement regions 11 (the repetition period of the wiring arrangement regions 12). It is preferable to deviate by a half distance of the same). By doing so, the global wiring 14 can be formed so as to extend in the same length in each of the pair of adjacent element arrangement regions 11, so that the degree of freedom in the mask pattern layout design of the integrated circuit is improved.

Further, in the semiconductor integrated circuit device according to the first embodiment, the functional blocks 13 (semiconductor elements and local wiring) are not necessarily provided in all the element disposition regions 11.
And it is not always necessary to arrange the global wiring 14 inside all the wiring arrangement regions 12.

Although the EPL is used in the exposure method according to the first embodiment, an optical stepper may be used instead of the EPL. In this case, by setting the size of each element arrangement area 11 and each wiring arrangement area 12 to be equal to or smaller than the maximum field size of the optical stepper,
Exposure can be performed with each element arrangement area 11 and each wiring arrangement area 12 as one field.

(Modification of First Embodiment) A semiconductor integrated circuit device according to a modification of the first embodiment of the present invention and an exposure method used for manufacturing the same will be described below.
A description will be given with reference to the drawings. The semiconductor integrated circuit device according to the modification of the first embodiment has a plurality of semiconductor elements formed on the substrate.

FIG. 2 is an enlarged plan view of a part of a semiconductor integrated circuit device (hereinafter, may be simply referred to as a device) according to a modification of the first embodiment.

As shown in FIG. 2, the main surface of the substrate 10 is partitioned by a plurality of element disposition regions 11 (regions surrounded by broken lines), and crosses the boundary between the element disposition regions 11. A plurality of wiring arrangement areas 12 provided
It is partitioned by (area surrounded by a thick solid line).
That is, in the modified example of the first embodiment, the shape of each element placement region 11 and each wiring placement region 12 is variable, unlike the first embodiment.

Further, as shown in FIG. 2, as in the first embodiment, inside each element placement area 11, a functional block 13 composed of an element group and local wiring is placed. Specifically, the first functional block is provided inside each of the first element placement area 11a, the second element placement area 11b, the third element placement area 11c, and the fourth element placement area 11d which are adjacent to each other. 13a, a second functional block 13b, a third functional block 13c and a fourth functional block 13d are arranged.

Further, as shown in FIG. 2, as in the first embodiment, inside each wiring arrangement area 12, the functional block 13 provided in a pair of adjacent element arrangement areas 11 is provided.
Global wirings 14 that connect the two are arranged.

The exposure method according to the modification of the first embodiment, specifically, the exposure method used for manufacturing the semiconductor integrated circuit device shown in FIG. 2 will be described below using an EPL as an example. To do.

First, the size of each element placement area 11 and each wiring placement area 12 is set to a size equal to or smaller than the maximum subfield size of the EPL. As a result, exposure can be performed with each element arrangement area 11 and each wiring arrangement area 12 as one subfield.

Next, the functional block 1 corresponding to each of the plurality of element disposition areas 11 partitioning the main surface of the substrate 10 is formed.
The gate electrode pattern of the entire device is formed on the substrate 10 by repeating the formation of the pattern constituting the element group of the third group, for example, the gate electrode pattern by the exposure using the electron beam. At this time, since each element group is provided inside each element placement region 11, the gate electrode pattern can be formed without a connection error.

Next, by repeatedly forming the local wiring pattern of the corresponding functional block 13 by exposure using an electron beam in each of the plurality of element arrangement regions 11, the entire device is formed on the substrate 10. Forming a local wiring pattern. At this time, since each local wiring is provided inside each element placement region 11, the local wiring pattern can be formed without a connection error.

Next, by repeatedly forming the pattern of the corresponding global wiring 14 in each of the plurality of wiring arrangement regions 12 that partition the main surface of the substrate 10 by exposure using an electron beam, the substrate 10 is formed. A pattern of the global wiring 14 of the entire device is formed on the top. At this time, each global wiring 14 is placed inside each wiring placement area 12.
Since the pattern is provided, the pattern of the global wiring 14 can be formed without a connection error.

As described above, according to the semiconductor integrated circuit device of the modified example of the first embodiment, the functional block 13, that is, the element, is provided inside each element disposition region 11 partitioning the main surface of the substrate 10. Group and local wiring are arranged. Therefore, the size of each element placement region 11 is set to be EP
By setting the size to one subfield of L or less, the element group and the local wiring can be formed in each element placement region 11 without a connection error. As a result, it is possible to prevent the fluctuation or deterioration of the element characteristics due to the connection error. Also,
It is possible to prevent disconnection or the like in the local wiring due to electromigration or stress migration due to a connection error. Therefore, the performance and reliability of the device can be prevented from being deteriorated.

Further, according to the semiconductor integrated circuit device of the modified example of the first embodiment, inside the wiring arrangement regions 12 that partition the main surface of the substrate 10 and cross the boundary between the element arrangement regions 11, Global wirings 14 that connect the functional blocks 13 provided in the pair of adjacent element arrangement regions 11 are arranged. Therefore, by setting the size of each wiring arrangement region 12 to be equal to or smaller than the size of one subfield of the EPL, the global wiring 14 that crosses the boundary between the element arrangement regions 11 can be formed without a connection error. Therefore, the functional blocks 13 can be connected to each other over a large area without lowering the reliability of the global wiring 14, thereby realizing a device having a large chip area.

Further, according to the semiconductor integrated circuit device of the modification of the first embodiment, the size of each element placement area 11 and each wiring placement area 12 can be made variable, so that the mask pattern layout design of the integrated circuit can be performed. The degree of freedom is improved.

Further, according to the exposure method of the modification of the first embodiment, the gate electrode pattern of the functional block 13 corresponding to each of the plurality of element disposition regions 11 partitioning the main surface of the substrate 10 or After forming the gate electrode pattern or the local wiring pattern of the entire device by repeating the formation of the local wiring pattern and the like, a plurality of wiring arrangement regions 12 that partition the main surface of the substrate 10 are formed.
The pattern of the global wiring 14 corresponding to each of the above is repeated to form the pattern of the global wiring 14 of the entire device. Therefore, by setting the sizes of the element placement area 11 and the wiring placement area 12 to the same size as one subfield of the EPL, an integrated circuit pattern larger than the one subfield is surely formed on the substrate 10. Can be formed into

Further, according to the exposure method according to the modification of the first embodiment, each of the plurality of wiring arrangement regions 12 in which the pattern of each global wiring 14 is formed has each gate electrode pattern or each local wiring pattern. It is provided so as to cross the boundary between the plurality of formed element arrangement regions 11. Therefore, even when the pattern of the global wiring 14 crosses the boundary between the element placement regions 11,
The pattern can be formed without a connection error, whereby the integrated circuit pattern can be formed with high accuracy.

In the semiconductor integrated circuit device according to the modification of the first embodiment, the local wiring is the element placement region 1
1 and the global wiring 14 is formed inside the wiring arrangement area 12, but instead of this, local wiring is formed so as to cross the boundary between the element arrangement areas 11. Alternatively, the global wiring 14 may be formed so as to cross the boundary between the wiring arrangement areas 12. This is because the wiring layer of the semiconductor integrated circuit device has a multi-layered structure, and the wiring width used for the wiring layer becomes thicker as it becomes an upper layer, so that a wiring width that is thick enough to ignore a connection error is used. This is because the reliability of the wiring layer does not deteriorate even if the local wiring or the global wiring 14 is not formed inside the element arrangement area 11 or the wiring arrangement area 12. Further, when the local wiring is formed so as to cross the boundary between the element arrangement areas 11 or the global wiring 14 is formed so as to cross the boundary between the wiring arrangement areas 12, the integrated circuit The degree of freedom in mask pattern layout design is improved.

In the semiconductor integrated circuit device according to the modification of the first embodiment, the boundary between the element arrangement regions 11 or the boundary between the wiring arrangement regions 12 may have a predetermined width.

Further, in the semiconductor integrated circuit device according to the modification of the first embodiment, it is not always necessary to arrange the functional blocks 13 (semiconductor elements and local wirings) inside all the element arrangement regions 11, and it is not always necessary. It is not necessary to arrange the global wiring 14 inside all the wiring arrangement areas 12.

Although the EPL is used in the exposure method according to the modification of the first embodiment, an optical stepper may be used instead of the EPL. In this case, by setting the size of each element placement area 11 and each wiring placement area 12 to be equal to or smaller than the maximum field size of the optical stepper, each of the element placement area 11 and each wiring placement area 12 is set to one field. Can be exposed as.

(Second Embodiment) A semiconductor integrated circuit device according to a second embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is an enlarged plan view of a part of the semiconductor integrated circuit device according to the second embodiment. The semiconductor integrated circuit device according to the second embodiment is obtained by improving one element placement region 11 in the semiconductor integrated circuit device according to the first embodiment shown in FIG.
The same members as those of the first embodiment shown in FIG.

The difference of the second embodiment from the first embodiment is that, as shown in FIG.
That is, the wiring connection terminal 21 that crosses the boundary between the wiring arrangement regions 12 is arranged inside one of the element arrangement regions 11 of 1. Specifically, one element placement area 11 is divided into four small areas by the boundary between four adjacent wiring placement areas 12 (only a part of each wiring placement area 12 is shown in FIG. 3). In addition, the conductive wiring connection terminal 21 is formed so as to cross the boundary between the wiring arrangement areas 12 and to span two small areas. The wiring connection terminal 21 is formed, for example, in a wiring layer for local wiring. However, the wiring connection terminal 21 is not connected to the semiconductor element and the local wiring.

By the way, in the first embodiment, the functional block 13 (see FIG. 1) is arranged inside each element arrangement region 11, but in the second embodiment,
The first sub-block 22a, the second sub-block 22b, the third sub-block 22c and the fourth sub-block 22b that form the functional block 13 are provided inside the four small regions that form one element placement region 11 shown in FIG. Sub-blocks 22d are arranged respectively. At this time, a wiring (not shown) that connects the sub blocks 22 to each other is formed in a region between the wiring connection terminals 21.

Further, as shown in FIG. 3, the wiring connection terminal 21 has the first contacts 23a provided at both ends thereof.
Also, the first global wiring 14a and the second global wiring 14b arranged inside the pair of adjacent wiring arrangement regions 12 are electrically connected to each other via the second contact 23b. As a result, the global wiring 14 is extended so as to substantially cross the boundary between the wiring arrangement areas 12.

According to the second embodiment, the following effects can be obtained in addition to the effects of the first embodiment.

That is, in the first embodiment, since the global wirings 14 are arranged so as not to cross the boundary between the wiring arrangement areas 12, the global wirings 1 are arranged.
4 cannot be extended beyond the boundary between the wiring arrangement areas 12, so that the degree of freedom in the mask pattern layout design of the integrated circuit is limited. On the other hand, in the second embodiment, since the wiring connection terminal 21 that crosses the boundary between the wiring arrangement regions 12 is arranged inside the element arrangement region 11, the wiring connection terminal 21 The global wirings 14 arranged in the pair of wiring arrangement areas 12 adjacent to each other can be relayed. For this reason, the global wiring 14 can be formed substantially over the three or more element placement regions 11, so that the degree of freedom in the mask pattern layout design of the integrated circuit is improved.

In the second embodiment, the sub-blocks 22 are respectively provided inside the four small areas formed by dividing the element placement area 11 by the boundaries between the wiring placement areas 12.
Was placed, but instead of this, 4 sub-blocks
It may be arranged so as to straddle two or more small areas of one small area.

(Modification of Second Embodiment) A semiconductor integrated circuit device according to a second embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is an enlarged plan view of a part of the semiconductor integrated circuit device according to the modification of the second embodiment. still,
The semiconductor integrated circuit device according to the modification of the second embodiment is
This is a modification of one element placement region 11 in the semiconductor integrated circuit device according to the modification of the first embodiment shown in FIG. 2, and is the same as the modification of the first embodiment shown in FIG. 2 in FIG. The description of the members will be omitted by attaching the same reference numerals.

The modification of the second embodiment is different from the modification of the first embodiment in that, as shown in FIG. That is, the wiring connection terminals 21 are arranged inside the wiring arrangement regions 12 so as to cross the boundaries between the wiring arrangement regions 12. In particular,
One element placement area 11 is divided into four small areas by the boundary between four adjacent wiring placement areas 12 (only a part of each wiring placement area 12 is shown in FIG. 4), and 2 across the boundary between the placement areas 12
Conductive wiring connection terminal 2 to span two small areas
1 is formed. The wiring connection terminal 21 is formed, for example, in a wiring layer for local wiring. However, the wiring connection terminal 21 is not connected to the semiconductor element and the local wiring.

By the way, in the modification of the first embodiment, the functional block 13 is provided inside each element placement region 11.
(See FIG. 2) is arranged, but in the modified example of the second embodiment, the functional block 13 is formed inside the four small regions forming the one element arrangement region 11 shown in FIG. First sub-block 22a, second sub-block 2
2b, a third sub block 22c and a fourth sub block 22d are arranged respectively. At this time, a wiring (not shown) that connects the sub blocks 22 to each other is formed in a region between the wiring connection terminals 21.

Further, as shown in FIG. 4, the wiring connecting terminal 21 has the first contacts 23a provided at both ends thereof.
Also, the first global wiring 14a and the second global wiring 14b arranged inside the pair of adjacent wiring arrangement regions 12 are electrically connected via the second contact 23b. As a result, the global wiring 14 is extended so as to substantially cross the boundary between the wiring arrangement areas 12.

According to the modification of the second embodiment, the following effects can be obtained in addition to the effects of the modification of the first embodiment.

That is, in the modification of the first embodiment, since the global wirings 14 are arranged so as not to cross the boundary between the wiring arrangement areas 12, the global wirings 14 are arranged at the boundaries between the wiring arrangement areas 12. Since it cannot be extended beyond, the degree of freedom in mask pattern layout design of the integrated circuit is limited. On the other hand, in the modified example of the second embodiment, since the wiring connection terminals 21 that cross the boundary between the wiring arrangement areas 12 are arranged inside the element arrangement area 11, the wiring connection terminals are formed. By 21, the global wirings 14 arranged in the pair of wiring arrangement areas 12 adjacent to each other can be relayed. For this reason, the global wiring 14 can be formed substantially over the three or more element placement regions 11, so that the degree of freedom in the mask pattern layout design of the integrated circuit is improved.

In the modification of the second embodiment, the sub-blocks 22 are arranged inside the four small areas formed by dividing the element arrangement area 11 by the boundaries between the wiring arrangement areas 12. The number (plurality) of small areas obtained by dividing the element placement area 11 is not particularly limited. In addition, the sub-block is 2 of the plurality of small areas.
It may be arranged so as to extend over one or more small areas.

[0098]

According to the present invention, the size of the element placement area and the wiring placement area that partition the main surface of the substrate is set to be equal to or less than the size of one field of the optical stepper or one subfield of the EPL. As a result, the element group and the local wiring can be formed in the element arrangement region without a connection error, and the global wiring crossing the boundary between the element arrangement regions can be formed without a connection error. Therefore, it is possible to prevent the fluctuation or deterioration of the element characteristics or the disconnection of the wiring due to the connection error, so that the deterioration of the performance and reliability of the semiconductor integrated circuit device can be prevented. Further, the element groups, that is, the functional blocks can be connected to each other over a large area without reducing the reliability of the global wiring, thereby realizing a semiconductor integrated circuit device having a large chip area.

[Brief description of drawings]

FIG. 1 is a partially enlarged plan view of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a partially enlarged plan view of a semiconductor integrated circuit device according to a modification of the first embodiment of the present invention.

FIG. 3 is a partially enlarged plan view of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 4 is a partially enlarged plan view of a semiconductor integrated circuit device according to a modification of the second embodiment of the present invention.

FIG. 5 is an enlarged plan view of a part of a conventional semiconductor integrated circuit device.

6 (a) to 6 (c) are diagrams showing a connection error occurring at a joint between patterns in a conventional semiconductor integrated circuit device.

[Explanation of symbols]

10 substrates 11 element placement area 11a First element arrangement region 11b Second element placement region 11c Third element placement region 11d Fourth element arrangement region 12 Wiring placement area 13 functional blocks 13a First functional block 13b Second functional block 13c Third functional block 13d Fourth functional block 14 Global wiring 14a First global wiring 14b Second global wiring 21 Wiring connection terminal 22 sub-blocks 22a First sub-block 22b Second sub-block 22c Third sub-block 22d Fourth sub-block 23a First contact 23b Second contact

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Claims (13)

(57) [Claims] 1. A semiconductor integrated circuit device having a plurality of semiconductor elements formed on a substrate, wherein a main surface of the substrate is partitioned by a plurality of element placement regions arranged two-dimensionally . Crossing the boundary between the plurality of element placement areas and the plurality of element placement areas
Two-dimensionally so that it is displaced by a predetermined distance from the array of
It is partitioned by a plurality of arranged wiring arrangement regions, and inside the plurality of element arrangement regions, an element group including at least one semiconductor element of the plurality of semiconductor elements, and The local wiring connecting the semiconductor elements crosses the boundary between the plurality of element arrangement regions.
Are arranged so that there is no local wiring inside the plurality of wiring arrangement areas.
On the upper side of the line, the global wiring connecting the element groups does not cross the boundary between the plurality of wiring arrangement areas.
A semiconductor integrated circuit device characterized by being arranged in such a manner. 2. The plurality of element arrangement regions and the plurality of element arrangement regions
Wires each arrangement region, a semiconductor integrated circuit device according to claim 1, characterized in that are two-dimensionally arranged as periodically repeated and the shape has a predetermined shape. 3. The predetermined distance is equal to the plurality of element arrangements.
3. The semiconductor integrated circuit device according to claim 2, wherein the distance is half the repetition period in the array of regions . 4. The plurality of element placement regions and the plurality of element placement regions
Each of the wiring placement areas must have the same shape
The semiconductor integrated circuit device according to claim 1. 5. The plurality of element arrangement regions and the plurality of element arrangement regions
The size of each wiring arrangement area is determined by one exposure.
Equal to or larger than the pattern transferable size
2. The semiconductor integrated device according to claim 1, wherein
Circuit device. 6. A wiring connection terminal that crosses a boundary between the plurality of wiring arrangement areas is arranged inside at least one element arrangement area of the plurality of element arrangement areas. The semiconductor integrated circuit device according to claim 1 . 7. A plurality of semiconductor elements formed on a substrate
A method of manufacturing a semiconductor integrated circuit device, comprising: a plurality of element arrays arranged two-dimensionally on the main surface of the substrate.
Inside the storage area, at least one of the plurality of semiconductor elements is
And a pattern of an element group consisting of one semiconductor element,
The local wiring pattern that connects the semiconductor elements in the element group
Crosses the turn and the boundary between the multiple element placement areas
And a step of forming by exposure so as not to cross the boundary between the plurality of element arrangement regions and
Deviates by a specified distance from the array of several element placement areas
A plurality of two-dimensionally arranged on the main surface of the substrate.
Above the local wiring inside the wiring arrangement area
A global wiring pattern that connects the device groups to each other.
Does not cross the boundary between the plurality of wiring placement areas.
And the step of forming by exposure.
A method for manufacturing a semiconductor integrated circuit device. 8. The plurality of element arrangement regions and the plurality of element arrangement regions
Each of the wiring placement areas has a predetermined shape and
Are arranged two-dimensionally with the shape as a repeating cycle
A semiconductor integrated circuit device according to claim 7, characterized in that
Build method. 9. The predetermined distance is equal to the plurality of element arrangements.
A distance that is half of the repetition period in the array of regions
9. The semiconductor integrated circuit device according to claim 8, wherein
Manufacturing method. 10. The plurality of element placement regions and the plurality of element placement regions
Each of the wiring placement areas must have the same shape.
The semiconductor integrated circuit device according to claim 7,
Production method. 11. The plurality of element arrangement regions and the plurality of element arrangement regions
The size of each wiring placement area of
The size is equal to or larger than the pattern transfer
The semiconductor collection according to claim 7, which is smaller than
Method for manufacturing integrated circuit device. 12. The device group and the local wiring are arranged.
The process of forming each pattern includes
Inside at least one element placement area of the placement area
Wiring that crosses the boundary between the plurality of wiring placement areas
Comprising the step of forming by exposure the patterns of the connection terminals
8. The semiconductor integrated circuit device according to claim 7, wherein
Manufacturing method. 13. The device group and the local wiring are arranged.
The process of forming each pattern and the global
In the process of forming the wiring pattern, electromagnetic waves or load
A contract characterized by performing exposure using an electron particle beam
A method for manufacturing a semiconductor integrated circuit device according to claim 7.