JP3533124B2 - Arithmetic processing chip and power consumption control method in arithmetic processing chip - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power consumption control technique in an arithmetic processing chip provided with arithmetic processing means for performing a predetermined arithmetic processing.

[0002]

2. Description of the Related Art In a large computer system or the like, as shown in FIG. 7, an arithmetic processing chip 710a having an arithmetic processing unit (not shown) for performing a predetermined arithmetic processing,
, 710n are arranged on the circuit board 700, and a plurality of such circuit boards 700 are mounted, so that complicated calculations are performed in a short time. Each circuit board 700 is normally connected to a power source (not shown) by a harness so that power is supplied to the arithmetic processing chips 710a, ..., 710n.

By the way, arithmetic processing is executed by an arithmetic processing unit (not shown), and such an arithmetic processing chip 710 is used.
If a time change amount of the power consumption occurs in a, ..., 710n, the change amount may be mixed into the arithmetic processing unit as noise and cause a malfunction. Therefore, a normal electric field capacitor or the like is provided on the circuit board 700. It was arranged appropriately to take measures against noise.

However, in such noise countermeasures, there are problems that the cost increases due to the arrangement of the electrolytic capacitors and that the circuit dimensions increase due to the size of the electrolytic capacitors. there were.

The present invention has been made in order to solve such a conventional problem, and an arithmetic processing chip and a consumption chip in which an amount of change in power consumption is reduced without causing the above-mentioned problems. It is an object to provide a power control method.

In order to achieve the above object, the invention according to claim 1 of the present invention is an arithmetic processing chip provided with arithmetic processing means for performing a predetermined arithmetic processing, wherein the arithmetic processing is performed. When the means consumes power to execute the predetermined arithmetic processing, it does not consume power,
On the other hand, when the arithmetic processing means does not execute the predetermined arithmetic processing and does not consume power , the arithmetic processing means includes power consumption control means that operates to consume power.
The stage is the above when the level reaches either of the two levels.
Calculation control signal which is a signal for instructing execution of constant calculation processing
Depending on the level of the input operation control signal.
The power consumption is configured to perform the predetermined operation.
The force control means inverts the operation control signal with an inverter.
Input the power consumption control signal, which is the signal
The level of the power consumption control signal indicates the execution of the arithmetic processing
Value of the D-type flip-flop
Hold, while at a different level
Changes the value of D-type flip-flop to an odd number of inverters
Therefore, it is configured to be inverted, and the odd-numbered invertor is used.
The performance by adjusting the number of its inverters.
To suppress fluctuations in total power consumption within the arithmetic processing chip
Was so that is configured.

In the invention according to the first aspect, the power consumption control means does not consume power when the arithmetic processing means performs the predetermined arithmetic processing, but the power consumption control means does not consume the power. When the means does not execute the predetermined arithmetic processing and does not consume the power, the means consumes the power. Therefore, the amount of change in power consumption in the arithmetic processing chip is reduced, and as a result, noise generation is suppressed. Also consumption
The power control means inverted the operation control signal with the inverter.
Input the power consumption control signal, which is a signal,
The level of the power consumption control signal indicates the execution of arithmetic processing.
Holds the value of the D flip-flop if it is bell
And does not consume power. On the other hand, a different level
, The value of the D-type flip-flop is
Power consumption is achieved by reversing with an inverter.
In this way, the power consumption change amount in the arithmetic processing chip
To reduce. Therefore, the power consumption control means is controlled.
Input the power consumption control signal for
It can be generated by a simple circuit using an inverter. Furthermore,
The power consumption control means includes a D-type flip-flop and an odd number of stages.
It can be realized with a simple circuit configuration using an inverter. Well
In addition, this D-type flip-flop is
Generally used in large numbers, so when manufacturing arithmetic processing means
Manufactures D-type flip-flops for power consumption control means
The power consumption control means manufacturing process.
You can simplify the process.

[0006]

[0007]

[0008]

[0009]

[0010]

[0011]

According to a second aspect of the present invention, in the arithmetic processing chip according to the first aspect , the arithmetic processing chip has a shape adapted to the arrangement shape of the arithmetic processing means in the chip having a predetermined shape. The power consumption control means is arranged in the chip.

According to the second aspect of the present invention, by disposing the power consumption control means in the chip so as to have a shape that matches the arrangement shape of the arithmetic processing means in the chip having a predetermined shape, The power consumption control means can be arranged in the remaining area in the chip where the arithmetic processing means is arranged. As a result, it is not necessary to provide a special area for the power consumption control means, and it is possible to prevent the circuit scale from increasing.

According to a third aspect of the present invention, there is provided a power consumption control method in an arithmetic processing chip including arithmetic processing means for performing predetermined arithmetic processing, wherein the arithmetic processing means executes the predetermined arithmetic processing. when performing the power consumption in order, without performing the power consumption in the power control unit, on the other hand, if the processing means does not perform the power consumption without performing the predetermined operation processing, the line Align the power consumption in the power consumption control means, said processing means, the two-level
When any of the levels in the above
Input the operation control signal that is a signal to instruct the line
The predetermined calculation is performed according to the level of the calculation control signal applied.
And the power consumption control means outputs the arithmetic control signal.
Input the power consumption control signal which is the signal inverted by the inverter.
The input power consumption control signal level.
If it is a level that instructs execution of arithmetic processing, D-type
It keeps the value of the lip flop, while it has a different
If it is bell, set the value of D flip-flop to an odd number
Inverted by the inverter of the stage
The performance by adjusting the number of its inverters.
To suppress fluctuations in total power consumption within the arithmetic processing chip
A power consumption control method in the arithmetic processing chip, characterized in that configured.

According to the third aspect of the invention, when the arithmetic processing means consumes power to execute a predetermined arithmetic processing, the power consumption control means does not consume power. On the other hand, when the arithmetic processing means does not execute the predetermined arithmetic processing and does not consume the power , the power consumption controlling means performs the power consumption. Therefore, the amount of change in power consumption in the arithmetic processing chip is reduced, and as a result, noise generation is suppressed. Also, power consumption control
The stage is a signal obtained by inverting the operation control signal with an inverter.
Input the power consumption control signal and input this power consumption control
The signal level is the level that instructs the execution of arithmetic processing.
In that case, hold the value of the D-type flip-flop and turn off the power.
Do not pay. On the other hand, if the level is different from this
The value of the D flip-flop is an odd number of inverters
So that it consumes power by inverting
To reduce the amount of power consumption change in the arithmetic processing chip.
It Therefore, the power consumption for controlling the power consumption control means is reduced.
Inverter for inputting power consumption control signal and calculation control signal
It can be generated by a simple circuit using Furthermore, power consumption
A D-type flip-flop and an odd number of inverters
It can be realized with a simple circuit configuration using and. Also, this D
Type flip-flops are generally a large number of arithmetic processing means.
Since it is used, power consumption during manufacturing of the arithmetic processing means
Make a D-type flip-flop for control means
This simplifies the manufacturing process of the power consumption control means.
It can be

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block configuration diagram of an arithmetic processing chip 300 according to an embodiment of the present invention. As shown in FIG. 1, the arithmetic processing chip 300 according to this embodiment.
Includes an arithmetic processing unit 100, a power consumption control unit 200, a clock supply unit 50 that supplies a clock signal to each D-type F / F (hereinafter, a flip-flop is referred to as “F / F”),
An inverter 60 that inverts the arithmetic control signal 400 to generate a power consumption control signal. Each circuit element is composed of CMOS.

The arithmetic processing unit 100 includes selectors 101, 1
02, D-type F / Fs 110 and 111, and an adder 120
And a D-type F / F 130. Selector 10
Reference numerals 1 and 102 respectively take in the data A and the data B when the operation control signal 400 is at the high level, and are D-type F / F 11
0, 111, on the other hand, when the operation control signal 400 is at low level, the values held by the D-type F / Fs 110, 111 are sent to the D-type F / Fs 110, 111, and the arithmetic processing in the arithmetic processing unit 100 is not performed. It is like this. D type F
The / F110 delays and outputs the data from the selector 101 in synchronization with the rising edge of the clock signal supplied from the clock supply unit 50, and similarly, the D-type F / F111 outputs the clock supplied from the clock supply unit 50. The data from the selector 102 is delayed and output in synchronization with the rising edge of the signal. Further, the adder 120 adds the output of the D-type F / F 110 and the output of the D-type F / F 111 and outputs the addition result. The D-type F / F 130 has a clock supply unit 50.
The addition result from the adder 120 is synchronized with the rising edge of the clock signal supplied from the data C (C0, C1,
...) is output as a delay.

The power consumption control unit 200 includes a selector 201.
, D-type F / F 205, and three-stage inverters 210, 2
11 and 213. When the power consumption control signal 401 is at a high level, the selector 201 operates in the inverter 21.
3 output, that is, the output of the D-type F / F 205 is inverted by the odd-numbered inverters,
When the power consumption control signal 401 is at a low level, the value held by the D-type F / F 205 is sent to the D-type F 205.
/ F205, so that the power consumption control unit 200 does not consume power. The D-type F / F 205 delays and outputs the data from the selector 201 in synchronization with the rising edge of the clock signal supplied from the clock supply unit 50.

Next, the operation will be described with reference to FIGS. First, the operation of the arithmetic processing unit 100 will be described with reference to FIGS. When the arithmetic control signal 400 is at high level (FIG. 2B), the selectors 101 and 102
Are data A (A0, A1, ...) And data B (B
0, B1, ...) and D-type F / F 110, 111
Send to. The D-type F / Fs 110 and 111 that input this are
Data A and data B are output in a delayed manner in synchronization with the rising edge of the clock signal (FIG. 2A) (FIG. 2A).
(C), (d)). Then, the adder 120 adds the data A and the data B, and the addition result is the D-type F / F1.
Then, the D type F / F 130 synchronizes this addition result with the data C in synchronization with the rising edge of the clock signal (FIG. 2A).
(FIG. 2 (e)). In this way, when the arithmetic control signal 400 is at the high level, power consumption is performed by executing the arithmetic processing.

On the other hand, when the operation control signal 400 is at the low level (FIG. 2B), the selectors 101 and 102 are
The values held by the D-type F / F 110 and 111 are set to the D-type F / F 1
10 and 111, the values of the D-type F / Fs 110 and 111 remain A5 and B5, respectively, so the arithmetic processing is not executed (FIGS. 2C, 2D, and 2E), and the power consumption is reduced. It is not consumed (Fig. 2 (f)). Then, when the arithmetic control signal 400 becomes high level again, arithmetic processing is executed and power consumption is performed.

Next, the operation of the power consumption control section 200 will be described with reference to FIGS. 2 (a) and 2 (g) to (l). First, when the operation control signal 400 is at the high level, it is brought to the low level by the inverter 60, and the power consumption control signal 401 becomes the low level (FIG. 2 (g)). in this case,
Since the selector 201 sends the value held by the D-type F / F 205 to the D-type F / F 205 as it is, the D-type F / F 205
Keeps the initial value “0” (FIG. 2 (h)) and does not consume power (FIG. 2 (l)).

On the other hand, when the operation control signal 400 is at the low level, this becomes the high level by the inverter 60, and the power consumption control signal 401 becomes the high level (FIG. 2).
(G)). In this case, the selector 201 is the inverter 2
The output of No. 13, that is, the inverted value of the value held by the D-type F / F 205 is sent to the D-type F / F 205. By this, D type F
The / F 205 outputs the inverted value to the inverter 210 with the rising edge of the clock signal as synchronization (FIG. 2A). Then, the inverters 210, 211, and 212 respectively output the inverted outputs of the signals sequentially given with a predetermined delay amount (FIGS. 2 (i) and 2 (j),
(K)), the holding value of the D-type F / F 205 changes alternately (FIG. 2 (h)). When the power consumption control signal 401 goes low (FIG. 2 (g)), the D-type F / F2
The value of 05 remains held (FIG. 2 (h)).

By the way, FIG. 3 shows an example of a CMOS inverter, which includes a P-type MOSFET 600 having one end connected to a power source (Vcc) and an N-type MOSFET having one end connected to a ground potential (gnd). MOSFET 601
When a signal (Vin) that changes from low level to high level is input, the output signal (Vout)
Changes from the power supply voltage level to the low level in response to this (FIGS. 4 (a) and 4 (b)), but at this time, one MOSFET is always in the OFF state, and its power consumption is This is only when the level of the signal (Vout) changes (FIG. 4 (c)).

Therefore, when the power consumption control signal 401 is at a high level, the D-type F / F 205 and the inverter 2
Since the values of 10, 212 and 212 change alternately, power consumption is performed, while when the power consumption control signal 401 is at the low level, power consumption is not performed.

As described above, according to this embodiment, the power consumption control unit 200 includes the arithmetic processing unit 100.
Does not consume power in order to perform addition, power consumption is performed if the arithmetic processing unit 100 does not perform power consumption without performing addition. Therefore, the power consumption in the arithmetic processing chip 300 is as shown by reference numerals 501, 502, and 503 in FIG. 5, and the amount of change in the power consumption in the arithmetic processing chip 300 is smaller than that in the conventional case (shown by the reference numeral 504). I see. As a result, noise generation and the like are suppressed.

When the arithmetic processing unit 100 does not perform power addition without performing addition, the arithmetic processing unit 100 may perform power consumption corresponding to the power consumption for performing addition. For example, the total amount of power consumption in the arithmetic processing chip 300 becomes a constant value, and as a result, there is no change in power consumption, and noise generation is further suppressed. For this purpose, the adjustment may be made by increasing the number of inverters in the power consumption control unit 200. Further, in this embodiment, the power consumption control unit 200 inputs a power consumption control signal 401 which is a signal obtained by inverting the operation control signal 400 by the inverter 60, and the input power consumption control signal 401.
Level that instructs addition execution (low level)
If the level is different from the above, power consumption is not performed. On the other hand, if the level is different from this (high level), the power consumption is reduced to reduce the power consumption change amount. Therefore, the power consumption control signal 401 for controlling the power consumption control unit 200 is set to the calculation control signal 4
It can be generated by a simple circuit using the inverter 60 for inputting 00.

Further, in this embodiment, when the level of the power consumption control signal 401 is a level (low level) instructing the execution of addition, the value of the D-type F / F 202 is held and power consumption is reduced. On the other hand, if the level is different (high level), the value of the D-type F / F 205 is set to three stages (odd stages) of the inverters 210, 211, 21.
The power consumption is changed by reversing by 2 to reduce the power consumption change amount in the arithmetic processing chip 300. Therefore, the power consumption control unit 200
To the D-type F / F 205 and odd-numbered inverters 210, 2
It can be realized with a simple circuit configuration using 11, 213 and the like.
Since many D-type F / Fs are generally used in the arithmetic processing unit 100, the D-type F / F for the power consumption control unit 200 should be manufactured before manufacturing the arithmetic processing unit 100. By doing so, the manufacturing process of the power consumption control unit 200 can be simplified.

Further, by arranging the power consumption control unit 200 in the chip so as to have a shape that matches the arrangement shape of the arithmetic processing unit 100 in the chip having a predetermined shape, the calculation in the chip is performed. The power consumption control unit 200 can be arranged in the remaining area where the processing unit 100 is arranged. As a result, it is not necessary to provide a special area for the power consumption control unit 200, and it is possible to prevent the circuit scale from increasing. In the example shown in FIG. 6, the rectangular arithmetic processing chip 3 is used.
The arithmetic processing unit 100 arranged in 00 has a quadrangular shape as a whole, and the lower right side portion thereof has a horizontally long rectangular shape and is lacking. In this case, the rectangular power consumption control unit 200 has a horizontally long rectangular shape in the rectangular area.
By arranging, the arithmetic processing chip 300 of the present invention can be realized by utilizing the empty area.

Although the embodiments of the present invention have been described above, various modifications and the like can be made to the above embodiments without departing from the gist of the present invention. For example, the number of power consumption control units 200, etc. Needless to say, can be appropriately selected based on the conditions of odd-numbered stages, and the type of arithmetic processing can be subtraction or multiplication other than addition.

As described above, according to the present invention, when the arithmetic processing means consumes electric power to execute a predetermined arithmetic processing, the arithmetic processing means does not consume the electric power, while the arithmetic processing means. Since the power consumption is performed when the power consumption is not performed without executing the predetermined calculation processing, the power consumption change amount in the calculation processing chip is reduced, and as a result, the occurrence of noise is suppressed. The effect is obtained.

In particular, when the power consumption control means for performing the power consumption control operation is realized by a simple circuit configuration using a D type F / F and an odd number of stages of inverters, the arithmetic processing means generally also Since many D-type F / Fs are used,
If the D-type F / F for the power consumption controlling means is manufactured at the time of manufacturing the arithmetic processing means, an effect that the manufacturing process of the power consumption controlling means can be simplified can be obtained. To be

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an arithmetic processing chip 300 according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the arithmetic processing chip 300.

FIG. 3 is a configuration diagram of a CMOS circuit.

FIG. 4 is an explanatory diagram of power consumption of a CMOS circuit.

FIG. 5 is an explanatory diagram of effects of the embodiment of the present invention.

6 is an explanatory diagram of a layout example of the arithmetic processing unit 100 and the power consumption control unit 200. FIG.

FIG. 7 is a schematic explanatory view of a conventional technique.

[Explanation of symbols]

50 clock supply unit 60 inverter 100 arithmetic processing unit 101 selector 102 selector 110 D type F / F 111 D type F / F 120 adder 130 D type F / F 200 Power consumption controller 201 selector 210 inverter 211 inverter 212 inverter 300 arithmetic processing chip 400 arithmetic control signal 401 Power consumption control signal 600 P-type MOSFET 601 N-type MOSFET

Claims (3)

(57) [Claims] 1. An arithmetic processing chip comprising arithmetic processing means for performing a predetermined arithmetic processing, wherein when the arithmetic processing means consumes power to execute the predetermined arithmetic processing, no power consumption is performed. On the other hand, when the arithmetic processing means does not perform power consumption without executing the predetermined arithmetic processing, the arithmetic processing means includes power consumption control means that operates to consume power , and the arithmetic processing means has two levels. When one of the levels becomes
Input a calculation control signal that is a signal to instruct execution of arithmetic processing
Depending on the level of this input operation control signal,
The power consumption control means is a signal obtained by inverting the operation control signal by an inverter.
Input the power consumption control signal and input this power consumption control signal.
Is the level that instructs the execution of the arithmetic processing.
If the value of the D-type flip-flop is held,
On the other hand, if the level is different from this,
Invert the flip-flop value by an odd number of inverters
The odd-numbered inverters are configured to adjust the number of the inverters.
The total amount of power consumption in the arithmetic processing chip
An arithmetic processing chip that is configured to suppress the fluctuation amount of . 2. The arithmetic processing chip according to claim 1, wherein an arrangement shape of the arithmetic processing means in a chip having a predetermined shape is adopted.
The power consumption control having a conforming shape
An arithmetic processing chip, characterized in that the means is arranged in the chip. 3. An arithmetic processing means for performing a predetermined arithmetic processing.
A method for controlling power consumption in a provided arithmetic processing chip , wherein the arithmetic processing means executes the predetermined arithmetic processing.
Power consumption by the power consumption control means.
Power consumption is not performed, while the arithmetic processing unit
If you do not perform power calculation without executing
The power consumption control means performs power consumption, and the arithmetic processing means inputs an arithmetic control signal which is a signal for instructing execution of the predetermined arithmetic processing at any one of two levels. The predetermined operation is executed according to the level of the input operation control signal, and the power consumption control unit inputs a power consumption control signal which is a signal obtained by inverting the operation control signal by an inverter, and the input power consumption when the level of the control signal is a level for instructing the execution of the calculation process, when holding the value of the D-type flip-flop, whereas a level different from this is, D-type flip
The number of inverters is adjusted by the odd-numbered inverters, and the odd-numbered inverters adjust the number of the inverters.
The total amount of power consumption in the arithmetic processing chip
A power consumption control method in an arithmetic processing chip, which is configured to suppress the fluctuation amount of