JP3533147B2 - Fading frequency detection method and circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fading frequency detection circuit, and more particularly to a circuit for detecting a fading frequency with high accuracy according to a time variation of a reception level.

[0002]

2. Description of the Related Art In mobile communication under a fading environment in which a received signal level fluctuates drastically, signal transmission quality is significantly deteriorated when the received signal level is lowered. The fading frequency is one of the important parameters for estimating and effectively improving the signal transmission quality that fluctuates due to fading. Various methods have been proposed in the past for detecting fading frequencies.

An example of a conventional fading frequency detecting method is disclosed in Japanese Patent No. 2953959. Referring to FIG. 8, the conventional fading frequency detection circuit includes a receiver 81, a level detection unit 82, an AD converter (ADC) 83, a storage unit 84, a difference detection unit 85, an integration unit 86, and a fading frequency detection unit 87. is doing.

The receiver 81 receives a radio wave, the level detector 82 detects the received signal level with a timing signal having a predetermined cycle, and the AD converter 83 converts the detected signal level into a digital value, thereby sampling the received signal level. .
Then, the sampled value is held in the storage unit 84.

The difference detection unit 85 calculates the difference between the received signal level sampled this time and the previously sampled received signal level held in the storage unit 84 at each sampling timing, and outputs it to the integrating unit 86. To do. The integrating unit 86 integrates the differences sequentially input from the difference detecting unit 85 over a predetermined time to obtain an integrated value.

The fading frequency detecting section 87 has a correlation table in which the correlation between the integrated value and the fading frequency obtained in advance by experiment is recorded, and the integrated value input from the integrating section 86 using the correlation table. The fading frequency is calculated based on

The moving speed of the mobile station is estimated by the fading frequency calculated in this way, and it is intended to use it for improving the signal transmission quality.

[0008]

[Patent Document 1] Japanese Patent No. 2953959
In the conventional fading frequency detection method described in the publication, if the fading frequency is constant within a predetermined time, the correlation recorded in the correlation table holds between the integrated value and the fading frequency, and an accurate fading frequency is obtained. Obtainable.

However, since the conventional fading frequency detecting method does not take into consideration the change of each difference which is sequentially input to the fading frequency detecting section 87 for each sampling, when the fading frequency changes within a predetermined time, the correlation table The fading frequency obtained by may differ from the actual fading frequency,
There is a problem that an error occurs in the obtained fading frequency.

It is an object of the present invention to provide a fading frequency detection circuit which detects a fading frequency in real time with high accuracy.

[0011]

[0012]

[0013]

[0014]

[0015]

[Means for Solving the Problems] To achieve the above object
In, the fading frequency detection method of the present invention is a fading frequency detection method for detecting the frequency of time variation of the received signal level due to the effect of fading,
The received signal is sampled with a sampling clock of a predetermined cycle, the value obtained by sampling is compared with the value one cycle before, and positive when the value exceeds a predetermined threshold during one cycle, and decreases when it exceeds the threshold. If it does, it is judged as negative, and if it does not increase or decrease beyond the threshold value, the previous judgment result is held, a pulse is output every time the judgment result shifts from negative to positive, and is counted between pulses. The number of clocks of the sampling clock is obtained, and the reciprocal of the product of the period of the sampling clock and the number of clocks is calculated as the fading frequency.

Therefore, it is possible to accurately detect the fading frequency by removing the fluctuation below the threshold value.

[0017]

[0018]

The fading frequency detection circuit of the present invention is
A fading frequency detection circuit for detecting a frequency of a time-varying received signal level due to the influence of fading, including an AD converter for sampling a received signal with a sampling clock of a predetermined cycle, and a period of a cycle obtained by dividing the sampling clock. A frequency division tuning circuit that outputs a plurality of different frequency division clocks, a plurality of memory units that are provided corresponding to the frequency division clocks and that delay the sampling signal by one cycle by the frequency division clocks, and a frequency division clock that correspond to the frequency division clocks. The sampling value input from the AD converter is provided to the memory unit at the timing of the divided clock, and the value obtained by the sampling is subtracted from the value delayed by one cycle to obtain the difference value. A plurality of sampling data calculation units for calculating and provided corresponding to the sampling data calculation unit, A plurality of fluctuation determination units that output a pulse each time the value shifts from negative to positive, and a plurality of fluctuation determination units that are provided corresponding to the fluctuation determination units and that determine the number of clocks counted between the pulses of the corresponding divided clocks. A counter and a plurality of count determination units that are provided corresponding to the counter and that output the clock number when the clock number is within a predetermined range determined corresponding to the counter; It has a fading frequency calculation processing section that calculates the reciprocal of the product of the number of input clocks and the period of the corresponding divided clock as the fading frequency.

Another fading frequency detection circuit of the present invention
Is a fading frequency detection circuit for detecting the frequency of the time variation of the received signal level due to the effect of fading, and an AD converter for sampling the received signal with a sampling clock of a predetermined cycle, and a value obtained by sampling for the sampling clock. A memory unit that delays by one cycle, a sampling data calculation unit that outputs the value obtained by sampling input from the AD converter to the memory unit, and compares the value with the value delayed by one cycle in the memory unit, and sampling data From the comparison result of the calculation unit, it is judged as positive when the value obtained by sampling exceeds a predetermined threshold value during one cycle, and as negative when it decreases below the threshold value, and also increases when it exceeds the threshold value. If not, the previous judgment result is retained and a pulse is output each time the judgment result changes from negative to positive. A fluctuation determining unit, a counter for determining the number of clocks of the sampling clock counted between the pulses, and a fading frequency calculation processing unit for calculating the reciprocal of the product of the period of the sampling clock and the number of clocks as the fading frequency. There is.

Still another fading frequency detecting circuit of the present invention is a fading frequency detecting circuit for detecting a frequency of a temporal change of a received signal level due to the influence of fading, and sampling the received signal with a sampling clock of a predetermined cycle. An AD converter, a frequency-division tuning circuit that frequency-divides the sampling clock and outputs a plurality of frequency-divided clocks with different cycles, and a value provided by sampling that is provided corresponding to the frequency-divided clock A plurality of memory units for delaying by a minute and a frequency-divided clock are provided, and the value obtained by sampling input from the AD converter is output to the memory unit at the timing of the frequency-divided clock, and the memory unit performs one cycle. A plurality of sampling data calculation units for comparing the value delayed by a minute, and a sampling data calculation unit Provided in correspondence, the comparison result of the sampling data operation unit, a value obtained by sampling 1
It is determined to be positive when it increases beyond a predetermined threshold during the cycle, negative when it decreases above the threshold, and retains the previous determination result when it does not increase or decrease beyond the threshold, and determines A plurality of fluctuation determination units that output a pulse each time the result shifts from negative to positive, and a plurality of fluctuation determination units that are provided corresponding to the fluctuation determination units and that determine the number of clocks counted between the pulses of the corresponding divided clocks. A counter and a plurality of count determination units that are provided corresponding to the counter and that output the clock number when the clock number is within a predetermined range determined corresponding to the counter; It has a fading frequency calculation processing section that calculates the reciprocal of the product of the number of input clocks and the period of the corresponding divided clock as the fading frequency.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION A fading frequency detection circuit according to an embodiment of the present invention will be described in detail with reference to the drawings. (First Embodiment) Referring to FIG. 1, a fading frequency detecting circuit according to a first embodiment of the present invention is provided with an antenna 1
, Receiver 2, signal detector 3, sampling signal generator 4
It has an AD converter (ADC) 5, a sampling data calculation unit 6, a memory unit 7, a variation determination unit 8, a counter 9, and a fading frequency calculation processing unit 10.

The receiver 2 receives a radio signal via the antenna 1.

The signal detector 3 outputs a detection voltage according to the received signal level of the signal received by the receiver 2.

The sampling signal generator 4 generates a sampling signal A having a predetermined cycle for sampling the received signal.

The AD converter 5 samples the detection signal detected by the signal detection unit 3 at the timing of the sampling signal A generated by the sampling signal generation unit 4,
Quantize and convert to digital sampling values.

The sampling data calculation unit 6 outputs the sampling value input from the AD converter 5 to the memory unit 7 to hold it, and compares the previous sampling value output from the memory unit 7 with the current sampling value. And the change is calculated.

The memory unit 7 holds the sampling value from the sampling data operation unit 6 for one clock of the sampling signal and then outputs it to the sampling data operation unit 6.

The fluctuation determining unit 8 outputs a periodic signal B indicating the fading period when the received signal level shifts from a decrease to an increase based on the change input from the sampling data calculation unit 6. In order to prevent the fading frequency from being erroneously detected, the fluctuation determining unit 8 separates a fluctuation in the received signal level due to random noise from a fluctuation in the received signal level due to fading, and a predetermined threshold M.
(And threshold-M) are stored, and when the change output from the sampling data calculator 6 is larger than the threshold M, it is determined to be “increase”, and when the change is smaller than the threshold −M, it is determined to be “decrease”. When the change amount is greater than or equal to the threshold value −M and less than or equal to the threshold value M, the previous determination result is maintained, and when the change amount changes from “decrease” to “increase”, a pulse is output as the periodic signal B.

The counter 9 increments the sampling signal A by +1.
It is a counter that counts up one by one and outputs the count value T up to that time when the periodic signal B enters and resets the counter value to zero.

The fading frequency calculation processing section 10 calculates the fading frequency by taking the reciprocal of the value (fading cycle) obtained by multiplying the cycle of the sampling signal A by the counter value T.

Next, the operation of the fading frequency detection circuit of the first embodiment will be described.

The received signal level of the radio wave changes temporally due to fading, and its waveform has peaks (peaks) and valleys (falls) in the fading cycle. The fading cycle is not constant but changes with time. Here, the reception signal received by the receiver 2 via the antenna 1 and detected by the signal detection unit 3 is shown in FIG.
It is assumed that the waveform is like.

FIG. 3 is an explanatory diagram for explaining the operation of the fading frequency detection circuit of the first embodiment.

The AD converter 5 samples the received signal at the timing of the sampling signal A generated by the sampling signal generator 4 and quantizes it to calculate a sampling value. The sampling value output from the AD converter 5 is delayed by one clock of the sampling signal A in the memory unit 7.

The difference between the current sampling value output from the AD converter 5 and the previous sampling value delayed by the memory section 7 is calculated by the sampling data calculating section 6 as a variation of the sampling value.

In FIG. 3, the variation of the sampling value is the threshold value M.
The case where it is larger than "M" is shown as "+", the case where it is smaller than the threshold -M is shown as "-", and the case where it is more than the threshold -M and less than the threshold M is shown as "0". For example, at the timing when the sampling value S2 is output from the AD converter 5, since the sampling value S1 is output from the memory unit 7, the change in the sampling value becomes S2-S1. In the example of FIG. 3, the sampling value change S2-S1 is smaller than the threshold value -M and is therefore "-".

"Increase" when the variation of the sampling value is larger than the threshold value M, and "decrease" when it is smaller than the threshold value -M.
If the change in the sampling value is greater than or equal to the threshold value −M and less than or equal to the threshold value M, the previous determination result is retained and the comparison determination is performed, and the comparison determination result shifts from “decrease” to “increase”. The fluctuation determination unit 8 outputs the periodic signal B at the timing.

In FIG. 3, when the result of the comparison judgment is "increase", it is indicated by "+", and when it is "decrease", it is indicated by "-". For example, at the timing when the sampling value S20 is output from the AD converter 5, the sampling value change amount is “0” because the sampling value change amount is greater than or equal to the threshold value −M and less than or equal to the threshold value M, and the previous sampling value change amount is Since it is "-", the comparison determination result is "-".

Then, as shown in FIG. 4, the number of sampling signals A from the pulse of the periodic signal B to the next pulse is counted by the counter 9. The fading frequency calculation processing unit 10 calculates the fading frequency by multiplying the cycle of the sampling signal A by the count value T from the counter 9 and taking the reciprocal.

Therefore, the variation below the threshold value M is eliminated,
Since the fading frequency is detected for each timing of the periodic signal B, that is, for each fading valley, an accurate fading frequency without false detection due to random noise can be detected in real time. (Second Embodiment) Referring to FIG. 5, a fading frequency detecting circuit according to a second embodiment of the present invention includes an antenna 1
, Receiver 2, signal detector 3, sampling signal generator 4
And AD converter 5 and period calculators 50 ₁ , 50 ₂ , 50 ₃
And frequency division tuning circuit 51 and fading frequency calculation processing unit 5
Have two.

The antenna 1, the receiver 2, the signal detector 3, the sampling signal generator 4, and the AD converter 5 are the same as those in the first embodiment.

The cycle calculating units 50 ₁ , 50 ₂ , 50 ₃ are respectively memory units 6 ₁ , 6 ₂ , 6 ₃ and sampling data calculating units 7 ₁ , 7 ₂ , 7 ₃ and fluctuation determining units 8 ₁ , 8 _2. , 8 ₃ and counters 9 ₁ , 9 ₂ , 9 ₃ and count determination units 11 ₁ , 11 ₂ , 11 ₃
have. The period calculation units 50 ₁ , 50 ₂ , and 50 ₃ have the same configuration, but have different frequency ranges detected by them.

The memory units 6 ₁ , 6 ₂ and 6 ₃ are the same as the memory unit 6 of the first embodiment and the sampling data calculation units 7 ₁ , 7 ₂ ,
7 ₃ is the sampling data calculation unit 7 of the first embodiment.
The counters 9 ₁ , 9 ₂ and 9 ₃ are the same as the counter 9 of the first embodiment.

The count determination unit _111, the count value T ₁ to the output of the counter 10 ₁ and outputs the count value T ₁ if the count range is set value of the predetermined range.
Similarly, the count determination units 11 ₂ and 11 ₃ use the counter 10
_If the count values T ₂ and T ₃ output by ₂ and 10 ₃ are within the count range, the count values T ₂ and T ₃ are output. The count range of each of the count determination sections 11 ₁ , 11 ₂ , and 11 ₃ can be set individually, and the cycle calculation section 50 of each of them can be set.
₁ , 50 ₂ and 50 ₃ are determined based on the range of fading frequencies to be detected.

The frequency-division tuning circuit 51 includes a period calculation unit 5
In order to assign 0 ₁ , 50 ₂ , and 50 ₃ to the detection of different fading frequency ranges, the sampling signal A output from the sampling signal generation unit 4 is divided, and three kinds of different periods as shown in FIG. Sampling signals X, Y, Z are generated. Dividing the tuning circuit 51, a sampling signal X of the same period as the sampling signal A to the period calculating unit 50 _1, the sampling signal Y of 4 times the period the period calculating unit 50 _2, 16 times the cycle of the sampling signal Z Are output to the cycle calculation unit 50 ₃ .

The fading frequency calculation processing section 52 receives the count values T ₁ , from the cycle calculating sections 50 ₁ , 50 ₂ and 50 ₃ .
When T ₂ and T ₃ are output, the fading frequency is calculated by taking the reciprocal of the value (fading period) obtained by multiplying the count values T ₁ , T ₂ and T ₃ by the periods of the sampling signals X, Y and Z corresponding thereto, respectively. calculate.

Next, the operation of the fading frequency detection circuit of the second embodiment will be described.

The sampling values calculated by the AD converter 5 are delayed by one clock of the corresponding sampling signals X, Y and Z in the memory sections 7 ₁ , 7 ₂ and 7 ₃ , respectively. The sampling data calculation units 6 ₁ , 6 ₂ and 6 ₃ calculate the difference between the previous sampling value and the current sampling value (sampling value change) at the timings of the sampling signals X, Y and Z corresponding to the respective sampling data.

The fluctuation determining units 8 ₁ , 8 ₂ and 8 ₃ determine “increase” or “decrease”, and when the transition from “decrease” to “increase” is made, the periodic signals B ₁ , B ₂ and B ₃ are changed. Output. The number of sampling signals X, Y, Z from the pulse of the periodic signals B ₁ , B ₂ , B ₃ to the next pulse is counted by counters 9 ₁ , 9 ₂ , 9 ₃ , respectively, and count values T ₁ , T ₂ , Calculate T ₃ . The count values T ₁ , T ₂ , and T ₃ are the count determination unit 1
If the count range is set to 1 ₁ , 11 ₂ , and 11 ₃ , the count values T ₁ , T ₂ , and T ₃ are set to the count determination unit 1
The signals are output from 1 ₁ , 11 ₂ , and 11 ₃ to the fading frequency calculation processing unit 52. The fading frequency is calculated by multiplying the count values T ₁ , T ₂ , and T ₃ input by the fading frequency calculation processing unit 52 by the periods of the sampling signals X, Y, and Z, respectively, and taking the reciprocal.

For example, as shown in FIG. 7, the sampling signal X is set to 8 KHz, the sampling signal Y is set to 2 KHz, and the sampling signal Z is set to 500 Hz, which are output to the period calculating units 50 ₁ , 50 ₂ , and 50 ₃ , respectively.

Further, the count range of the count determination unit 11 ₁ is set to a count value of 60 or less, the count range of the count determination unit 11 ₂ is set to a count value of 16 or more and 60 or less, and the count range of the count determination unit 11 ₃ is set to a count value of 16 or more. Set to.

As a result, the fading frequency 133H
z (≈1 / (60/8 KHz)) or more is the period calculation unit 50
Detected using ₁ and fading frequency 33Hz (≒ 1
/ (60 / 2KHz)) to 125Hz (≒ 1 / (16
/ 2 KHz)) is detected using the cycle calculation unit 50 ₂ , and the fading frequency is 31 Hz (≈1 / (16/50
It is possible to configure a fading frequency detection circuit that detects the frequency of 0 Hz)) or less by using the period calculation unit 50 ₃ .

Therefore, since the sampling signals X, Y, and Z having different cycles are assigned to each range of fading frequencies for detecting, fading frequencies in a wide range can be detected without increasing the upper limit of the count value to increase the resolution. It is possible to provide a fading frequency detection circuit that detects a wide range of fading frequencies with a small circuit scale.

[0055]

According to the present invention, fluctuations below a threshold can be removed, and a fading frequency can be detected for each fading valley, so that an accurate fading frequency without false detection due to random noise can be obtained in real time. Can be detected.

Further, since divided clocks having different cycles are assigned to different fading frequency ranges, fading frequencies in a wide frequency range can be detected without increasing the upper limit of the count value, and fading over a wide range with a small circuit scale. The frequency can be detected.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a fading frequency detection circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram showing an example of temporal changes in reception level due to fading.

FIG. 3 is an explanatory diagram for explaining the operation of the fading frequency detection circuit of the first embodiment.

FIG. 4 is an explanatory diagram for explaining the operation of the counter of the fading frequency detection circuit according to the first embodiment.

FIG. 5 is a block diagram showing a configuration of a fading frequency detection circuit according to a second embodiment of the present invention.

FIG. 6 is a timing chart showing the operation of the frequency division tuning circuit of the fading frequency detection circuit of the second embodiment.

FIG. 7 is an explanatory diagram for describing an example of a fading frequency range detected by each cycle calculation unit according to the second embodiment.

FIG. 8 is a block diagram showing a configuration of a conventional fading frequency detection circuit.

[Explanation of symbols]

1 Antenna 2 Receiver 3 Signal Detector 4 Sampling Signal Generation Unit 5 AD Converter 6, 6 _{1 to} 6 ₃ Sampling Data Calculation Unit 7, 7 _{1 to} 7 ₃ Memory Unit 8, 8 ₁ to 8 ₃ Fluctuation Judgment Unit 9, 9 _{1 to} 9 ₃ counter 10 fading frequency calculation processing unit 11 _{1 to} 11 ₃ count determination unit 50 cycle calculation unit 51 frequency division tuning circuit 52 fading frequency detection circuit

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04B 17/00 H04B 7/26

Claims (4)

(57) [Claims] 1. A fading frequency detection method for detecting a frequency of a temporal change of a received signal level due to the influence of fading, wherein a received signal is sampled with a sampling clock of a predetermined cycle, and a value obtained by the sampling is Compare the values one cycle before, and if the increase exceeds a predetermined threshold during one cycle, it is judged as positive, and if the decrease exceeds the threshold, it is judged as negative, and neither increase nor decrease exceed the threshold. If the result of the previous determination is held, a pulse is output each time the determination result shifts from negative to positive, the number of clocks of the sampling clock counted between the pulses is calculated, and the cycle of the sampling clock and the A fading frequency detection method that calculates the reciprocal of the product of the number of clocks as the fading frequency. 2. A fading frequency detection circuit for detecting a frequency of a received signal level that fluctuates over time due to the influence of fading, the AD converter sampling a received signal with a sampling clock having a predetermined cycle, and dividing the sampling clock. And a frequency division tuning circuit that outputs a plurality of frequency division clocks having different periods, and a plurality of frequency division tuning circuits that are provided corresponding to the frequency division clocks and delay the value obtained by sampling by one cycle of the frequency division clocks. A memory unit, which is provided corresponding to the divided clock, outputs the value obtained by the sampling input from the AD converter to the memory unit at the timing of the divided clock, and from the value obtained by the sampling. A plurality of sampling data operations for calculating a difference value by subtracting a value delayed by one cycle in the memory unit. Section, a plurality of variation determination sections that are provided corresponding to the sampling data calculation section, and that output a pulse each time the difference value shifts from negative to positive, and a plurality of variation determination sections that are provided corresponding to the variation determination section. A plurality of counters for obtaining the number of clocks counted between the pulses of the divided clock, and the number of clocks provided within the predetermined range corresponding to the counters. In the case of fading, calculating a reciprocal of a product of a plurality of count determination units that output the number of clocks, the number of clocks input from the count determination unit, and the cycle of the corresponding divided clock as a fading frequency. A fading frequency detection circuit having a frequency calculation processing unit. 3. A fading frequency detection circuit for detecting a frequency of a time-varying received signal level due to the influence of fading, the AD converter sampling a received signal with a sampling clock having a predetermined cycle, and a value obtained by the sampling. Of the sampling clock is delayed by one cycle, and a value obtained by the sampling input from the AD converter is output to the memory section and is compared with a value delayed by one cycle in the memory section. From the comparison result of the sampling data operation unit and the sampling data operation unit, positive when the value obtained by the sampling exceeds a predetermined threshold value during one cycle, and positive when the value exceeds the threshold value. If the result of the judgment is negative and the value does not increase or decrease beyond the threshold, the previous judgment result is retained. Then, a variation determination unit that outputs a pulse each time the determination result shifts from negative to positive, a counter that determines the number of clocks of the sampling clock counted between the pulses, a cycle of the sampling clock, and the number of clocks. A fading frequency detection circuit having a fading frequency calculation processing section for calculating the reciprocal of the product of the above as a fading frequency. 4. A fading frequency detection circuit for detecting a frequency of a received signal level that changes with time due to the effect of fading, the AD converter sampling a received signal with a sampling clock of a predetermined cycle, and dividing the sampling clock. And a frequency division tuning circuit for outputting a plurality of frequency division clocks having different cycles, and a plurality of memories provided corresponding to the frequency division clocks and delaying the value obtained by the sampling by one cycle of the frequency division clocks. And a sampling value input from the AD converter at the timing of the divided clock and provided to the memory unit and delayed by one cycle in the memory unit. A plurality of sampling data calculation units for comparing with a value, corresponding to the sampling data calculation unit Is determined to be positive when the value obtained by the sampling exceeds a predetermined threshold value during one cycle, and negative when the value exceeds the threshold value, based on the comparison result of the sampling data calculation unit. However, when the determination result of the previous time is held when neither increase nor decrease exceeds the threshold value, a plurality of variation determination units that output a pulse each time the determination result shifts from negative to positive, and the variation determination unit A plurality of counters that are provided corresponding to each other and that determine the number of clocks counted between the pulses of the corresponding divided clock; and a plurality of counters that are provided corresponding to the counters and the number of clocks is determined corresponding to the counters. When the number of clocks is within the predetermined range, a plurality of count determination units that output the number of clocks, the number of clocks input from the count determination unit, and the corresponding divided clock A fading frequency detection circuit having a fading frequency calculation processing section for calculating the reciprocal of the product of the period as a fading frequency.