JP3534396B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a high speed and highly integrated semiconductor device including fine elements.

[0002]

2. Description of the Related Art Semiconductor integrated circuits (LSI = Large Scale)
High integration is due to its component element, MO
This has been promoted by miniaturization of S transistors. When a so-called deep sub-micron LSI with a minimum element size of 0.5 micron or less is used, the withstand voltage of the element decreases and L
An increase in the power consumed by SI becomes a problem. For such a problem, it is considered that reducing the operating power supply voltage with the miniaturization of the element is an effective means.

Since the power supply voltage of the present LSI is currently 5V, the technique of mounting a voltage conversion circuit for stepping down the external power supply voltage on the LSI chip is used as a means for constructing the LSI with fine elements. EE EE Journal of Solid State Circuits, 2nd
Volume 1, Issue 5, Pages 605-611 (1986) (IEE
E Jounal of Solid-State Circuits, vol.21, No.5, p
p.605-611, October 1986).
The values of the external power supply voltage and the internal power supply voltage in this case are 5V and 3.5V, respectively. As described above, the problem of power consumption is becoming apparent in the dynamic RAM (DRAM) having the highest degree of integration among LSIs.

[0004]

On the other hand, however, it has been pointed out that the power supply voltage has a lower limit due to physical restrictions. Regarding this restriction, I.E.E.Journal of Solid State Circuits, Vol. 9, No. 5, 256-267 (197)
4) (IEEE Jounal of Solid-State Circuits, vol.9, N
o.5, pp.256-267, October 1974). As shown therein, the low current characteristic of the MOS transistor has a so-called subthreshold characteristic in which the drain current decays exponentially with respect to the gate voltage. This coefficient is called a subthreshold coefficient (tailing coefficient), and is a value of about 80 mV / 1 digit at room temperature. Therefore, if the gate threshold voltage is lowered in proportion to the drop in the power supply voltage, a minute DC current will flow even during the period when the transistor is cut off, which will increase the standby current consumption. . Therefore, in the conventional CMOS circuit, it has been said that the threshold voltage cannot be lowered below a certain value when the power supply voltage is lowered. For the practical lower limit, see Proceedings of Technical Papers, 1989.
・ International Symposium on Bryer S Technology System and Applications, 188-192 (1989) (Proce
edings of Technical Papers, 1989 International Symp
osium on VLSI Technology, Systems and Application
s, pp.188-192, May 1989) and Proceedings
Of the Symposium on Low Temperer Electronics & High Temperer
Superconductors, pp. 55-69 (198
7) (Proceedings of the Symposium on Low Tempera
ture Electronics and High Temperature Superconduct
ors, pp.55-69, Oct. 1987). Its value is about 0.35 to 0.55V.
The lower limit of the power supply voltage at this time is practically about 1.5 V, and there is a problem that the delay time remarkably increases when the voltage is further lowered.

An object of the present invention is to provide a semiconductor integrated circuit which can operate with a low power supply voltage.

[0006]

An example of the present invention will be described below. That is, in a semiconductor device including a plurality of logic circuits connected in multiple stages, each of the plurality of logic circuits has a first P-channel having a first threshold voltage.
A first CMOS circuit including a MOS transistor and an N-channel second MOS transistor having a second threshold voltage, which is one of the plurality of logic circuits connected in multiple stages, and which transmits a signal through a predetermined signal path. The first CMOS circuit of the logic circuit is for replacing the first and second MOS transistors with a P-channel third MOS transistor having a third threshold voltage and an N-channel fourth MOS transistor having a fourth threshold voltage. And a second CMOS circuit including and. Here, the absolute value of the third threshold voltage is lower than the absolute value of the first threshold voltage, and the absolute value of the fourth threshold voltage is the absolute value of the second threshold voltage. Lower than the value. Further, the third and fourth M
Each of the OS transistors has a threshold voltage having a characteristic that a subthreshold current flows when its source-gate voltage is OV.

Second CMO for driving a predetermined signal transmission path
By using a MOS transistor having a small threshold voltage in the S circuit, the speed of the signal path can be increased.

[0008]

1 is an embodiment for explaining the basic concept of a CMOS integrated circuit according to the present invention. In the figure, the CMOS integrated circuit is composed of a plurality of circuit blocks such as BLK1 and BLK2, and signal wirings for transmitting signals between them. In the example of this figure, the output of BLK1 is transmitted to the input of BLK2 through the signal wiring SIG1. Each circuit block receives a signal of a small amplitude from another circuit block and converts it into a signal of a large amplitude (eg, REC2 in the figure), and a signal processing section that processes a signal of a large amplitude (eg, a figure). Medium INV1 and INV2), and a drive circuit (for example, DRV1 in the figure) that outputs a signal with a small amplitude to the signal wiring.

Of these, the signal processing section uses the power supply voltage VC
It operates by C and VSS, and its signal amplitude is (VCC-V
SS). The drive circuit DRV1 includes an N-channel MOS transistor TN2 and a P-channel MOS transistor T.
It is composed of P2. This drive circuit has a power supply voltage VCL
It operates with O and VSLO, and the amplitude (V
CLO-VSLO) signal is output. In addition, between these power supply voltages, VCC>VCLO>VSLO> VSS
The following relationship holds. In this example, the back gate of TN2 is VSS and the back gate of TP2 is VC.
Connected to C respectively, but VSLO and V respectively
You may connect to CLO.

The signal receiving unit REC2 includes an N-channel MOS transistor TN3 and a P-channel MOS transistor TP3 which form a transfer gate, and an N-channel MOS transistor pair TN4 whose gates and drains are cross-connected.
And TN5 and P channel MOS transistor pair TP4
And TP5.

A voltage V is applied to the gate of the transfer gate TN3.
CLI and a voltage VSLI are applied to the gate of TP3, respectively. The back gate of TN3 is VSS.
Further, the back gate of TP3 is connected to VCC, respectively, but these may be VSLO and VCLO, respectively. In this embodiment, the gate threshold voltage of the N-channel MOS transistor is about 0.5V and the gate threshold voltage of the P-channel MOS transistor is about -0.5V.
It is set to V.

The operation of this circuit will be described with reference to FIG. In this example, VCC = 1.5V, VSS = 0V,
VCLO = 1V, VSLO = 0.5V, VCLI = 1.5
The case where V and VSLI = 0V will be described, but the values are not limited to these values, and VCC>VCLO>VSLO>
It is effective if the voltage is VSS and VCLI> VSLI. Now, now the circuit block BLK1
The output N1 of the inverter INV1 in the above circuit changes from 1.5V to 0V at time t0 and from 0V to 1.5 at time t3.
Consider the case where it changes to V 1.

Before the time t0, that is, the terminal N1 is 1.
During 5V, the gate-source voltage of the transistor TN2 is 1V, and the gate-source voltage of the transistor TP2 is 0.5V, so that TN2 is conductive and TP2 is non-conductive, that is, the output of the drive circuit, that is, the signal line. VSLO = 0.5V is output to SIG1. At the same time, the gate-source voltage of the transfer gate TN3 and the gate-source voltage of the transistor TP3 that form the receiving circuit REC2 are 1 V, respectively, so that TN3 is conductive and TP3 is non-conductive. The drive capability of the transistor TN3 is set to TP4
Since it is designed to be sufficiently large compared with the above, the terminal N2 is at 0.5V which is equal to the input SIG1, and the transistor TP5 is conducting. On the other hand, the voltage of the terminal N3 is 0.5
Since it is lower than V, the transistor TN5 is non-conductive, and the terminal N4 is at 1.5V. Therefore, the transistor TN4 is conducting and the terminal N3 is consequently set to 0V. Among these transistors, the gate-source voltage of TP3 is -0.5V, which is equal to the gate threshold voltage, so a minute current called the subthreshold current flows, but it is less than the transistors of the entire integrated circuit. For example, this transistor occupies a small proportion, and its current is negligibly small. Now,
Consider a case where the terminal N1 changes from 1.5V to 0V at time t0. The gate-source voltage of the transistor TN2 is -0.5 V, and the gate-source voltage of the transistor TP2 is
Since the source-to-source voltage is -1V, TN2 is non-conducting and T
P2 becomes conductive and the output of the drive circuit, that is, the signal line S
VCLO = 1V is output to IG1. This allows
The voltage of the terminal N2 rises to about 1V, and the receiving circuit REC2
Since the gate-source voltage of the transfer gate TN3 configuring the above is 0.5 V and the gate-source voltage of the transistor TP3 is -1 V, TN3 is non-conductive and TP3 is conductive. By designing the driving capability of the transistor TP3 to be sufficiently larger than that of TN4, the terminal N3 is connected to the input SIG1.
Becomes equal to 1 V, and the transistor TN5 becomes conductive.
On the other hand, since the voltage of the terminal N2 has risen to about 1V ,
The transistor TP5 becomes non-conductive, and the terminal N4 becomes 0V. As a result, the transistor TP4 becomes conductive and the terminal N
2 is pulled up to 1.5V at time t2.

Similarly, when the terminal N1 changes from 0V to 1.5V at time t3, the signal line SIG1 is also changed.
Changes from 1V to 0.5V, and the terminal N4 changes from 0V to 1.5V.

In this way, the signal amplitude of 1.5 V in the circuit block BLK1 is converted into a signal having an amplitude of 0.5 V, and the signal is converted again into a signal amplitude of 1.5 V in the circuit block BLK2. be able to. In general,
Most of the power consumption of the integrated circuit is consumed by charging / discharging a signal line (bus) provided for exchanging signals between circuit blocks. Therefore, reducing the voltage amplitude of this signal line is extremely effective in reducing the power consumption of the entire integrated circuit. In addition, by increasing the voltage amplitude in the integrated circuit block to be larger than the signal amplitude of the bus, the operating speed of the circuit group in the block is increased, and at the same time, the gate of the inverter circuit (driver) that drives the bus is set above the amplitude of the bus. It has the advantage that it can be driven with a large amplitude and the switching speed of the bus can be improved. In this embodiment, the charge amount required to charge and discharge the load capacitance CW of the signal line SIG1 once is changed from CW (VCC-VSS) to CW (V
CLO-VSLO) can be reduced to about one third. As a result, current consumption and power consumption can be reduced to about one third. In addition, when compared at the same operating speed, the peak current of the signal line and power supply line that occurs with the charging and discharging of the signal line capacity can be reduced to about one-third, and the metal wiring that constitutes the signal line and power supply line can be reduced. The reliability of can be improved. Furthermore, the noise of the power supply generated due to the resistance of the power supply line can be reduced to about one third, and an integrated circuit with more stable operation can be provided. By thus reducing the signal amplitude of the main signal line, it is possible to realize an integrated circuit with low power consumption and low noise while maintaining high speed.

In the above description, the six power supply voltages VCC,
The case where the circuit is configured using VSS, VCLO, VSLO, VCLI, and VSLI has been described. Some of these voltages may be the same voltage as shown in this embodiment. All of these may be supplied from the outside, or VCC and VSS may be supplied from the outside of the device and VCLO, VSLO, VCLI, VSLI, etc. may be generated by a voltage conversion circuit provided inside the integrated circuit.

FIG. 3 shows another embodiment of the CMOS integrated circuit according to the present invention. In this embodiment, the number of types of threshold voltage of each conductivity type MOS transistor is plural in order to reduce the number of types of power supply. In the figure, the difference from the embodiment of FIG. 1 is that the N channel M that constitutes the drive circuit DRV3.
The absolute value of the gate threshold voltage of the OS transistor TN6 and the P-channel MOS transistor TP6, and the gate threshold voltage of the N-channel MOS transistor TN7 and the P-channel MOS transistor TP7 that form the transfer gate of the signal receiving unit REC4 of the MOS transistors that form another circuit. That is, it is lower than the absolute value of the gate threshold voltage. As a result, the power supply voltage of the drive circuit and the gate application voltage of the transfer gate can be made equal to VCL and VSL. In addition,
The back gate of TN6 and TN7 is VSS, TP6 and T
The back gates of P7 are connected to VCC, respectively, but they may be VSL and VCL, respectively. In the present embodiment, the gate threshold voltage of the N-channel MOS transistor is about 0.5 V when it is higher and about 0 V when it is lower, and the gate threshold voltage of the P-channel MOS transistor is about −V when the absolute value is higher. 0.5V, the lower absolute value is about 0V.

The operation of this circuit is similarly described with the operation waveforms shown in FIG. Here, VCC = 1.5V, VSS
The case of = 0 V, VCL = 1 V, VSL = 0.5 V will be described, but it is obvious that the values are not limited to these values.

Before the time t0, that is, the terminal N5 is 1.
During 5V, the gate-source voltage of the transistor TN6 is 1V, and the gate-source voltage of the transistor TP6 is 0.5V, so that TN6 is conductive and TP6 is non-conductive, that is, the output of the drive circuit, that is, the signal line. VSL = 0.5V is output to SIG2. At the same time, the receiving circuit R
Since the gate-source voltage of the transfer gate TN7 constituting the EC4 is 0.5 V and the gate-source voltage of the transistor TP7 is 0 V, TN7 is conductive and TP7.
Becomes non-conducting. The drive capability of the transistor TN7 is TP
By designing the terminal N6 to be sufficiently larger than 8, the terminal N6 is set to 0.5V which is equal to the input SIG2, and the transistor TP9 is conductive. On the other hand, since the voltage of the terminal N7 is 0.5V or less, the transistor TN9 is non-conductive, and the terminal N8 is 1.5V. Therefore, the transistor TN8 becomes conductive and the terminal N
7 is consequently set to 0V. Among these transistors, the gate-source voltage of TP7 is 0V,
A minute current called a subthreshold current flows because it matches the gate threshold voltage, but this transistor occupies a smaller proportion than the transistor of the entire integrated circuit, and the current is negligibly small.

The operation at other times is the same as that of the example shown in FIG. As described above, by using the MOS transistors having two types of gate threshold voltages for each conductivity type, the four power supply voltages VCC, VSS, VCL, and VSL are used.
The circuit can be configured by. All of these may be supplied from the outside, or VCC and VSS are given from the outside of the device, and VC is supplied by a voltage conversion circuit provided inside the integrated circuit.
L, VSL, etc. may be generated. In addition, according to this embodiment, the same effect as the effect described in the previous embodiment can be obtained. Furthermore, the MO included in the drive circuit DRV3
Since the threshold voltage of the S-transistor is lowered, the current driving capability is increased and higher speed can be expected.

Next, the effect of the present invention will be specifically described with reference to FIG. 4 and 5 show the load capacitance (CL = 2p
An example in which the drive circuit of F) is configured by using the conventional technique and the present invention is shown. In either case, the amplitude (VCL
-VSL) signal is input and the load amplitude (VCL-V
It is driven by SL). In the conventional CMOS integrated circuit, as shown in FIG. 4, a driving circuit is composed of a plurality of stages of CMOS inverters. In a CMOS inverter, the power supply voltage is equal to the signal amplitude as it is, so V
CL and VSL are used as power sources. On the other hand, in the present invention, as shown in FIG. 5, the level conversion circuit REC5 for amplifying the amplitude of the input signal and the CMOS inverter circuit DRV5 for driving the load are used. REC5 is the same as REC4 in FIG. 3, and DRV5 is DRV3 in FIG.
And each is basically the same. The gate threshold voltage of each transistor is also the same as the value described in the description of FIG. Gate oxide film thickness of MOS transistor is 7 nm
(Nanometer), and the gate length L and the gate width W of each transistor are as follows.

[0022] As a result, the power consumption of the conventional circuit and the circuit of the present invention during standby becomes substantially the same.

FIG. 6 shows input (IN) and output (OUT) waveforms. The time when the output reaches 10% to 90% is the output rise time tr, the time when the output reaches 90% to 10% is the output fall time tf, and the time from when the input rises to 50% to when the output rises to 50%. Is defined as the rising propagation delay time tpdr, and the time from the input falling to 50% until the output falling to 50% is defined as the falling propagation delay time tpdf.

FIG. 7 shows the signal amplitude (V
(CL-VSL) dependency computer analysis results are shown.
In a conventional drive circuit using a CMOS inverter, the rise time sharply increases when the signal amplitude is 1.5 V or less. A typical relationship between signal amplitude and rise time is shown below. Becomes Taking tr <2 ns as one guide from the viewpoint of speed performance, the minimum value of the signal amplitude is 1.5V. on the other hand,
In the present invention, the relationship between the signal amplitude and the rise time is Therefore, the minimum value of the signal amplitude is about 0.12 V when tr <2 ns is one guideline. From this analysis result,
Considering the output rise time tr as a reference, according to the present invention,
The signal amplitude can be reduced by about an order of magnitude from the conventional 1.5V to about 0.12V. Although the analysis result of the output rise time tr is shown here, the same improvement effect can be obtained for the output fall time tf.

FIG. 8 shows the result of computer analysis of the dependence of the rising propagation delay time tpdr on the signal amplitude (VCL-VSL). In the conventional drive circuit using the CMOS inverter, as in the rise time, when the signal amplitude is 1.5 V or less, the rise propagation delay time sharply increases. A typical relationship between signal amplitude and rising propagation delay time is shown below. Becomes Taking tpdr <3 ns as one guideline from the viewpoint of speed performance, the minimum value of the signal amplitude is about 1.2V. On the other hand, in the present invention, the relationship between the signal amplitude and the rising propagation delay time is Therefore, if tpdr <3 ns is used as a guideline, the minimum value of the signal amplitude is about 0.31V. From this analysis result,
Considering the rise propagation delay time tpdr as a reference, according to the present invention, the signal amplitude can be reduced from about 1.2V in the related art to about 0.31V by about 1/4. Although the analysis result of the rising propagation delay time tr is shown here, a similar improvement effect can be obtained for the falling propagation delay time tf.

FIG. 9 shows another embodiment of the CMOS integrated circuit according to the present invention. In the embodiment of FIG. 1 or 3, when the signal transits between the high level and the low level, a minute DC current flows from the signal receiving portion to the signal line or from the signal line to the signal receiving portion. If the signal rise or fall time is long due to the influence of the parasitic resistance and capacitance of the signal line, or if many signal receiving circuits are connected to one signal line, this current should be smaller. It is preferable in terms of circuit operation. FIG. 9 shows an example of a configuration in which the direct current is prevented from flowing. In this example, a signal receiving unit that receives a signal with a small amplitude from another circuit block and converts it into a signal with a large amplitude is composed of a receiving circuit REC8A by a CMOS inverter and a level conversion circuit REC8B. The inverter circuit of REC8A is similar to the inverter circuit of drive circuit DRV7 in the figure, and VCL and V
It operates using SL as a power source. Level conversion circuit REC8B
Is basically the same as REC4 in FIG. In the figure, an N channel MO that constitutes the drive circuit DRV7
S transistor TN16, P channel MOS transistor TP16, and N forming the inverter of the receiving circuit REC8A
Channel MOS transistor TN17 and P channel MOS transistor TP17, and level conversion circuit R
N-channel MOS transistor TN18 and P-channel MOS transistor TP which form the transfer gate of EC8B
The absolute value of the gate threshold voltage of 18 is set lower than the absolute value of the gate threshold voltage of the MOS transistors forming the other circuits. In addition, TN16, TN17 and TN
The back gates of 18 are connected to VSS, and the back gates of TP16, TP17, and TP18 are connected to VCC, respectively, but these may be VSL and VCL, respectively. Similar to the embodiment of FIG. 3, N channel M
The higher gate threshold voltage of the OS transistor is about 0.5 V, the lower one is about 0 V, and the gate threshold voltage of the P-channel MOS transistor is about -0.
5V, the lower absolute value is about 0V.

The operation of this circuit will be described with reference to the operation waveforms shown in FIG. The difference from the example shown in FIG. 3 is that the input of the level conversion circuit REC8B is driven by an output inverted by an inverter instead of being directly driven by a signal line. Therefore, in this embodiment, the signal at the terminal N10 is transmitted to the terminal N14.
It has been reversed by, but the basic operation is the same. Note that here, VCC = 1.5V, VSS = 0V, VC
The case of L = 1V and VSL = 0.5V will be described, but it is obvious that the values are not limited to these values.

As described above, by configuring the signal receiving unit with the CMOS inverter and the level converting circuit, the direct current flows from the signal line to the signal receiving unit or the direct current flows from the signal receiving unit to the signal line. Can be eliminated. A direct current flows from the power source VCL to VSL in the CMOS inverter that constitutes the receiving circuit. However, since the number and size of elements forming the inverter are so small as to be negligible with respect to the total number and size of elements of the integrated circuit, this current does not have a great influence on the current consumption of the integrated circuit.

FIG. 11 shows another embodiment of the CMOS integrated circuit according to the present invention. In this embodiment, a signal receiving unit is provided which receives a plurality of signals of small amplitude and converts the logical operation result into a large signal amplitude used inside the circuit block.

In this example, the signal receiving section is composed of a receiving circuit REC11A having a NAND gate and a level conversion circuit REC11B. REC11A NAND
The gate operates using VCL and VSL as power supplies, as in the REC 8A in FIG. The level conversion circuit REC11B is
It is basically the same as REC4 in FIG. 3 or REC8B in FIG.

As in the case of a normal CMOS circuit, two N-channel MOS transistors TN3 connected in series are connected.
2, TN33 and two P-channel MO connected in parallel
A NAND gate is composed of the S transistors TP32 and TP33. In addition to this, another circuit block BLK9
Signal SIG4 from BLK10 and signal SIG5 from BLK10
And the NAND output is obtained at the terminal N15. N
As shown in FIG.
As in the case of the REC 8A, a low threshold voltage absolute value is used. With such a configuration, the logical operation result of a plurality of low-amplitude signals can be taken into the circuit block as a large signal. Here, the case of a 2-input NAND has been described as an example of the logical operation.
It is obvious that any logical operation such as NOR of two or more inputs, EOR (exclusive OR), or the like can be similarly applied.

FIG. 12 shows an embodiment of a circuit configuration for generating the power supply voltages VCL and VSL inside the chip based on the external power supply voltages VCC and VSS.

In the figure, DIV is three resistors R1, R2, R
3, a voltage dividing circuit configured by 3, OP1 and OP2 are differential amplifier circuits, TP40 is a P channel MOS transistor for driving VCL, and TN40 is an N channel MOS for driving VSL.
Transistors, R4 and R5 are bias resistors, C1 to
C3 is a smoothing capacitor. This circuit allows VCL and V
For SL, VCL = (R2 + R3) × (VCC-VSS) / (R1
+ R2 + R3) VSL = R3 × (VCC-VSS) / (R1 + R2 + R
3) The following voltage is obtained. For example, VCC = 1.5V, VS
When S = 0V, R1 = R2 = R3, VCL = 1
V, VSL = 0.5V is obtained.

FIG. 13 shows another embodiment of the integrated circuit according to the present invention. In this embodiment, common power supplies VCL and VSL
Instead of being supplied to the drive circuit of the signal line, VCC, VS
S is supplied to reduce the signal amplitude for each drive circuit.

In FIG. 13, CHP5 is an integrated circuit chip, BLK12 and BLK13 are circuit blocks constituting the chip, SIG6 is a signal line for transmitting a signal of a small amplitude from BLK12 to BLK13, DRV12 is a signal line drive circuit, The REC 13 is a signal receiving circuit. The basic configuration is the same as that shown in FIG. 3 except for the drive circuit DRV12.

The drive circuit DRV12 is an N channel MOS.
Transistor TN40, P channel MOS transistor TP40, NPN type bipolar transistor Q1, P
It is composed of an NP type bipolar transistor Q2. The collector terminals of the two bipolar transistors are connected to the power supplies VCC and VSS, respectively, and the emitter terminals are connected to the CMOS inverter. At the base terminal of each bipolar transistor, a DC voltage VCLB,
Applying VSLB. These values are VCLB = VCL + VBE VSLB = VSL-VBE, respectively. Here, VBE is the forward voltage drop between the base and the emitter of the bipolar transistor and is about 0.7.
It is 5V. With such a connection, VCL is obtained at the terminal N20 and VSL is obtained at the terminal N21. According to this circuit system, it is not necessary for the VCL and VSL power supplies to have a low impedance as in the example of FIG. Therefore, the generating circuit as shown in FIG. 12 does not need to have a large driving ability either, and the occupying area of the generating circuit itself and the power consumption are not increased. Similar effects can be obtained by using N-channel and P-channel MOS transistors instead of the NPN-type and PNP-type bipolar transistors used in this example.

FIG. 14 shows an embodiment of the configuration of a circuit for generating power supply voltages VCL, VSL and VCLB, VSLB inside the chip based on the external power supply voltages VCC, VSS.

In the figure, the voltage dividing circuit includes resistors R10, R11 and R.
NPN type and PN in which 12 and the base and the emitter are connected
It is composed of P-type bipolar transistors Q3 and Q4. Q5 is an NPN type bipolar transistor for driving VCL, Q6 is a PNP type bipolar transistor for driving VSL, R13 is a resistor for bias, C10
C12 are smoothing capacitors. This circuit allows VCL
VSL = ((R11 + R12) x VCC + (R10-R11-R12) x VBE) / (R10 +
R11 + R12) VSL = (R12 × VCC + (R10 + R11-R12) × VBE) / (R10 + R11 + R1
2) is obtained. However, it is assumed here that VSS = 0V. VBE is a forward voltage drop between the base and the emitter of the bipolar transistor, which is about 0.
It is about 75V. For example, VCC = 3V, 0.25 ×
When R11 = R10 = R12, VCL = 2V, VS
L = 1V is obtained.

FIG. 15 shows another embodiment of the integrated circuit according to the present invention. In this embodiment, the signal transmission between the integrated circuit chips is carried out by a low amplitude signal.

In the figure, CHP6 and CHP7 are integrated circuit chips, SIG7 is a signal line for transmitting a signal of small amplitude from CHP6 to CHP7, DRV16 is a signal line drive circuit, and REC17 is a signal reception circuit. The drive circuit DRV16 is similar to the DRV12 shown in FIG.
C17 is basically the same as that shown in REC13 in FIG.

With such a structure, it is possible to reduce the power required to drive the signal line between the chips having a large capacitance. Further, it is possible to suppress the peak current generated due to the charge and discharge of the signal line to a low level, and it is possible to reduce the reliability of the signal wiring and the noise of the power supply line. Therefore, the effect is particularly great in an integrated circuit having a large number of signal lines such as a microprocessor.

Further, in the conventional input circuit of the integrated circuit chip, the TTL level (for example, the LOW judgment level maximum value V
IL _MAX = 0.8V, HIGH judgment level minimum value VIH
There is a problem in that a stand-by current cannot be reduced because a through current flows through the CMOS inverter with respect to an input of ( _MIN = 2.4 V). However, if the receiver circuit of the present invention is used, this stand-by current is reduced. Since it can be made extremely small, it is extremely effective in reducing the current consumption of the integrated circuit chip.

FIG. 16 shows another embodiment of the integrated circuit according to the present invention. In this embodiment, as in the case of FIG. 15, the signal transmission between the integrated circuits is performed by a signal having a low amplitude.

In the figure, CHP8 and CHP9 are integrated circuit chips, SIG8 is a signal line for transmitting a signal of small amplitude from CHP8 to CHP9, DRV18 is a signal line drive circuit, and REC19 is a signal reception circuit. The drive circuit DRV18 is an NPN type bipolar transistor Q2.
0 and a PNP bipolar transistor Q21 are used as a complementary inverter circuit, and a CMOS inverter circuit provided to drive the base terminal which is the input thereof. VCLB and VSLB are applied to the power supply voltage of the CMOS inverter circuit, and the input of the complementary inverter circuit is set to VCL + VB as a high level.
E, VSL-VBE is obtained as a low level. As a result, the amplitude of the signal line becomes (VCL-VS
L) can be obtained.

With this structure, it is possible to reduce the electric power required to drive the signal line between the chips having a large capacitance. Further, it is possible to suppress the peak current generated due to the charge and discharge of the signal line to a low level, and it is possible to reduce the reliability of the signal wiring and the noise of the power supply line. In particular, since the output circuit is composed of only bipolar transistors, it is possible to obtain a larger load driving capability than the example of FIG.

17 to 20 show a CMOS according to the present invention.
7 illustrates another embodiment of an integrated circuit. In these embodiments, other methods of the signal receiving section are shown in which a plurality of signals having small amplitudes are input and the logical operation result is converted into a large signal amplitude used inside the circuit block.

FIG. 17 shows an example of the circuit configuration of the signal receiving section which outputs the operation result Q of the inverted logical product (NAND) of the two inputs A and B. That is, when both inputs A and B are at high level, output Q is at low level, and at other times, output Q is at high level. As for the signal amplitudes of the inputs A and B and the inverted signal B-bar of the signal B, the low level is VSL and the high level is VCL, as in the embodiment of FIG. The inverted signal B-bar may be generated by a drive circuit, or may be generated from the input B by providing an inverter in the receiving section. In this circuit, in REC4 in FIG. 3, the transfer gate is composed of four transistors, TN70, TN71, TP70 and TP71, in order to utilize the level conversion function as it is and newly have a logical operation function. In addition to increasing the voltage, a signal is applied to the gate terminal of the transfer gate instead of the DC voltage.

Next, the operation of this circuit will be described. When the input B is at the low level, that is, when the input B-bar is at the high level, the transistor TN70 is in the non-conducting state, TN7.
1 becomes conductive, and the terminal N40 becomes low level. Further, the transistor TP70 is turned off, the transistor TP71 is turned on, and the terminal N41 also goes low. Therefore, the output Q becomes high regardless of the level of the input A. On the other hand, when the input B is at the high level, the transistor TN70 is in the conductive state, the TN71 is in the non-conductive state, and the terminal N40 is at the same level as the input A. Further, the transistor TP70 is in a conductive state, the TP71 is in a non-conductive state, and the terminal N41 is also at a level equal to the input A. Therefore, the inverted output of the input A is obtained at the output Q. From these, the output becomes low level only when both inputs A and B are at high level, and the output becomes high level in the other combinations. That is, the operation result of the inverted logical product (NAND) of A and B is obtained at the output Q.

FIG. 18 shows an example of a circuit configuration of a signal receiving section which outputs an operation result Q of an inverted logical sum (NOR) of two inputs A and B. That is, when both inputs A and B are at low level, output Q is at high level, and at other times, output Q is at low level. When input B is high level,
That is, when the input B-bar is low level, the transistor TN75 is conductive, the TN76 is nonconductive, and the terminal N45 is high level. Further, the transistor TP75 is turned on, the transistor TP76 is turned off, and the terminal N46 also goes high. Therefore, the output Q becomes a low level regardless of the level of the input A. On the other hand, input B
Is low, the transistor TN75 is non-conductive, the TN76 is conductive, and the terminal N45 is input A
The level is equal to. Further, the transistor TP75 is turned off, the transistor TP76 is turned on, and the terminal N46 is set to the same level as the input A. Therefore, the inverted output of the input A is obtained at the output Q. From these, inputs A and B
The output becomes high level only when both are low level, and the output becomes low level in other combinations. That is, the operation result of the inverted logical sum (NOR) of A and B is output Q
Can be obtained.

FIG. 19 shows an example of the circuit configuration of the signal receiving section which outputs the operation result Q of the inverted logical product (NAND) of the three inputs A, B and C. Similar to the embodiment of FIG. 17, when the inputs A, B and C are all at the high level, the terminals N50 and N51 are at the high level. From these, the output becomes low level only when the inputs A and B and C are all at high level, and the output becomes high level in the other combinations. That is, the operation result of the inverted logical product (NAND) of A, B and C is obtained at the output Q.

FIG. 20 shows an example of the circuit configuration of the signal receiving section which outputs the operation result Q of the exclusive OR of two inputs A and B (Exclusive-OR = EOR). That is, when the inputs A and B are at the same level, the output Q is low level, and at other times, the output Q is high level. Input B
Is at a high level, that is, when the input B-bar is at a low level, the transistor TN85 is in a conductive state and TN8
6 becomes non-conductive, and the terminal N55 becomes the same level as the input A. In addition, the transistor TP85 is conductive, and T
P86 becomes non-conductive, and the terminal N56 also becomes the same level as the input A. Therefore, the output Q has the inverted logic of the input A. On the other hand, when the input B is at the low level, the transistor TN85 is in the non-conductive state, the TN86 is in the conductive state, and the terminal N55 is at the same level as the input A-bar.
Further, the transistor TP85 is turned off, the transistor TP86 is turned on, and the terminal N56 is at the same level as the input A-bar. Therefore, the output Q has the same logic as the input A. From these, the exclusive OR (EOR) of inputs A and B
The calculation result of is obtained at the output Q.

As shown in the above embodiments, according to the present invention, since it is possible to directly perform a logical operation from a plurality of signals having a small input amplitude, after performing a level conversion on a plurality of inputs individually, The number of transistors used can be reduced as compared with the case where calculation is performed, and a highly integrated circuit can be configured. Further, it is obvious that the present invention can be similarly applied to a larger number of inputs and any other logical operation other than the above embodiment.

21 to 23 show a CMOS according to the present invention.
7 illustrates another embodiment of an integrated circuit. In these embodiments, examples are shown in which the present invention is applied to an input circuit that can accurately determine a logic level even with a small input signal amplitude. Generally, as the interface signal level of the CMOS integrated circuit, there are two levels of the CMOS level and the TTL level.
The types are widely used. The minimum value VOHmin of the output high level (VOH) of the signal level for each interface
And the maximum value VOLmax of the output low level (VOL) is C
In the case of MOS level, VOHmin = VCC-0.1 (V) VOLmax = 0.1 (V) In the case of TTL level, VOHmin = 2.4 (V) VOLmax = 0.4 (V) is there. The smaller the amplitude of these signals, the higher the speed and the smaller the charging / discharging current of the load capacitance, but the disadvantage is that the noise margin of the circuit that receives the signals is reduced. An ECL interface used in a bipolar LSI or a biCMOS LSI is known as an interface having a lower amplitude than these. In this case, VOHmin≈−1.0 (V) VOLmax≈−1.6 (V), and the signal amplitude is small at about 0.6V. With the high integration of CMOS integrated circuits and the increase in the number of signals (the number of pins) per integrated circuit, there has been a strong demand for higher speed and lower noise. However, the conventional ECL interface
Since the face is based on bipolar transistors, it is difficult to realize with a CMOS circuit. Since a large bias current is required for the input circuit, power consumption (especially power consumption in standby state) is large. There was a problem. There has been a demand for a low-amplitude interface that overcomes these problems and allows the noise margin to operate widely and stably and to maintain the low power consumption performance that is a characteristic of CMOS.
These new interfaces must meet the following conditions. (1) A signal amplitude of about 1 V or less, and sufficient noise margin. (2) There is almost no current consumption in the standby state (input is above VIHmin or below VILmax). In order to satisfy these conditions, an input circuit that reliably detects a small input signal amplitude and does not consume current in a standby state is required. An example of such an input circuit is
Although shown in FIG. 15 and FIG. 16, other examples will be shown below.

FIG. 21 shows an embodiment of the input circuit of the CMOS integrated circuit according to the present invention. In this embodiment, the two transfer gates of FIG. 15 or 16 are replaced by four transistors TN90, TN91, TP90 and TP91. Reference voltages VRN and VRP are applied to the gates of TN90 and TP91, respectively. VRN
As shown on the right side of the figure, VRP and VRP are set to a value of VRN = VIH + VTN + VTP VRP = VIL-VTN-VTP. Where VIH and VIL
Is the high level and low level of the input signal, VTN and VTP are N
It is the absolute value of the threshold voltage of the channel transistor and the P-channel transistor.

When the voltage of the input IN is lower than VIL, TN91 and TP91 are non-conductive, and TN90 and TP are
90 becomes conductive, and the terminal N60 becomes low level. As a result, the output OUT becomes high level and the terminal N6
1 is a low level. On the contrary, when the voltage of the input IN is higher than VIH, TN91 and TP91 are in the conductive state, T
N90 and TP90 become non-conductive, and the terminal N61 becomes high level. As a result, the output OUT goes low and the terminal N60 goes high. In this way, it is possible to configure an input circuit that responds stably to a small input signal amplitude. Further, since there is no DC current path from VCC to VSS, the current during standby can be made almost zero.

FIG. 22 shows another embodiment of the input circuit of the CMOS integrated circuit according to the present invention. Here, VI
An example of the configuration of the input circuit when L = 0 is shown. TN1 in the figure
00-TN103 is an N-channel transistor, TP10
0 to TP102 are P-channel transistors. TN
A reference voltage VREF1 is applied to the gate of 101, and its source is a CMOS composed of TN100 and TP100.
The inverter is connected. The input is TN103
In addition, the output inverted by the inverter is applied to the TN 102. These TN102, TN103 and TP101,
The TP 102 constitutes a level conversion circuit. The value of the reference voltage VREF1 is VREF1 = VIH + VTN + VTP. VIH is the high level of the input signal, and VTN and VTP are the absolute values of the threshold voltages of the N-channel transistor and the P-channel transistor.

When the voltage of the input IN is 0 (V), the output N65 of the inverter becomes high level. Therefore,
The TN 103 becomes non-conductive, the TN 102 becomes conductive, and the terminal N67 becomes high level and the terminal N66 becomes low level. As a result, the output OUT goes high. On the contrary, when the voltage of the input IN is higher than VIH, the output N65 of the inverter becomes low level. Therefore, TN10
2 becomes non-conductive, TN103 becomes conductive, the terminal N66 becomes high level, and the terminal N67 becomes low level. As a result, the output OUT becomes low level. In this way, it is possible to configure an input circuit that responds stably to a small input signal amplitude. Further, since there is no DC current path from VCC to VSS, the current during standby can be made almost zero.

FIG. 23 shows another embodiment of the input circuit of the CMOS integrated circuit according to the present invention. Here, in FIG.
Similar to the example shown in FIG. 2, a configuration example of the input circuit when VIL = 0 is shown. In the figure, TN110 to TN112 are N-channel transistors, and TP110 to TP113 are P-channel transistors. The reference voltage VREF2 is applied to the gate of the TN111. Input is TN110 and TP1
10 and the source of TP110 and the source of TN111.
Connected. Here, instead of creating an inverted signal of the input, the TN111 and TP110 realize an operation complementary to the N-channel transistor, that is, an operation that conducts when the input is at a low level and does not conduct when the input is at a high level. is doing. These TN110, TN111 and TP110 are further combined with TP111 and TP112 so as to have a level conversion function. The value of the reference voltage VREF2 is VREF2 = VIH + VTN + VTP. VIH is the high level of the input signal, and VTN and VTP are the absolute values of the threshold voltages of the N-channel transistor and the P-channel transistor.

When the voltage of the input IN is 0 (V), T
N110 becomes non-conductive, TN111 and TP110 become conductive, the terminal N70 becomes low level, and the output OUT becomes high level. On the contrary, when the voltage of the input IN is higher than VIH, TN111 and TP110 are in the non-conduction state, T
N110 becomes conductive, terminal N70 is at high level,
The output OUT becomes low level. In this way, it is possible to configure an input circuit that responds stably to a small input signal amplitude. Further, since there is no DC current path from VCC to VSS, the current during standby can be made almost zero.

If the input circuit described above is used, the amplitude of the input signal can be reduced while maintaining a sufficient noise margin, so that the signal can be transmitted at high speed. Further, since the transient current accompanying switching can be reduced, the fluctuation of the power supply voltage can be suppressed and the noise margin can be increased. Further, since the direct current is not consumed in the standby state, it can be applied to the battery operation requiring low power consumption.

Although the present invention has been described in detail with reference to the embodiments, the scope of application of the present invention is not limited to these. For example, here, the case where the LSI is composed of the CMOS transistor and the bipolar transistor has been mainly described, but the LSI using the junction type FET and further the material other than silicon, for example, the LSI in which the element is formed on the substrate such as gallium arsenide, etc. However, it can be applied as it is.

[0062]

According to the present invention, an LSI that operates at high speed can be provided.

[Brief description of drawings]

FIG. 1 is an embodiment for explaining the basic concept of the present invention.

FIG. 2 is a voltage waveform diagram in FIG.

FIG. 3 is an embodiment for explaining the basic concept of the present invention.

FIG. 4 is a conventional circuit.

5 shows a circuit according to the invention for comparison with the circuit of FIG.

FIG. 6 is a definition of an input / output waveform.

FIG. 7 is a characteristic comparison result in the circuits of FIGS. 4 and 5 for showing the effect of the present invention.

FIG. 8 is a characteristic comparison result in the circuits of FIGS. 4 and 5 for showing the effect of the present invention.

FIG. 9 is another embodiment for explaining the basic concept of the present invention.

FIG. 10 is a voltage waveform diagram in FIG.

FIG. 11 is a specific example in which the present invention is applied to a NAND gate circuit.

FIG. 12 is a specific example of a circuit for generating an internal power supply voltage according to the present invention.

FIG. 13 is another embodiment for explaining the basic concept of the present invention using a bipolar transistor.

FIG. 14 shows an example of a VCL, VSL, VCLB, VSLB generation circuit.

FIG. 15 shows another embodiment in which the present invention is used for signal transmission between chips.

FIG. 16 shows another embodiment in which the present invention is used for signal transmission between chips.

FIG. 17 shows another embodiment in which the present invention is applied to a logic circuit.

FIG. 18 shows another embodiment in which the present invention is applied to a logic circuit.

FIG. 19 shows another embodiment in which the present invention is applied to a logic circuit.

FIG. 20 shows another embodiment in which the present invention is applied to a logic circuit.

FIG. 21 shows another embodiment in which the present invention is used in an input circuit.

FIG. 22 shows another embodiment in which the present invention is used in an input circuit.

FIG. 23 is another embodiment in which the present invention is used in an input circuit.

[Explanation of symbols]

CHP1 to CHP9 ... Integrated circuit chips, BLK1 to BLK
K13 ... Integrated circuit block, INV1 to INV19 ... Inverter, DRV1 to DRV18 ... Drive circuit, REC2
~ REC19 ... Receiving circuit, R1 to R13 ... Resistor, Q1
Q21 ... Bipolar transistors, OP1, OP2 ... Differential amplifier circuits, C1 to C12 ... Smoothing capacitors.

Continuation of the front page (56) Reference JP-A-1-135224 (JP, A) JP-A-1-190117 (JP, A) JP-A-2-17714 (JP, A) JP-A-125023 (JP , A) JP-A 4-211515 (JP, A) JP-A 50-58958 (JP, A) JP-A 62-190923 (JP, A) JP-A 60-51327 (JP, A) JP-A 54-69949 (JP, A) JP-A-58-20034 (JP, A) JP-A-63-111720 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03K 19/0185 H01L 21/822 H01L 27/04

Claims (10)

(57) [Claims] 1. A semiconductor device formed on a semiconductor substrate, a first circuit block, a second circuit block, between said first circuit block and the second circuit block
And a signal line for transmitting a signal, the first circuit block and a second 2MOS preparative transistor of N-channel having a first 1MOS transistor and the second threshold voltage of the P channel having the first threshold voltage First including
It receives the output from the CMOS circuit and the first CMOS circuit.
Only the second including a first 4MOS preparative transistor of N-channel having a first 3MOS transistor and the fourth threshold voltage of P-channel having a third threshold voltage for driving the signal line
A CMOS circuit , the absolute value of the third threshold voltage is lower than the absolute value of the first threshold voltage, and the absolute value of the fourth threshold voltage is the second threshold voltage. A semiconductor device having a threshold voltage lower than the absolute value of the threshold voltage and having a characteristic that a subthreshold current flows when the third and fourth MOS transistors each have a source-gate voltage of 0 V. . 2. The semiconductor device according to claim 1, wherein the second CMOS circuit is an inverter in which the third and fourth MOS transistors are connected in series. 3. The first CMOS circuit according to claim 1.
Is a semiconductor device which is an inverter in which the first and second MOS transistors are connected in series. 4. In any of claims 1 to 3, wherein the second circuit block includes a first 5MOS of P-channel having a third threshold voltage which receives the output from the signal line
A semiconductor device having a third CMOS circuit including a transistor and an N-channel sixth MOS transistor having the fourth threshold voltage. 5. The method of claim 4, wherein said first 3CMOS circuit of the second circuit block, said fifth and 6MOS transistor inverter or NAN connected in series
A semiconductor device which is a D gate. 6. A semiconductor device including a plurality of logic circuits formed on a semiconductor substrate and connected in multiple stages, wherein each of the plurality of logic circuits is a P-channel first circuit having a first threshold voltage. It is formed of a first CMOS circuit including one MOS transistor and an N-channel second MOS transistor having a second threshold voltage. In a specific signal transmission path between a plurality of logic circuits connected in multiple stages, Each of the first logic circuit that receives a signal and outputs a second signal and the second logic circuit that receives the second signal and outputs a third signal is a P-channel third MOS having a third threshold voltage. A second CMOS circuit including a transistor and an N-channel fourth MOS transistor having a fourth threshold voltage, wherein the absolute value of the third threshold voltage is the first threshold value. Lower than the absolute value of the voltage, the absolute value of the fourth threshold voltage is lower than the absolute value of the second threshold voltage, the third and fourth MOS transistors, respectively, the source-gate voltage A semiconductor device having a threshold voltage having a characteristic that a subthreshold current flows when is 0V. 7. The semiconductor device according to claim 6, wherein the second CMOS circuit of the second logic circuit is an inverter in which the third and fourth MOS transistors are connected in series. 8. The method of claim 6, wherein said 2CMOS circuit of the second logic circuit, a semiconductor device wherein the third and 4MOS transistors are NAND gates connected in series. 9. The semiconductor device according to claim 6, wherein the second CMOS circuit of the first logic circuit is an inverter in which the third and fourth MOS transistors are connected in series. 10. In any one of claims 6 to 9, one of the plurality of logic circuits of the preceding stage of supplying the first signal to an input node of said first 2CMOS circuit of the first logic circuit A semiconductor device which is an inverter in which the first and second MOS transistors are connected in series.