JP3534609B2 - Semiconductor memory - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a circuit technology suitable for realizing a reduction in cycle time and a reduction in power consumption.
The present invention relates to a technique effectively applied to a write pulse generation method of an OS static RAM.

[0002]

2. Description of the Related Art In a semiconductor memory, when writing is performed, an address signal for designating an address for writing, a data input signal for designating data to be written, and a write pulse for permitting writing are applied. Generally, the write pulse has a predetermined pulse width determined by the response characteristics of the memory cell array, and is applied to the address signal and the data input signal or the clock signal with a predetermined setup time and hold time. There is a need. These timing conditions for the write pulse are becoming more and more strict as the speed of the semiconductor memory becomes faster, and are the most important factor preventing the speedup of the cycle time.

On the other hand, a logical LS for generating a write pulse
A large parasitic capacitance or parasitic inductance exists in the wiring between I and the memory LSI. Therefore, the write pulse formed by the logic LSI is delayed by these parasitic capacitances, etc., and its waveform is deformed. Therefore, it is becoming difficult to form the write pulse that satisfies the above-mentioned strict timing conditions outside the memory LSI.

Then, as a method for solving this problem,
There is a method of providing a write pulse generation circuit inside the memory LSI and generating a write pulse inside the memory LSI in synchronization with a clock signal. According to this method, logical L
Writing can be performed stably and at high speed without being affected by the wiring capacitance or parasitic inductance between the SI and the memory LSI, and the cycle time can be shortened.

As an example of the prior art in which a write pulse generating circuit is provided inside a memory LSI, Japanese Patent Laid-Open No. 63-308 is known.
There is one described in Japanese Patent No. 789. In this conventional technique, the write pulse generating circuit (hereinafter, abbreviated as WPG) is composed of a normal logic circuit. On the other hand, for example, in a bipolar memory cell, an SBD (Schottky Barrier Diode),
It includes elements that are not used in ordinary logic circuits, such as pnp transistors, resistance elements with extremely high sheet resistance, and fine transistors. Furthermore, the circuit configuration of the write circuit that drives the memory cell array is different from that of a normal logic circuit. Therefore, when the element characteristics change due to manufacturing variations, the circuit characteristics of the write pulse generation circuit WPG and the response characteristics of the memory cell array are completely different. For example, even if the junction capacitance of the SBD increases and the inversion time of the memory cell increases, the pulse width of the write pulse generated by the write pulse generation circuit WPG does not change. Therefore, in the prior art, variations in the response characteristics of the memory cell array due to variations in element characteristics are expected in advance, and a margin is given to the pulse width of the write pulse, setup time, and hold time. That is, for example, it is assumed that the time trev from the start of writing until the information in the memory cell is inverted fluctuates by ± 30% due to variations in the characteristics of the elements forming the memory cell. In addition, the pulse width tw of the write pulse generated by the WPG is ± due to variations in the characteristics of the elements forming the logic circuit.
It shall fluctuate by 20%. In the prior art, the WPG and memory cell constituent elements and circuit configurations are completely different.
ev and tw can change completely independently. Therefore, trev is 30
%, And tw may be reduced by 20%. Therefore, to design a WPG so that writing can be performed regardless of how the element characteristics change, the design center value tw (typ) of tw and the center value trev (typ) of trev are 0.8t.
w (typ)> 1.3trev (typ), that is, tw (typ)> 1.
It is necessary to satisfy the relationship of 625 trev (typ). That is, trev changes only 30%, but tw (ty
p) needs to be designed 62.5% larger than trev (typ). Similarly, it is necessary to take a considerably large timing margin for the setup time and the hold time, which is an obstacle to further speeding up the write cycle time.

In order to solve this problem, the inventors have already proposed a semiconductor memory shown in FIG. 7 (Japanese Patent Laid-Open No. 6-1.
95983). FIG. 7 is a diagram showing the configuration of this semiconductor memory, and FIG. 8 is a diagram showing the timing relationship of each signal in FIG. In FIG. 7, WPG is a write pulse generation circuit, WA is a write circuit, CA is a cell array, and BD is a bit line drive circuit. The write pulse generation circuit WPG includes a dummy cell array DCA including a dual port cell DPC and a dummy bit line drive circuit DB.
D, dummy write amplifier DWA, dummy sense amplifier DSA for detecting information of pseudo memory cell, master / slave latch circuit DL, comparison circuit CMP, inverter INV,
It is composed of a pulse width expansion circuit STR and a delay circuit DLY. The dummy cell array DCA includes one dual port cell DPC as a pseudo memory cell including the same circuit configuration as the memory cells C0 to Cn and n dummy cells DC1 to DC.
It consists of n. In this example, the number of cells connected to the dummy bit lines DB and / DB as complementary signal lines is set to the cell array C.
It is equal to A. The selection potential (high potential) VH is applied to the word line of the dual port cell DPC and the dummy cell DC1.
A non-selection potential (low potential) VL is applied to the word lines of DCn to DCn so that writing is performed in the dual port cell DPC. The dual port cell DPC has a memory cell configuration having a read-only port for the memory cell C0. That is, the dual port cell DPC is
It has one write port and one read port,
Reading can be performed even during writing. Since the dual port cell DPC can be constructed by making a slight modification to the main body memory cell, the response to the write operation is almost the same as that of the memory cell. Further, the circuit configurations of the dummy bit line drive circuit DBD and the dummy write amplifier DWA are also the same as those of the bit line drive circuit BD and the write circuit WA. With this structure, the inversion times trev of the memory cells in the dummy cell array DCA and the cell array CA can be made equal, no matter how the element characteristics change. DL is a master-slave latch and takes in data at the rising edge of the clock signal CLK. The dummy write amplifier DWA functions to write the information of the dummy data signal DDIB to the dual port cell DPC when the dummy write signal DWE is "0". The comparison circuit CMP is composed of an EXOR circuit (exclusive OR circuit), and outputs "0" when the input signals match and outputs "1" when the input signals do not match.

The operation of the circuit of FIG. 7 will be described in detail below with reference to FIG. The write pulse generation circuit WPG operates in synchronization with the clock signal CLK, and C is used for one cycle.
It is assumed that it starts from the rise of LK (time t1, t9, t17, ...). When CLK rises (for example, time t1), information of the dual port cell DPC is taken into the latch circuit DL (time t2). In the example of FIG. 8, DPC
Since the first stored information (time t0) is “0”,
The read data signal RD of PC is "0", and the output DDI of the latch circuit is "0" (time t2). Therefore, the output DWE of the comparison circuit CMP becomes "0" (time t3). Further, DDI is inverted by the inverter INV, and its output signal DDIB becomes "1" (time t
3). As a result, the operation of writing "1" in the dummy cell array DCA starts. When the information stored in the DPC is inverted to "1", the dummy sense amplifier detects this and R
Since D changes to "1" (time t6), the comparison circuit CM
The output DWE of P is inverted to "1" (time t7), and the write operation ends. Thus, in this circuit, the dummy write amplifier DWE is set to "0" in synchronization with the CLK signal,
Inversion writing is performed on the dual port cell DPC, the fact that the information is inverted is detected by the dummy sense amplifier DSA, and the dummy write signal DWE is returned to "1" by the comparison circuit CMP. Therefore, the pulse width of the dummy write signal DWE is the sum of the inversion time of the dual port cell DPC and the delay time of the dummy sense amplifier DSA and the comparison circuit CMP. Here, if the delay time of the dummy sense amplifier DSA and the comparison circuit CMP is sufficiently smaller than the cell inversion time, the pulse width of the dummy write signal DWE becomes substantially equal to the inversion time of the dual port cell DPC. The dummy write signal DWE is increased in pulse width by the pulse width expansion circuit STR to have a minimum necessary margin, and delayed by the delay circuit DLY for a desired setup time.
This is supplied to the write circuit WA as the write signal WE.

As described above, in the present circuit, the dummy cell array DCA that responds the same as the cell array CA is provided, and it is detected that the information of the dual port cell DPC is inverted, and the pulse width of the write signal WE is determined. ,
Write pulse width no matter how the device characteristics change
It is possible to equalize the fluctuation amounts of tw and the inversion time trev of the cell. Therefore, it is not possible for trev to increase and tw to decrease as in the prior art. This circuit can greatly reduce the timing margin that was required in the past, so that the cycle time can be shortened.

[0009]

However, in the semiconductor memory using the write pulse generating circuit WPG shown in FIG. 7, the dummy bit lines DB, / DB in the dummy cell array DCA are used.
However, there is a problem that the power consumption becomes large because it is switched twice during one cycle and every cycle. Further, since the write pulse width cannot be made smaller than the sum of the cell inversion time and the delay time of the dummy sense amplifier DSA and the comparison circuit CMP, there is a limit to the reduction of the cycle time.

First, the first problem, that is, the problem of power consumption will be described in more detail. As described above, in the circuit of FIG. 7, the dummy write signal DWE is set to “0” in synchronization with the CLK signal, the dual port cell DPC is inversely written, and the inversion of the information is detected by the dummy sense amplifier DSA. , The dummy write signal DWE is returned to "1" by the comparison circuit CMP. The point to be noted here is that in this circuit, the dummy write signal D is used as a signal for controlling the inversion write to the dual port cell DPC.
This is the point where WE is used. As shown in FIG. 8, the dummy write signal DWE is a signal that switches twice during one cycle of the clock signal CLK. Therefore, the circuits such as the dummy write amplifier DWA driven by the dummy write signal DWE, the dummy bit line drive circuit DBD, and the dummy cell array DCA are all switched twice in one cycle. Especially, the dummy bit line D in the dummy cell array DCA
Since many memory cells are connected to B and / DB and an equivalently large parasitic capacitance is connected, a large amount of power is consumed each time this dummy bit line is charged / discharged.
Further, in a memory or the like configured by CMOS, the power consumed by charging / discharging the bit line occupies 10 to 30% of the power consumption of the entire memory. Therefore, if a large amount of power is consumed each time the dummy bit line is charged / discharged. The power consumption of the whole memory will increase.

Next, the second problem, that is, the limit of shortening the cycle time will be described. As described above, the original purpose of the invention described in JP-A-6-195983 is as follows.
The write pulse width tw is made equal to the cell inversion time trev. However, in the circuit of FIG. 7, the pulse width tw of the dummy write signal DWE is determined by the inversion time trev of the dual port cell DPC and the delay time tp of the dummy sense amplifier DSA.
It is the sum of d (DSA) and the delay time tpd (CMP) of the comparison circuit CMP. That is, tw = trev + tpd (DSA) + tpd (CMP). Here, the dummy sense amplifier DSA and the comparison circuit C
MP delay time tpd (DSA) + tpd (CMP) is cell reversal time
If it is sufficiently smaller than trev, the dummy write signal DWE
The pulse width tw of is approximately equal to the cell inversion time trev.
However, the cell inversion time trev and the delay time tpd (DSA) of the dummy sense amplifier DSA are becoming smaller year by year with the miniaturization of memory cells and memory sense amplifiers, where high performance is the highest priority. The delay time tpd (CMP) of the comparison circuit CMP, which is a so-called logic circuit, has not become so small, and tpd (CMP) cannot be ignored with respect to trev. For this reason, the cycle time of the memory is limited by the delay time tpd (CMP) of the comparison circuit CMP, and the limit of shortening the cycle time is beginning to be seen. This will be described more specifically with reference to FIG. In FIG. 8, the delay time of the master / slave latch circuit DL is Δt, the delay time of the inverter INV is Δt, the sum of the delay times of the dummy write amplifier DWA and the dummy bit line drive circuit DBD is Δt,
The delay period of the dual port cell DPC is 2 × Δt, the delay time tpd (DSA) of the dummy sense amplifier DSA is zero, the delay time tpd (CMP) of the comparison circuit CMP is Δt, and the pulse width in the pulse width expansion circuit STR is Zero extension time, delay circuit DL
This is an operation waveform when the delay time at Y is Δt. Since the cell inversion time trev is the time from the start of writing until the information in the memory cell is inverted, the signal RD becomes "1" after the dummy write signal DWE becomes "0" (time t3) in FIG. Until the time becomes "(time t6),
That is, the cell inversion time trev = 3 × Δt. On the other hand, the width tw of the write pulse is the time from when the write signal WE becomes “1” (time t4) to when the write signal WE becomes “0” (time t8), that is, the width tw of the write pulse tw = 4. × Δt. Therefore, the write pulse width tw
Shows that the pulse becomes longer than the cell inversion time trev by the delay time tpd (CMP) = Δt of the comparison circuit CMP, although the expansion time in the field expansion circuit STR is zero. That is, the cycle time cannot be shortened by this amount.

An object of the present invention is to reduce the number of times of charging / discharging dummy bit lines in a write pulse generation circuit of a semiconductor memory to reduce the power consumption of the entire memory, and to set the write pulse width tw to the cell inversion time trev. And the cycle time of the memory is not limited by the delay time of the comparison circuit CMP.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0014]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, memory cells (C0 to Cn) arranged in a matrix, a write pulse generator (WPG) for generating a write pulse (WE) from a clock signal input from the outside, and the write pulse (WE).
Write control signal (R / W) and data input signal (D
In the semiconductor memory having a write circuit (WA) which receives I) and writes data to the memory cell, the write pulse generation circuit is the same as the frequency divider (FD) that divides the clock signal and the memory cell. Pseudo memory cell (DP) that includes the configuration and simulates the response characteristics of the memory cell
C) and a phase comparison circuit (CMP) that compares the phase of the signal
And inputting the information of the divided signal output from the divider to the pseudo memory cell, and comparing the phase of the response output signal of the pseudo memory cell with the phase of the divided signal by the phase comparison circuit. By doing so, a write pulse is generated.

According to the above, as a signal for controlling the inversion writing to the pseudo memory cell, conventionally, two signals are generated during one cycle.
While the dummy write signal that switches once is used, the frequency dividing signal that switches only once in one cycle is used in the present invention. Therefore, charging / discharging of the dummy bit line to which a large parasitic capacitance is connected also occurs only once in one cycle. Therefore, according to the present invention, the power consumed by charging / discharging the dummy bit line is
Can be 2.

Further, according to the present invention, the divided signal obtained by dividing the clock signal and the output of the pseudo memory cell are compared by the comparison circuit, and the dummy write signal as the comparison result is set to "1".
In parallel with this, the pseudo write is performed to the pseudo memory cell by the frequency division signal, and the dummy write signal is returned to "0" according to the comparison result of the comparison circuit of the inversion signal and the frequency division signal.
Therefore, the pulse width of the dummy write signal does not include the delay time of the comparison circuit as in the conventional case. Therefore, by using the present invention, the cycle time can be shortened by the delay time of the comparison circuit as compared with the conventional case.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 6 shows an example of a semiconductor memory according to the present invention as a whole. The semiconductor memory 1 includes a cell array CA, a row decoder / word driver 3, a row address buffer 4, a column switch circuit 5, a column decoder 6, a column address buffer 7, a write circuit WA having a write amplifier, a read circuit 9, a write pulse generation circuit. With WPG. The cell array CA has a large number of memory cells whose select terminals are connected to word lines and whose data input / output terminals are connected to complementary bit lines, and these memory cells are arranged in a matrix. The row address buffer 4 converts the row address signal into an internal complementary address signal, and receives the row decoder and word driver 3
Decode the internal complementary address signal and drive the word line selected thereby to the select level. The column address buffer 7 converts the column address signal into an internal complementary address signal, and the column decoder 6 decodes this. The complementary bit lines are commonly connected to the complementary common data line via the column switch circuit 5, and which bit line is conducted to the complementary common data line is determined by a column selection signal obtained from the decoding result of the column decoder 6. . The complementary common data line is connected to the write circuit WA and the read circuit 9. When the read operation is instructed by the read / write signal R / W, the read circuit 9 outputs the data on the complementary common data line to the outside as the data output signal D0. The write pulse generation circuit WPG uses the write pulse signal W based on the clock signal CLK input from the outside.
Generate E. The write circuit WA receives the write pulse signal WE, the read / write signal R / W, and the write data signal DI from the outside, and controls the write operation to the memory cell. When the write operation is instructed by the read / write signal R / W, the write circuit WA controls the write operation to the memory cell according to the pulse width of the write pulse signal WE.

The semiconductor memory 1 is formed on one semiconductor substrate such as single crystal silicon.

FIG. 1 shows a detailed example of the write pulse generation circuit WPG of the semiconductor memory according to the present invention. FIG. 2 shows an example of the operation timing of the write pulse generation circuit WPG in FIG.

In FIG. 1, WPG is a write pulse generation circuit, WA is a write amplifier, CA is a cell array, and BD.
Is a bit line drive circuit. Write pulse generation circuit W
PG is a dummy cell array DCA including a dual port cell DPC, a dummy bit line drive circuit DBD, a dummy write amplifier DWA, a dummy sense amplifier DSA for detecting information of a pseudo memory cell, a master slave latch circuit D.
It has L, a phase comparison circuit CMP, an inverter INV, a pulse width expansion circuit STR, and a delay circuit DLY. The dummy cell array DCA includes one dual-port cell DPC including the same circuit configuration as the memory cells C0 to Cn and n dummy cells DC1 to DCn. In this example, the number of cells connected to the dummy bit lines DB and / DB is set equal to that of the cell array CA. The selection potential (high potential) VH is applied to the word line of the dual port cell DPC and the dummy cell D
Unselected potential (low potential) VL is applied to the word lines of C1 to DCn.
Is applied to write data to the dual port cell DPC. The dual port cell DPC has a dedicated read port for the memory cell C0. For example, the data input / output node of the memory circuit of the dual port cell is connected to the dummy bit lines DB and / DB via the selection transistor switch-controlled by the word line,
The read transistor whose selection terminal is connected to the data input / output node is connected to the input terminal of the dummy sense amplifier DAS. The circuit configurations of the dummy bit line drive circuit DBD and the dummy write amplifier DWA are also the bit line drive circuit B.
It is configured exactly the same as the D and write circuit WA.

Write pulse generation circuit W shown in FIG.
PG is a frequency divider FD that divides the clock signal CLK.
And inputting the divided signal DDI which is the output of the frequency divider FD to the dual port cell DPC, and the phase of the response output signal RD of the dual port cell DPC and the phase of the divided signal DDI. The write pulse WE is generated by the comparison by the comparison circuit CMP. here,
The dummy write amplifier DWA uses the dummy write signal DDW.
When E is "0", the circuit functions to write the information of the dummy data signal (divided signal in this example) DDI to the dual port cell DPC. In this example, the signal DDWE is always set to "0". Keep it. Therefore, actually, the write operation is started as soon as the dummy data signal (divided signal in this example) DDI is switched. The phase comparison circuit CMP is composed of an EXOR circuit (exclusive OR circuit), and outputs “0” when the input signals match and outputs “1” when the input signals do not match.

The operation of the circuit shown in FIG. 1 will be described in detail with reference to FIG. The circuit shown in FIG. 1 operates in synchronization with the clock signal CLK, and for one cycle, the clock signal CLK rises (time t1, t9, t17, ...).
Shall begin with. When the clock signal CLK rises (for example, time t1), the frequency division signal DDI which is the output of the frequency divider FD switches. That is, the divided signal DDI becomes "0" at time t2. On the other hand, since the first state (time t0) of the divided signal DDI is "1", the read data signal RD is "1" at the time t2 corresponding to this state. Therefore, the output DWE of the phase comparison circuit CMP becomes "1" (time t3). Further, since the dummy write signal DDWE is always “0”, the frequency division signal DD
When I becomes "0" at time t2, the write operation of "0" to the dual port cell DPC immediately starts. When the stored information of the dual port cell DPC is inverted to "0", the dummy sense amplifier DSA detects this and the signal RD changes to "0" (time t5). Therefore, the output signal DWE of the phase comparison circuit CMP is detected. Becomes "0" (at time t
6), the write operation ends. As described above, in the write pulse generation circuit WPG of FIG. 1, the divided signals DDI and RD obtained by dividing the clock signal CLK are compared by the phase comparison circuit CMP to set the signal DWE to “1”, and in parallel to this, The dual port cell DPC is inversely written by the signal DDI, the fact that the information is inverted is detected by the dummy sense amplifier DSA, and the phase comparison circuit CMP outputs the signal DWE.
Is returned to "0". Therefore, the pulse width of the signal DWE is the sum of the inversion time of the dual port cell DPC and the delay time of the dummy sense amplifier DSA. Here, since the delay time of the dummy sense amplifier DSA is sufficiently smaller than the cell inversion time, the pulse width of the signal DWE becomes almost equal to the cell inversion time. This signal DWE is applied to the pulse width expansion circuit S
The pulse width is increased by TR to provide a necessary minimum margin, the delay circuit DLY delays it by a desired setup time, and this is supplied to the write circuit WA as a write pulse WE.

Next, the write pulse generation circuit WP of FIG.
It will be explained that by adopting G, the conventional problems described above are solved.

First, the first problem, that is, the problem of power consumption will be described. As already mentioned, in this example,
The signal DDWE input to the dummy write amplifier DWA is always "0". Therefore, the write operation is started immediately after the division signal DDI is switched. In other words, in this example, the divided signal DDI is used as a signal for controlling the inversion writing to the dual port cell DPC (the signal DWE was used conventionally). As shown in FIG. 2, the divided signal DDI is a signal that switches only once in one cycle (in contrast, the signal DWE switches twice in one cycle). Therefore, all the circuits such as the dummy write amplifier DWA, the dummy bit line drive circuit DBD, and the dummy cell array DCA driven by the divided signal DDI are switched only once in one cycle. Therefore, charging / discharging of the dummy bit line DB or / DB to which a large parasitic capacitance is connected also occurs only once in one cycle as shown in FIG. That is, in this example, the power consumed by charging / discharging the dummy bit line can be halved as compared with the conventional one.

Next, the second problem, that is, the reduction of the cycle time will be described. As described above, in the circuit of FIG. 1, the divided signal DDI obtained by dividing the clock signal CLK is used.
The signal DWE is set to "1" by the phase comparison circuit CMP and the dual port cell DPC by the divided signal DDI in parallel therewith.
Then, the dummy sense amplifier DSA detects that the information is inverted, and the phase comparison circuit CMP returns the signal DWE to "0". Therefore, the signal DWE
Pulse width tw of dual port cell DPC inversion time tr
ev becomes the sum of the delay time tpd (DSA) of the dummy sense amplifier DSA, and the delay time of the phase comparison circuit CMP is not included as in the conventional case. That is, tw = trev + tpd (DSA) (previously tw = trev + tpd (DSA) + tpd (CMP)). Therefore, even if the delay time tpd (CMP) of the phase comparison circuit CMP becomes so large that it cannot be ignored with respect to the cell inversion time trev, tw will not be affected in this example. This will be described more specifically with reference to FIG. In FIG. 2, as in FIG. 8, the delay time of the frequency divider FD is Δt, the sum of the delay times of the dummy write amplifier DWA and the dummy bit line drive circuit DBD is Δt, and the delay period of the dual port cell DPC is 2 ×.
Δt, the delay time tpd (DSA) of the dummy sense amplifier DSA is zero, the delay time tpd (CMP) of the phase comparison circuit CMP is Δt, the pulse width expansion time in the pulse width expansion circuit STR is zero, and the delay circuit DLY is 2 is an operation waveform of FIG. 1 when the delay time is Δt. Since the cell inversion time trev is the time from the start of writing until the information in the memory cell is inverted, the frequency division signal DDI becomes "0" (time t2) in FIG. 2 and the signal RD becomes "0". Becomes (time t
Time until 5), that is, cell reversal time trev = 3 ×
Δt. On the other hand, the write pulse width tw is the time from when the write pulse signal WE becomes “1” (time t4) to when the signal WE becomes “0” (time t7), that is, the write pulse width tw = It becomes 3 × Δt. Therefore, the write pulse width tw becomes equal to the cell inversion time trev (conventionally, tw = trev + Δt). Therefore, in this example, the cycle time can be shortened by Δt as compared with the conventional case.

FIG. 3 shows still another example of the write pulse generation circuit WPG of the semiconductor memory according to the present invention. FIG. 4 shows the operation timing of the circuit of FIG. 3 when the control signal C1 to be described later is “1” and C2 is “1” in the write pulse generation circuit WPG of FIG.

The configuration of FIG. 3 differs from that of FIG. 1 in that switches SW1 and SW2 and a control terminal S / R for set / reset are added to a frequency divider FD, a gate MDL as a delay circuit, An OR circuit OR, an AND circuit AND, a selector SEL is added, a pulse width expansion circuit STR is inserted at a different position, and the dummy cell array DCA is composed of only dual port cells DPC in order to simplify the circuit. In addition, the dummy write amplifier DWA and the dummy sense amplifier DSA are removed. The operation of this circuit is basically the same as the operation of the circuit of FIG. 1 when the control signal C1 is “1” and C2 is “0”, and therefore only the points different from FIG. 1 will be described below.

The switch SW1 is a switch for switching between a pulse generated by the write pulse generating circuit WPG and a write pulse EXWE input from the outside for testing a memory, for example. The switch SW2 is a switch for measuring the delay time of the circuits forming the write pulse generating circuit WPG and checking how much the width of the write pulse generated by the write pulse generating circuit WPG is actually. That is, when the switch SW2 is switched, a set signal is input to the set terminal S of the frequency divider FD, and the output DDI of the frequency divider FD is fixed to "1", the circuit forming the write pulse generation circuit WPG is closed loop, That is, a ring oscillator is configured, and the delay time of the circuit can be known by measuring the oscillation frequency of this ring oscillator.

Next, in the gate MDL, the OR circuit OR, the AND circuit AND, and the selector SEL, when the response time of the dual port cell DPC is smaller than the delay time of the gate MDL, the width of the write pulse is determined from the delay time of the gate MDL. It is a circuit for doing so. As described above, the response time of the cell is decreasing year by year, whereas the delay time of the so-called logic circuit is not decreasing so much. Therefore, if the cell response time becomes too small, the write pulse signal having a pulse width equal to the cell response time may disappear inside the write pulse generation circuit WPG. That is, there is a possibility that the logic circuit forming the write pulse generation circuit WPG cannot follow a signal having a small pulse width and the signal does not propagate normally. Therefore, in this example, the control signal C1 is "
When 1 "and C2 are" 1 ", OR circuit OR, AND circuit A
In the ND and the selector SEL, when the response time of the dual port cell DPC is shorter than the delay time of the gate MDL, the width of the write pulse is determined from the delay time of the gate MDL (see FIG. 4). Therefore, the gate M
By appropriately setting the delay time of DL, it is possible to prevent the write pulse signal from disappearing inside the write pulse generation circuit WPG.

Finally, the reason for changing the insertion position of the pulse width expansion circuit STR is that the comparison circuit C is as shown in FIGS.
This is because if the pulse width expansion is performed after MP, not only the pulse width expansion circuit becomes complicated, but also the timing of sending the write pulse to the write circuit WA is delayed. That is, when the pulse width expansion circuit is inserted before the comparison circuit CMP as shown in FIG. 3, the pulse width expansion circuit may be a simple delay circuit, and the write pulse may be added to the write circuit W.
The timing of sending to A will not be delayed.

FIG. 5 shows an example in which the circuit of FIG. 3 is further embodied. For example, the logic gate of FIG.
(Logic) circuit is shown as an example. Therefore, the operation of this circuit is basically the same as the operation of the circuit of FIG. However, the characteristic of the example of FIG. 5 is that all the signal paths directly connecting the frequency divider FD to the comparison circuit CMP and the signal paths connecting the frequency divider FD to the comparison circuit CMP via the dual port cell DPC. The point is that they are connected by two complementary signal lines. As described above, in the present invention, 1 is set as the signal for controlling the inversion writing to the dual port cell DPC.
A frequency division signal that is switched only once during the cycle is used. Therefore, a cycle in which the dual port cell DPC is driven by the frequency division signal that switches from "1" to "0",
On the contrary, there is a cycle for driving the dual port cell DPC with the frequency division signal which switches from "0" to "1" (for example, the time t2 of the DDI signal of FIG. 2 or FIG. 4).
And switching at time t10). On the other hand, the write pulse width must be the same in odd cycles and even cycles. In order to satisfy this condition in the example of FIG. 5,
All signal paths connecting the frequency divider FD to the phase comparison circuit CMP are connected by two complementary signal lines. By doing so, the operation of each circuit becomes completely symmetrical when the divided signal is switched from "1" to "0" and when it is switched from "0" to "1", and the write pulse width is even even in odd cycles. The same goes for cycles.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, the write control signal is not limited to the read / write signal R / W, but may be an appropriate signal. Further, the present invention is not limited to the bipolar RAM, but can be applied to various semiconductor memories such as a MOS static RAM. Further, it can be applied to an on-chip memory of a microcomputer or the like.

[0035]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, conventionally, a dummy write signal that switches twice in one cycle is used as a signal for controlling inversion writing to a pseudo memory cell, whereas in the present invention, it is once in one cycle. A frequency-divided signal that only switches is used. Therefore, charging / discharging of the dummy bit line connected to a large parasitic capacitance occurs only once in one cycle, so that the number of charging / discharging of the dummy bit line in the write pulse generation circuit of the semiconductor memory can be reduced. The power consumption of the entire memory can be reduced.

Further, according to the present invention, the dummy write signal is set to "1" by the divided signal obtained by dividing the clock signal and the comparator circuit, and in parallel with this, the divided signal is inverted and written in the pseudo memory cell, and its inversion is performed. The dummy write signal is returned to "0" by the signal and the comparison circuit. Therefore, the pulse width of the dummy write signal does not include the delay time of the comparison circuit as in the conventional case. Therefore, the write pulse width can be made equal to the cell inversion time, and the memory cycle time can be prevented from being limited by the delay time of the comparison circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a detailed example of a write pulse generation circuit of a semiconductor memory according to the present invention.

FIG. 2 is a timing chart showing an example of operation timing of the write pulse generation circuit of FIG.

FIG. 3 is a block diagram showing still another example of the write pulse generation circuit of the semiconductor memory according to the present invention.

4 is a timing chart showing an example of the operation timing of the circuit of FIG. 3 when the control signal C1 is "1" and C2 is "1" in the write pulse generation circuit of FIG.

5 is a circuit diagram showing an example in which the circuit of FIG. 3 is embodied as an ECL circuit.

FIG. 6 is a block diagram generally showing an example of a semiconductor memory according to the present invention.

FIG. 7 is a circuit diagram showing an example of a conventional write pulse generation circuit.

8 is a timing chart showing an example of operation waveforms of the circuit of FIG.

[Explanation of symbols]

1 Semiconductor memory WPG write pulse generation circuit, CA cell array C0 to Cn memory cells BD bit line drive circuit WA writing circuit DCA dummy cell array DPC dual port cell (pseudo memory cell) DC1 to DCn Dummy cells DBD dummy bit line drive circuit DWA dummy write amplifier DL master-slave latch circuit FD frequency divider CMP phase comparison circuit INV inverter STR pulse width expansion circuit DLY delay circuit R / W write control signal DI data input signal

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuo Kanaya 1-280 Higashi Koikekubo, Kokubunji, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Tsuru Yamazaki 1-280 Higashi Koikeku, Tokyo Kokubunji City Hitachi, Ltd. Central Research Laboratory (72) Inventor Kenichi Ohata 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. (72) Inventor Fumihiko Arakawa 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. (72) Inventor Takeshi Kusunagi 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. (72) Inventor Keiichi Kishita 3 Incorporated Hitachi, Ltd. Device Development Center, 6-16 Shinmachi, Ome City, Tokyo (72) Nishiyama Masahiko 6-chome, Shinmachi, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center at 3 No. 16 (72) Inventor Kunihiko Yamaguchi 5-22-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitachi Ultra SII Systems Inc. (72) Invention Tetsuya Saeki 5-22-1 Kamisuihoncho, Kodaira-shi, Tokyo Within Hitachi Cho-LS Systems Co., Ltd. (56) Reference JP-A-6-195983 (JP, A) JP-A-7- 65584 (JP, A) JP-A-7-153275 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 11/41-11/419

Claims (4)

(57) [Claims] 1. Memory cells arranged in a matrix,
A semiconductor memory comprising: a write pulse generation circuit that generates a write pulse from a clock signal input from the outside; and a write circuit that receives the write pulse, a write control signal, and a data input signal and writes data to the memory cell. The write pulse generation circuit includes a frequency divider that divides the clock signal, a pseudo memory cell that includes the same circuit configuration as the memory cell and simulates the response characteristics of the memory cell, and a phase comparison circuit that compares the phases of signals. Information of the frequency-divided signal output from the frequency divider is input to the pseudo memory cell, and the phase of the response output signal of the pseudo memory cell and the phase of the frequency-divided signal are compared by the phase comparison circuit. A semiconductor memory characterized in that a write pulse is generated thereby. 2. A signal path directly connecting the frequency divider to the phase comparison circuit or a signal path connecting the frequency divider to the phase comparison circuit via a pseudo memory cell has at least a part of two lines. 2. The semiconductor memory according to claim 1, wherein the semiconductor memory is connected by complementary signal lines. 3. The latch circuit, wherein the frequency divider circuit latches input data in synchronization with a predetermined change of a clock signal,
3. The semiconductor memory according to claim 1, comprising an inverter connected in antiparallel to the latch circuit. 4. A delay circuit is provided in parallel with the pseudo memory cell, and when the response time of the pseudo memory cell is smaller than the delay time of the delay circuit, the width of the write pulse is determined by the delay time. The semiconductor memory according to claim 1, wherein: