JP3534640B2 - Address translation method and apparatus - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address translation method and device, for example, an ATM (Asynchronous Transfe
r Mode: Asynchronous transfer mode) This is applicable when converting the routing information of a cell for each network node transmitting the ATM cell.

[0002]

2. Description of the Related Art Conventionally, as this type of address conversion method and apparatus, there are those described in the following documents 1 and 2.

Reference 1: "ATM Internetworking" (Nikkei BP Publishing Center) Anthony Alles, Translated by Tsunemi Shitara Reference 2: Reference of "Communication Protocol Encyclopedia" (Ascii Publishing Co., Ltd.) Hideyuki Kasano, Multimedia Communication Research Group These References 1, As described in Section 2, an ATM network is composed of a collection of ATM switches. These ATM switches are interconnected by point-to-point ATM links or interfaces.

Further, depending on the arrangement position on the network, the ATM switch supports two types of interfaces, that is, a user network interface (UNI) and a network node interface (NNI).

In the ATM network, it is necessary to prepare a virtual circuit on the ATM network prior to data transfer.

The ATM circuit has a virtual path identified by a virtual path identifier (VPI),
There are two types of virtual channels identified by a VPI and Virtual Channel Identifier (VCI) pair.

A virtual path (VP) is a virtual path
A bundle of channels (VCs), each VC having a common V
Transparently exchanged over ATM networks based on PI. However, both VPI and VCI have only local implications on a particular link, ie, a particular switch on an ATM network.

Therefore, in each switch, VC
The routing bits of I and VPI are converted so that they are convenient for themselves.

To perform such local address translation, the ATM switch usually has its own local translation table (LT table).

There are various possible configurations of the LT table, but at least the recognized VCI or VP is recognized.
It has a function of retrieving the connection value on the output side based on the connection value on the input side of the cell received on the I link. Since the connection value on the output side specifies the output port of the connection and the VC on the output side, the ATM switch sends cells in response to this.

The usage of the LT table is PVC.
There are two (Permanent Virtual Connections: fixed connection at the other end) and SVC (Switched Virtual Connections: connection selected at the other end).

Generally, PVC is a setting for a connection that is used for a medium to long term such as a leased line, and all ATMs existing on a transmission line between a source ATM system and a destination ATM system. This is done for the switch. Normally, PVC requires a manual setting operation from the outside by a network administrator.

In the PVC, once set, it is not possible to automatically reselect the path (the ATM switch to be transmitted) unless a new setting operation is performed.

On the other hand, SVC is a connection that is automatically established by a signaling protocol.
Manual operation at the time of establishment such as PVC is not required, and the connection can be released when not in use, or the route can be reselected according to the state of the network.

In principle, both of them can operate a 16-bit VC for each VP.

For example, VPI is 8 in the case of UNI.
Bit, NNI is expressed by 12-bit numerical value, V
CI is represented by a 16-bit numerical value. Therefore one V
P can accommodate up to 65,536 VCs.

[0017]

However, in a system using the entire resource area of VCI consisting of 16 bits for each VPI as described above, since resource allocation of VCI must be managed for each VP, hardware There is a problem that the amount becomes large.

In the case of UNI, for example, the 8-bit V
It is said that the PI and the LT table that can handle all the 24 routing bits consisting of the 16-bit VCI in the same way have to deal with 2 ²⁴ kinds of input bit patterns, resulting in a large scale hardware. That is.

With such large-scale hardware, 2
^Although it is possible to identify ²⁴ types of packets, this is an excessive function in the actual situation of the network, and in actual systems, it is rare that a combination of such a large number of identifiers is required, and even if the above-mentioned specifications are implemented. Often wasted.

Also, the number of bits that can be used for VCI is limited depending on the connected device.
There is also a problem that it is necessary to consider this limitation when allocating.

The above-mentioned packet means a message which is a set of a series of ATM cells transmitted in time series, and one connection is occupied on the corresponding link during the transmission of one packet. .

[0022]

In order to solve such a problem, a first invention is an address field used by a transmitting device which supports a predetermined protocol layer to select a transmission path of an input protocol unit signal. In the address conversion method for determining the conversion destination address in the state of the address field of the output protocol unit signal corresponding to the input protocol unit signal in accordance with the conversion source address in the state of Only part of the address field set above is converted as transmission route selection data, and the other part is transmitted between the transmission side transmission device and the reception side transmission device connected thereto. Converted as message identification data used to identify the message to be transmitted, and In a di-identification data, and wherein the configuring the destination address.

According to a second aspect of the present invention, a transmitting side transmission device supporting a predetermined protocol layer, based on a conversion source address which is a state of an address field used for selecting a transmission path of an input protocol unit signal, In an address translation device that determines a translation destination address that is a state of an address field of an output protocol unit signal corresponding to the input protocol unit signal, in the address field set on the protocol unit signal for selecting the transmission path, , Part of which is converted as transmission route selection data, and the other part of which is used as message identification data used for identifying a message transmitted between the transmission side transmission device and the reception side transmission device connected thereto. By converting the transmission route selection data and the message identification data,
It is characterized in that it is provided with an address processing means for forming the conversion destination address.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION (A) Embodiment Hereinafter, the address translation method and device according to the present invention will be
The embodiment will be described by taking as an example the case of being applied to L (ATM Adaptation Layer) 5.

In AAL3 / 4, MID (MessageID)
Identification of AAL connection for each packet using (CS
Message identification), but in AAL5, A
There is no AL3 / 4 MID.

Therefore, the following first through first corresponding to AAL5
In the fourth embodiment, only the VPI is used to identify the source and destination user terminals (transmission route selection) by software, and the VCI is assigned to each packet (that is, to each connection), A function corresponding to the MID is given.

The VPI processing by the software is
It may be 1 VPI per subscriber (1 ATM terminal).

(A-1) Configuration of the First Embodiment FIG. 2 shows the address conversion unit 10 of the present embodiment. The address conversion unit 10 is installed in an ATM switching device such as the CLS (connectionless server) and the ATM switches 11 and 13 shown in FIG. 4, and functions as a VC management mechanism.

The edge nodes 14 and 15 in FIG. 4 are, for example, UNI devices corresponding to PBXs (private branch exchanges) and routers, and have ATM cell multiplexing / demultiplexing functions and switching functions. Then, switching (exchange) of ATM cells, that is, address conversion is performed along with reconfiguration of overhead such as selection and distribution of SDH frame overhead in the UNI device.

Therefore, each of the ATM terminals 16 and 17 accommodated in the edge nodes 14 and 15 may be plural.

In this case, the address conversion unit 10 can also be mounted on the edge nodes 14 and 15. these,
The edge nodes 14 and 15, the CLSs 11 and 12,
The ATM switch 13 and the like are generically called a transmission device.

In FIG. 2, the address conversion unit 10 has V
CI management unit 21, VCI management RAM 22, free VC
It is composed of an I head register 23 and an empty VCI final register 24.

The VCI management unit 21 includes a VCI management RAM 2
2. A control device that manages VCI resources by controlling the empty VCI start register 23 and the empty VCI final register 24.

The VCI resource is a VCI contained in the address conversion unit 10.

The management of VCI resources is based on the set VC
There is an aspect similar to bandwidth management in that the packet is transmitted over and the bandwidth of the link (link transmission capacity) is occupied.
This is a concept different from bandwidth management in that it does not occupy a bandwidth during a period when an ATM cell forming the packet is not transmitted even within a period in which a certain VC is set.

The VCI management RAM 22 is a temporary table corresponding to the LT table, the details of which are shown in FIG.

The temporary table is a PDU (Protocol
It is generally used to temporarily hold information necessary for assembling a PDU from a cell and add the information to the cell when the data unit is transferred.

In FIG. 3, a 32-bit address (hexadecimal notation) is displayed in total in the RAM (random access memory) 22, but the upper 16 bits (corresponding to VPI, all "0"). Is processed by the software described above, and is not processed by the address conversion unit 10. Therefore, it is necessary to have a 16-bit address space corresponding to the lower 16 bits (corresponding to the UNI and NNI VCI). become.

Each memory address has a VCI of 1
16-bit data is stored corresponding to 6 bits. The 16 bits correspond to the maximum available VCI.

In the initial setting of this embodiment, the address and the data are associated with each other by setting the data of each address to a value obtained by adding “+1” to the corresponding address.

The empty VCI start register 23 is a 32-bit register, and the lower 16 bits thereof are bits processed by the address conversion unit 10 of this embodiment. The value of the lower 16 bits stored in this register corresponds to the VCI of the connection (message) set next.

The empty VCI final register 24 is also a 32-bit register, the lower 16 bits of which are subject to processing by the address conversion unit 10. The lower 16-bit value stored in this register is the V of the released connection.
Corresponds to CI.

The operation of this embodiment having the above-mentioned structure will be described below. (A-2) Operation of First Embodiment First, as described above as the initial setting, the VCI management RA
A value obtained by adding 1 to the corresponding address is stored in each address in M22. However, the final address is 0000 FF
Nothing is written to FF (H). FIG. 3 is a memory map in this initial state.

The initial value of the empty VCI start register 23 is 0000 0000 (H), and the initial value of the empty VCI final register 24 is 0000 FFFF (H) (VC
This is the final address of the I management RAM 22).

The operation of the address conversion unit 10 is shown in the flowchart of FIG. FIG. 1A shows a VCI allocation (connection setting) operation, and FIG. 1B shows a VC
The operation of releasing I (release of connection) is shown.

In FIG. 1 (A), V from software
When the CI allocation processing is instructed, first, the VCI management unit 2
1 reads the empty VCI start register 23 and the empty VCI final register 24 (601) and compares them (6)
02).

If they match, it is determined that there is no space,
Error processing is performed (606).

When error processing is performed, VCI is not assigned, so that the packet includes the ATM switch 13 and CLS1 in which the address conversion unit 10 is mounted.
It will not be transmitted beyond 1, 12 and so on.

However, this coincidence not only occurs in hardware when all 16-bit VCIs are actually in use, but may also exist, for example, due to VCI loss in the first cell of the packet, transmission error, or the like. Not VP
When receiving I (VCI) or recognizing congestion or the like, the software may operate to make them coincide with each other.

In addition, the software may be matched when it is desired to limit the number of VCIs to be used.

The VCI management unit 21 allocates the value recorded in the empty VCI head register 23 as the VCI on the output side to the area corresponding to the VCI of the routing field of each ATM cell forming the corresponding packet whose transmission has been started. (Write) (603).

The contents of the processing performed in the step 603 are notified to the above-mentioned software which manages the VPI, if necessary. This is because it is more rational to make the final decision on the routing field in software that is relatively slow but has high functionality.

Next, the VCI management unit 21 reads the address of the VCI management RAM 22 corresponding to the value recorded in the empty VCI start register 23 (604), and rewrites the empty VCI start register 23 with the value recorded at that address. (605).

On the other hand, FIG. 1 showing a VCI release procedure.
The flow of (B) is started by the software instructing the release of the VCI.

In FIG. 1B, the VCI management unit 21 first reads the value recorded in the empty VCI final register 24 (607), and then releases it to the address of the VCI management RAM 22 corresponding to the value. The value of VCI is written (608).

Finally, the freeing process is completed by rewriting the empty VCI final register to the value of VCI for freeing (609).

By these processes, the unused VCIs are managed in a chain form, and it is possible to prevent the VCIs in use from being assigned in duplicate.

Further, it is not necessary to release the RAMs in the order of allocation, and the RAMs 22 are registered in the RAM 22 in the order of being released.
The chains will be registered in the order registered in and will be newly allocated.

(A-3) Effects of First Embodiment As described above, according to the present embodiment, AA without MID is used.
Even if L5 is used, by providing the VCI with the MID function, it becomes easy to manage the transfer processing in packet units.

Further, the VPI is separately managed by software or the like, and only the VCI resource is centrally managed by the address translation unit 10, so that the address translation unit is compared with the case where the address translation is performed using all the bits of the VPI and VCI. The hardware amount of 10 can be reduced.

(B) Second Embodiment In the first embodiment, VC is mainly performed by software.
It is characterized in that the number of uses of I is limited by changing the setting value of the register in advance, mainly by the hardware and flexibly and with a low load on the software.

Other points, for example, the VCI having a function corresponding to the MID and the use of 1 VPI per subscriber (1 ATM terminal) may be the same as those in the first embodiment.

(B-1) Configuration and Operation of Second Embodiment FIG. 5 shows the address conversion unit 30 of this embodiment. The transmission device equipped with the address conversion unit 30 is the CLS1 of FIG.
4 and the like may be exactly the same as the address conversion unit 10 of the first embodiment.

In FIG. 5, the address conversion unit 30 is composed of a pointer bit 71, a VCI management unit 72, a VCI management RAM 73, an unused number register 74, a read pointer register 75, and a write pointer register 76. ing.

The VCI management unit 72 is the VCI management unit 2
The control device is the same as that of 1.

The configuration of the VCI management RAM 73 itself is
As shown in FIG. 6, the hardware is exactly the same as the VCI management RAM 22.

In this embodiment, VCI resource management is performed by the VCI management RAM 73, the read pointer register 75, and the write pointer register 76. V
The CI management RAM 73 stores usable VCI values.

As shown in FIG. 7, the read pointer 75 and the write pointer 76 are respectively the VCI management RAM 73.
This is a register that specifies the upper address.

The address designated by the read pointer register 75 is the address where the VCI to be used (read) next is stored, and the address designated by the write pointer register 76 is the VC which is released next (written).
This is the address for storing I.

The pointer bit 71 is the read pointer 7
5 is a flip-flop (FF) for determining whether all the VCI resources are available when the position (address designation) of the write pointer 76 and the position of the write pointer 76 match, or an empty state where no VCI is available at all.

This match can occur when no VCI resource is used and all are available, or when all VCI resources are used and no more can be used.

The initial value of the pointer bit 71 is "1", which is cleared to "0" when the read pointer 75 is added (incremented) and set to "1" when the write pointer 76 is added (incremented). .

The value of the unused number register 74 is the available V
The number of CIs is shown. This value is the write pointer 76
And the value of the read pointer 75. The value of the unused number register 74 is 1 bit more than the value of the read pointer / write pointer. However, when the values of the write pointer 76 and the read pointer 75 match, the value of the pointer bit is the most significant bit. Otherwise, it is "0" otherwise.

At the time of initial setting, the maximum number of VCIs to be used is written in the VCI management RAM 73. For example, as shown in FIG. 6, data having the same value as the lower 16 bits of the address may be written in the corresponding address.

In this embodiment, by setting the value of the read pointer 75 and the value of the write pointer 76, it is possible to set the range of usable VCI values and the number of simultaneously usable VCIs.

FIG. 8 is a flow chart showing the operation of this embodiment.

In FIG. 8B, the VCI allocation process instructed by the software is performed as follows.

First, from the information in the unused number register 74, V
The CI management unit 72 determines whether or not there is a free VCI (10
01).

If there is no VCI vacancy, it is regarded as a VCI hunt error and is subject to error processing (1006).

The content of this error processing is the same as that of the error processing in the first embodiment described above.

If there is a free VCI, the VCI management unit 72
First reads the read pointer register 75 (100
2) Read data stored in the VCI management RAM 73 using the value recorded in the read pointer register 75 as an address (1003).

Next, the data read from the RAM 73 is assigned (written) to the input packet as the VCI on the output side, and the contents are notified to the necessary functional blocks such as the above-mentioned software that manages the VPI ( 1004).

As soon as the allocation is completed, the read pointer is incremented by 1 and rewritten, and at the same time, the pointer bit 71
Is set to "0" (1005).

On the other hand, the VCI release procedure shown in FIG. 8A, which is also started by the instruction of the software, is as follows.

First, the value recorded in the write pointer register 76 is read (1007), and then the VC to be released to the address of the VCI management RAM 73 designated by the value.
The value of I is written (1008).

Finally, the write pointer 76 is incremented by 1 and rewritten, and at the same time, the pointer bit 71 is set to "1" (1009).

The VCI management RAM 73 does not necessarily have to be set with continuous values, and a desired value can be set freely.

(B-2) Effect of Second Embodiment As described above, according to this embodiment, the same effect as that of the first embodiment can be obtained.

In addition, according to this embodiment, the register 7
VC that can be used by changing the setting value of 5,76
The number and value range of I can be flexibly set, and the unused number can be easily managed.

Further, in this embodiment, as in the first embodiment, the values of the registers 23 and 24 used for addressing are replaced by the stored data value of each address of the VCI management RAM to be addressed. Since it is not a chain method, the relationship required for the address of the VCI management RAM and its stored data is not strict, and the VCI value stored in the VCI management RAM can be freely selected by default.

Further, in the present embodiment, since it is sufficient to secure the entries for the maximum number of VCIs to be used, the VCIs
It is possible to save the memory capacity of the management RAM.

(C) Third Embodiment Single and fixed VCI in the first and second embodiments
The feature is that the number of digits (the number of bits) of the value can be changed as needed.

The other points, for example, the VCI having a function corresponding to the MID and the use of 1 VPI per subscriber (1 ATM terminal) may be the same as those in the first embodiment.

(C-1) Configuration and Operation of Third Embodiment The address conversion unit 40 of this embodiment is shown in FIG. The transmission device equipped with the address conversion unit 40 is the CLS1 of FIG.
4 and the like may be exactly the same as the address conversion unit 10 of the first embodiment.

In FIG. 9, the address conversion unit 40 uses V
Other than the CI management unit 102, for lowVCI and highVC
It has two components for I.

That is, for lowVCI, lowVC
I management RAM 103, lowVCI unused number register 104, lowVCI read pointer register 105
, LowVCI write pointer register 106, l
owVCI pointer bit 107, high
For VCI, the highVCI pointer bit 101 and
It comprises a highVCI management RAM 108, a highVCI unused number register 109, a highVCI read pointer register 110, and a highVCI write pointer register 111.

Of these, VCI management RAMs 103, 10
Reference numeral 8 corresponds to the VCI management RAM 73 of the second embodiment, unused number registers 104 and 109 correspond to the unused number register 74, and read pointer registers 105 and 1.
10 corresponds to the read pointer register 75, write pointer registers 106 and 111 correspond to the write pointer register 76, pointer bits 107,
Since 101 corresponds to the pointer bit 71, detailed description thereof will be omitted.

It is assumed that the VCI management RAMs 103 and 108 in which usable VCI values are stored are set in different areas on the same RAM.

The VCI management unit 102 is a control device similar to the VCI management unit 21.

In the present embodiment, the VCI resource management is performed by the lowVCI management RAM 103, the lowVCI read pointer register 105, the lowVCI write pointer register 106, the highVCI management RAM 108,
highVCI read pointer register 110, high
This is performed by the hVCI write pointer register 111.

The low VCI is a VCI expressed by a bit number less than 16 bits, that is, a VCI having a valid bit number of less than 16, and all higher bits are defined as "0".

The high VCI is a VCI expressed by using all 16 bits except the low VCI, that is, a VCI having 16 effective bits. That is, hig
In hVCI, one is always set to "1" in the bits higher than lowVCI.

For example, when returning the released VCI to the management RAMs 103 and 108, the VCI management unit 102 pays attention to the upper 2 bits of the VCI, and the relevant 2 bits are “01”, “10”, and “11”. If either, hi
It may be returned to the ghVCI management RAM 108, and if the corresponding 2 bits are “00”, it may be returned to the lowVCI management RAM 103.

However, in this embodiment, the highest four
Paying attention to a bit, if the bit is “0001” to “111”
High VCI management RAM in case of 1 "(1 to FH)
Return to 108, and in the case of “0000” (0H), lo
It is returned to the wVCI management RAM 103.

Therefore, in this embodiment, as shown in FIG.
As shown in (A) and (B), the same VCI is not stored in the RAMs 103 and 108.

FIG. 10A shows the initial setting state of the VCI management RAM 103, and FIG. 10B shows the VCI management RAM 108.
Shows the initial setting state of.

Further, FIG. 11A shows each register initial setting state of the read pointer 105 and write pointer 106, and FIG. 11B shows each register initial setting state of the read pointer 110 and write pointer 111. Indicates.

As a default setting, highVCI management RA
The value of the VCI to be used is written in the M108 / lowVCI management RAM 103.

Also, the highVCI read pointer register 110 and the highVCI write pointer register 1
11.low VCI read pointer register 105.l
For each owVCI write pointer register 106,
By setting the value of the read pointer and the value of the write pointer, it is possible to set the range of usable VCI values and the number of simultaneously usable VCIs.

FIG. 12 shows VCI allocation processing, and FIG. 13 shows V
The operation | movement flowchart of CI release processing is shown.

In the VCI allocation process of FIG. 12, first, it is discriminated whether or not the transmission device on the receiving side requires the VCI bit constraint (401). In this step, if it is determined that the bit constraint is necessary, lowVCI allocation processing is performed, and if it is determined not to be necessary, highVCI allocation processing is performed.

When the highVCI allocation process is started, it is first checked whether or not there is a free highVCI (408), and if not, an error process (403) is performed.

The content of the error processing is the same as that of the first embodiment described above.

Whether or not there is an empty highVCI is highV.
This is done by checking the CI unused number register 109. If there is a free high VCI, the VCI management unit 10
2 is the highVCI read pointer register 110
Is read (409), and the value recorded in the read pointer register 110 is used as an address in the highVCI management RAM.
The VCI management unit 102 reads the stored data of 108 (410).

For the corresponding packet whose transmission has started, R
Where the value read from AM108 is assigned as the VCI on the output side and information is needed (the software, etc.)
(411).

As soon as the allocation is completed, the read pointer 110 is incremented by one and rewritten.
The I pointer bit 101 is set to "0" (412).

On the other hand, in the lowVCI allocation processing, first, it is confirmed whether or not there is an empty lowVCI (402), and if there is no empty lowVCI, error processing (403) is performed.

Whether or not there is an empty lowVCI is determined by lowVCI.
This is done by checking the unused number register 104. If there is an empty lowVCI, the VCI management unit 102 first reads the lowVCI read pointer register 105 (404), and reads the lowVCI management RAM 103 using the value recorded in the read pointer register 105 as an address (405).

For the corresponding packet whose transmission has started, R
The value read from the AM 103 is assigned as the VCI on the output side, and the information is notified to the required place (406).

As soon as the allocation is completed, the read pointer is incremented by one and rewritten, and at the same time, the lowVCI pointer bit 107 is set to "0" (407).

In the VCI release processing of FIG. 13 described above, the VCI value to be released is first identified (501) and hi is
If it is recognized as ghVCI, the highVCI release processing is executed.
If it is recognized as lowVCI, lowVCI release processing is performed.

When the highVCI release processing is started, first, h
The value recorded in the highVCI write pointer register 111 is read (502), and then the value of the VCI to be released is written to the highVCI management RAM 108 using that value as an address (503).

Finally, highVCI write pointer 1
11 is incremented by 1 for rewriting, and at the same time, the highVCI pointer bit 101 is set to "1" (504).

When the lowVCI release processing is started, first, the value recorded in the lowVCI write pointer register 106 is read (505), and then the value of the VCI to be released is written in the lowVCI management RAM 103 using the value as an address (506). .

Finally, the lowVCI write pointer 10
6 is incremented by 1 and rewritten, and at the same time, the lowVCI pointer bit 107 is set to "1" (507).

(C-2) Effects of the Third Embodiment According to this embodiment, the same effects as those of the second embodiment can be obtained.

In addition, according to the present embodiment, it becomes possible to connect to a transmission device in which the number of VCI bits is limited (reception side).

(D) Fourth Embodiment In the flow chart of the third embodiment, the branch is made depending on the presence / absence of the constraint on the number of bits of VCI, so that the number of connections set at the same time increases and
I is all in use, but lowVCI is unused when there are unused ones.
It may be better to be able to use it instead of CI.

This embodiment makes this possible from the viewpoint of improving the efficiency of use of limited VCI resources.

Other points, for example, the VCI having a function corresponding to MID and the use of 1 VPI per subscriber (1 ATM terminal) may be the same as those in the first to third embodiments.

(D-1) Configuration and Operation of Fourth Embodiment Since the hardware of the address conversion unit of this embodiment is exactly the same as that of the address conversion unit 40 of FIG. 9 which is the third embodiment, The description is omitted.

Further, the address conversion unit 4 of the present embodiment.
The transmission device in which 0 is mounted may be exactly the same as the address conversion unit 10 of the first embodiment, such as the CLS 14 in FIG.

Most of the operation of this embodiment is similar to that of the third embodiment.

Among the operations of this embodiment, the only difference from the operation of the third embodiment is the VCI allocation processing.

FIG. 14 shows the VCI allocation processing of this embodiment.
It is shown in the flowchart.

In FIG. 14, first, it is discriminated whether or not the transmission device on the receiving side requires the VCI bit constraint (601), and if necessary, lowVCI allocation processing is performed, and if not required, highVCI allocation processing is performed.

When the highVCI allocation processing is started, it is first checked whether or not there is a free highVCI (608), and if there is no empty VCI, lowVCI allocation processing is performed.

As already described in the third embodiment, h
The difference between IGVCI and LOWVCI is only the most significant 4 bits, and there is no overlap in both VCIs.

Therefore, lo with a bit constraint on VCI
When a packet having highVCI is sent to a transmission device that should receive wVCI, for example, VCI “0000”
Since "H" and "1000H" cannot be discriminated from each other, and "0001H" and "1001H" cannot be discriminated from each other, a trouble may occur in the transmission device or in the network.

However, the transmission device that should receive highVCI, which has no bit constraint on VCI, has lowV
Even if a packet having a CI is sent, since the most significant bit “0”, which is invalid in the third embodiment, is only processed as a valid bit, no inconvenience occurs in the transmission device. .

Alternatively, in order not to cause any inconvenience,
It suffices for the software of the transmission device to recognize that the VCI whose upper 4 bits are "0000" may be handled.

Focusing on this point, the processing of the step 608 of the present embodiment (branch without an empty high VCI) is performed. Therefore, in this embodiment, unlike the third embodiment, error processing is not performed when there is no free high VCI.

Whether there is a free highVCI is highV.
This is done by checking the CI unused number register 109.

If there is a free high VCI, the VCI management unit 102 first reads the high VCI read pointer register 110 (609), and reads the read pointer register 11
The highVCI management RAM 108 is read using the value recorded in 0 as an address (610).

For the corresponding packet whose transmission has started, R
The value read from the AM 108 is assigned as the VCI on the output side, and the information is notified to the required place (611).

As soon as the allocation is completed, the read pointer 110 is incremented by one and rewritten, and at the same time highVC
The I pointer bit 101 is set to "0" (612).

Including the case of branching in step 608, lo
When the wVCI allocation process is started, it is first checked whether or not there is a free low VCI (602), and if there is no error, the error process (60
Perform 3).

Whether or not there is an empty lowVCI is determined by lowVCI.
This is done by checking the unused number register 104. If there is an empty lowVCI, the VCI management unit 102 first reads the lowVCI read pointer register 105 (604), and reads the lowVCI management RAM 103 using the value recorded in the read pointer register 105 as an address (605).

For the corresponding packet whose transmission has started, R
The value read from the AM 103 is assigned as the VCI on the output side, and the information is notified to the required place (606).

As soon as the allocation is completed, the read pointer 105 is incremented by one and rewritten, and at the same time lowVCI
The pointer bit 107 is set to "0" (607).

As described above, the VC of this embodiment is
The I release process is the same as the other operations, and the VC of the third embodiment is
Since it is exactly the same as the I release processing, its explanation is omitted.

(D-2) Effects of the Fourth Embodiment According to this embodiment, the same effects as those of the third embodiment can be obtained.

In addition, according to the present embodiment, by giving priority to the VCIs that can be used, it is possible to prevent the VCIs that can be used only on the limited side from being exhausted. Therefore, it is possible to use the limited VCI resources. The efficiency can be increased.

(E) Other Embodiments In the above embodiment, the routing bit of the ATM cell is divided by VPI and VCI, and the connection is set by using VCI. However, the way of dividing the routing bit is limited to this. Absent. For example, to identify the destination terminal (transmission route selection), use only a part of VPI
It is also possible to use the remaining bits of PI and VCI to select a connection.

Similarly, it is possible to properly use VCI within a certain range and other than that.

When there are a plurality of types of devices in which the number of VCI bits is limited, the VCI management area (for example, RAM area) may be divided for each limited range, and queues or chains may be provided by that number. .

Further, the present invention is not limited to VCI, but VP
It can also be used as a method for managing other communication identifiers such as I, MID, and entry number of temporary table. Possible factors for assigning these identifiers include when a new subscriber is registered, when a new call is established, when a new PDU is transmitted, and so on.

In the above description, the VPI is processed by software, but the VPI may be processed by hardware.

Furthermore, the functions of the hardware of the first to fourth embodiments may be borne by software having an equivalent function.

That is, according to the present invention, a transmission apparatus on the transmission side which supports a predetermined protocol layer, based on a conversion source address which is a state of an address field used for selecting a transmission route of an input protocol unit signal, The present invention can be widely applied to an address conversion method and device for determining a conversion destination address which is a state of an address field of an output protocol unit signal corresponding to a protocol unit signal.

[0161]

As described above, according to the present invention, message identification can be performed even in a protocol layer where message identification cannot be originally performed.

Further, since it is sufficient to secure the necessary resources, the hardware scale can be reduced.

Furthermore, resource management becomes flexible and easy.

[Brief description of drawings]

FIG. 1 is a flowchart according to a first embodiment.

FIG. 2 is a block diagram showing the configuration of the first embodiment.

FIG. 3 is a memory map according to the first embodiment.

FIG. 4 is a schematic diagram of a network according to first to fourth embodiments.

FIG. 5 is a block diagram showing a configuration of a second exemplary embodiment.

FIG. 6 is a memory map according to the second embodiment.

FIG. 7 is a schematic diagram showing addressing according to the second embodiment.

FIG. 8 is a flowchart according to a second embodiment.

FIG. 9 is a block diagram showing a configuration of a third embodiment.

FIG. 10 is a memory map according to the third embodiment.

FIG. 11 is a schematic diagram showing addressing according to the third embodiment.

FIG. 12 is a flowchart according to a third embodiment.

FIG. 13 is a flowchart according to a third embodiment.

FIG. 14 is a flowchart according to a fourth embodiment.

[Explanation of symbols]

10, 30, 40 ... Address conversion units 21, 72, 10
2 ... VCI management unit, 22, 73, 103, 108 ... VC
I management RAM, 23 ... Free VCI start register, 24 ...
Free VCI final register.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Morio Yoshida 1-7-12 Toranomon, Minato-ku, Tokyo Oki Denki Kogyo Co., Ltd. (72) Inventor Naoya Hashimoto 1-7-12 Toranomon, Minato-ku, Tokyo Oki Denki Kogyo Co., Ltd. (72) Inventor Maki Tanikawa 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Japan Telegraph and Telephone Corporation (72) Inventor Toshinori Ikegami 3-chome Nishishinjuku, Shinjuku-ku, Tokyo No. 2 Nihon Telegraph and Telephone Corporation (72) Inventor Takashi Kondo 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Nihon Telegraph and Telephone Corporation (56) Reference JP-A-7-30554 (JP, A) ) JP 9-205435 (JP, A) JP 11-68788 (JP, A) JP 2000-92074 (JP, A) JP 9-17188 (JP, A) JP 11-275082 (JP, A) JP 2000-252990 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 12/56 G06F 13/14 320 H04L 12/28 200

Claims (10)

(57) [Claims] 1. A transmission device on the transmission side which supports a predetermined protocol layer selects an input protocol unit signal based on a source address which is a state of an address field used for selecting a transmission path of the input protocol unit signal. In an address conversion method for determining a conversion destination address which is a state of an address field of a corresponding output protocol unit signal, a part of the address field set on the protocol unit signal for selecting the transmission route is transmitted. Converted as route selection data, and part of the other is converted as message identification data used for identifying a message to be transmitted between the transmission side transmission device and the reception side transmission device connected thereto, and the transmission route concerned. It is possible to configure the conversion destination address with the selection data and this message identification data. Address conversion method for the butterflies. 2. The address conversion method according to claim 1, wherein the transmission-side transmission device is provided with a storage memory for accumulating the message identification data, and a conversion destination address of the protocol unit signal at the next message transmission start. The top register that stores the corresponding storage memory address that stores the message identification data is the message identification data that is stored in the corresponding storage memory address that is addressed by its own stored value each time the message transmission starts. Is read, the stored value of itself is replaced with the message identification data, and the final register that stores the corresponding storage memory address that stores the message identification data released at the end of the next message transmission is The stored value is the message identification data that is released at the end of message transmission. An address translation method characterized by replacing with an address. 3. The address translation method according to claim 1, wherein the transmitting side transmission device is provided with a storage memory that stores the message identification data, and the storage memory is used to read out the message identification data to be used. The stored value of the read address pointer for addressing is changed at each message transmission start, and the stored value of the write address pointer for addressing the accumulated memory is the message for writing the released message identification data in the accumulated memory. An address conversion method characterized in that it is changed after each transmission. 4. The address translation method according to claim 3, wherein when the read address pointer and the write address pointer have the same pointer value, the message identification data in the storage memory are all in use or none of them is in use. An address conversion method characterized by determining whether it is not in use. 5. The address conversion method according to claim 3, wherein the number of unused message identification data is displayed by comparing pointer values of the read address pointer and the write address pointer. How to convert. 6. The address conversion method according to claim 1, wherein the number of bits of an address field processed by the transmission side transmission device and the number of bits of an address field processed by the reception side transmission device are different from each other. In order to deal with the case, the address conversion method is characterized in that the transmission-side transmission device prepares message identification data having different effective bits. 7. The address translation method according to claim 6, wherein the message identification data having different effective bit numbers are set so as not to overlap with each other, and the reception corresponding to the message identification data having a large effective bit number. For the side transmission device, when the message identification data having a large number of effective bits is already in use, the message identification data having a small number of effective bits is used instead instead. 8. A transmission device on the transmission side which supports a predetermined protocol layer selects an input protocol unit signal based on a source address which is a state of an address field used for selecting a transmission path of the input protocol unit signal. In an address translation device that determines a translation destination address that is a state of an address field of a corresponding output protocol unit signal, only a part of the address field set on the protocol unit signal for the transmission path selection is transmitted. Converted as route selection data, and part of the other is converted as message identification data used for identifying a message transmitted between the transmission side transmission device and the reception side transmission device connected to the transmission side transmission device, and the transmission route concerned. The selection data and this message identification data form the address that constitutes the conversion destination address. Address converting apparatus comprising: a processing unit. 9. The address translation device according to claim 8, wherein a storage memory that stores the message identification data, and a corresponding storage that stores message identification data that is a conversion destination address of the protocol unit signal at the next message transmission start. When the memory address is stored and the message identification data stored in the corresponding storage memory address addressed by the stored value is read out every time the message transmission is started, the corresponding message identification data is used. It stores the top register that replaces the stored value and the corresponding storage memory address that stores the message identification data that will be released at the end of the next message transmission, and the stored value will be released each time the message transmission ends. And a final register for replacing with data. Address translation device. 10. The address translation device according to claim 8, wherein a storage memory that stores the message identification data, and a storage value that addresses the storage memory at each message transmission start in order to read the message identification data to be used. And a write address pointer for changing the stored value for addressing the storage memory at each completion of message transmission in order to write the released message identification data to the storage memory. Address translation device.