JP3534647B2 - Method for manufacturing semiconductor light emitting device - Google Patents
Method for manufacturing semiconductor light emitting deviceInfo
- Publication number
- JP3534647B2 JP3534647B2 JP12262399A JP12262399A JP3534647B2 JP 3534647 B2 JP3534647 B2 JP 3534647B2 JP 12262399 A JP12262399 A JP 12262399A JP 12262399 A JP12262399 A JP 12262399A JP 3534647 B2 JP3534647 B2 JP 3534647B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor light
- light emitting
- cut
- chip
- emitting device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
Landscapes
- Led Devices (AREA)
- Dicing (AREA)
- Led Device Packages (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体ウエハから
機械的な切断によって分離し、切断面の1つから発光出
力を取出す半導体発光素子の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor light emitting device which separates a semiconductor wafer by mechanical cutting and takes out light emission output from one of the cut surfaces.
【0002】[0002]
【従来の技術】従来から、発光ダイオード(以下「LE
D」と略称する)などの半導体発光素子は、半導体ウエ
ハに多数個を同時に形成し、ウエハの両面に電極を形成
した後、ダイシングあるいはスクライブなどの機械的な
切断処理で個々の半導体発光素子へのチップ分割を行っ
て製造している。分割された半導体発光素子は、電気配
線基板などへの実装方式から、ウエハの一面のみを電気
配線基板に接触させる縦置型とウエハの両面を電気配線
基板に接触させる横置型とに大別される。2. Description of the Related Art Conventionally, a light emitting diode (hereinafter referred to as "LE
Semiconductor light emitting devices such as D) are formed on a semiconductor wafer at the same time, electrodes are formed on both sides of the wafer, and then individual semiconductor light emitting devices are formed by mechanical cutting processing such as dicing or scribing. It is manufactured by dividing the chip. The divided semiconductor light emitting elements are roughly classified into a vertical mounting type in which only one surface of the wafer is in contact with the electrical wiring board and a horizontal mounting type in which both surfaces of the wafer are in contact with the electrical wiring board, depending on the mounting method on the electrical wiring board or the like. .
【0003】図7は、特公昭56−44591の第1図
として示されている縦置型の実装状態を示す。電気絶縁
性の基台1の主面に外部リード2に接続される導電体3
を所定のパターンで形成しておく。半導体発光素子4
は、その表面に形成される電極5が導電体3とろう層6
とによって電気的に接合される。導電体3にろう層6で
接合される電極5と対向する側にも電極5が設けられ、
細線7をワイヤボンドによって導電体3に電気的に接続
する。FIG. 7 shows a mounting state of the vertical type shown as FIG. 1 of Japanese Patent Publication No. 56-44591. Conductor 3 connected to external lead 2 on the main surface of electrically insulating base 1
Are formed in a predetermined pattern. Semiconductor light emitting element 4
The electrode 5 formed on the surface of the conductor 3 and the brazing layer 6
It is electrically joined by. The electrode 5 is also provided on the side facing the electrode 5 joined to the conductor 3 with the brazing layer 6,
The thin wire 7 is electrically connected to the conductor 3 by wire bonding.
【0004】図7に示すような縦置型の半導体発光素子
4は、細線7によるワイヤボンドの信頼性を高めるため
に、細線7は電極5と導電体3との間を直線状に接続す
るのではなく、ループを形成するように接続する必要が
ある。このため、ループを形成するための高さが必要と
なり、薄形化の障害となる。In the vertical type semiconductor light emitting device 4 as shown in FIG. 7, in order to improve the reliability of wire bonding by the thin wire 7, the thin wire 7 connects the electrode 5 and the conductor 3 linearly. Rather, they need to be connected to form a loop. Therefore, a height for forming a loop is required, which is an obstacle to thinning.
【0005】図8は横置型の実装形態の概要を示す。表
面実装基板11上には、導電パターン12が形成され、
導電ペースト13で半導体発光素子14を固定しながら
電気的接続を行う。半導体発光素子14は、ウエハの状
態での表面および裏面に電極15,16が形成され、電
極15,16が導電パターン12と導電ペースト13に
よって接合される。ウエハ状態では表面に対して平行に
形成されるPN接合面17は、表面実装基板11の表面
に対して垂直な状態で実装される。半導体発光素子14
は、表面実装方式で実装されるので、ワイヤボンドの必
要はなく、全体を薄形化することができる。FIG. 8 shows an outline of a horizontal mounting type. A conductive pattern 12 is formed on the surface mount substrate 11,
Electrical connection is made while fixing the semiconductor light emitting element 14 with the conductive paste 13. In the semiconductor light emitting device 14, electrodes 15 and 16 are formed on the front and back surfaces in a wafer state, and the electrodes 15 and 16 are joined to the conductive pattern 12 and the conductive paste 13. The PN junction surface 17 formed in parallel with the surface in the wafer state is mounted in a state perpendicular to the surface of the surface mount board 11. Semiconductor light emitting device 14
Is mounted by the surface mounting method, so that wire bonding is not necessary and the entire structure can be thinned.
【0006】前述の特公昭56−44591は、図7に
示すような縦置型の半導体発光素子4では、表面に細線
7があるので、発光の外部効率が低下する対策として、
図8と同様な横置型とする提案を行っている。さらに特
開昭54−22186や特開平6−177435にも、
縦置型を横置型にしてワイヤボンドを廃止し、生産性を
向上する先行技術が開示されている。本件出願人は、特
開平10−242533で、横置型のLEDチップの少
なくとも底面に電気絶縁膜を形成し、半導体素子の結晶
面が他の部分に接触することを防ぐ先行技術を開示して
いる。According to Japanese Patent Publication No. 56-44591 mentioned above, in the vertical type semiconductor light emitting device 4 as shown in FIG. 7, since the fine line 7 is provided on the surface, as a measure for reducing the external efficiency of light emission,
A horizontal type similar to that of FIG. 8 is proposed. Furthermore, in Japanese Patent Laid-Open No. 54-22186 and Japanese Patent Laid-Open No. 6-177435,
There is disclosed a prior art in which a vertical type is changed to a horizontal type to eliminate wire bonds and improve productivity. The applicant of the present application discloses, in Japanese Unexamined Patent Publication No. 10-242533, a prior art in which an electrically insulating film is formed on at least the bottom surface of a horizontal LED chip to prevent the crystal plane of the semiconductor element from contacting other portions. .
【0007】[0007]
【発明が解決しようとする課題】図7に示すような縦置
型に比較して、図8に示すような横置型では、表面実装
法を採用して、ワイヤボンドを不要とし、薄形化を図る
ことができる。図8に示すような実装状態で、半導体発
光素子14は、PN接合面17で発光を行う。PN接合
面17で発光された発光光18は、チップ天面19から
外部に照射される。半導体発光素子14を実装した際の
素子高さを低く抑えるために、ウエハ分割のダイシング
において、少なくともチップ天面19とチップ底面20
との間の高さを定めるダイシングピッチは極力小さく設
定する必要がある。また半導体発光素子14の一辺を短
くすると、ダイシング時に半導体発光素子14のチップ
がダイシングブレードから受ける力によって、ウエハを
固定している粘着シートから剥がれるのを防ぐために、
他の一辺は半導体発光素子14のチップが粘着シートと
接着する充分な面積を確保することができるように、あ
る程度の長さを有する必要がある。すなわち、半導体発
光素子14の厚さを薄くしようとすれば、チップ天面1
9およびチップ底面20の紙面に垂直な一辺の長さとし
て、半導体発光素子14のチップが粘着シートと接着す
る充分な面積を確保することができるようにする必要が
ある。Compared to the vertical type as shown in FIG. 7, the horizontal type as shown in FIG. 8 adopts the surface mounting method, which eliminates the need for wire bonding and reduces the thickness. Can be planned. In the mounted state as shown in FIG. 8, the semiconductor light emitting element 14 emits light at the PN junction surface 17. The emitted light 18 emitted from the PN junction surface 17 is emitted from the chip top surface 19 to the outside. In order to keep the device height when the semiconductor light emitting device 14 is mounted low, at least the chip top surface 19 and the chip bottom surface 20 are used in dicing for wafer division.
It is necessary to set the dicing pitch, which determines the height between the and, as small as possible. Further, if one side of the semiconductor light emitting element 14 is shortened, in order to prevent the chip of the semiconductor light emitting element 14 from being peeled from the adhesive sheet fixing the wafer by the force received from the dicing blade during dicing,
The other side needs to have a certain length so that a sufficient area for the chip of the semiconductor light emitting element 14 to adhere to the adhesive sheet can be secured. That is, in order to reduce the thickness of the semiconductor light emitting device 14, the chip top surface 1
9 and one side of the chip bottom surface 20 which is perpendicular to the paper surface, it is necessary to secure a sufficient area for the chip of the semiconductor light emitting element 14 to adhere to the adhesive sheet.
【0008】このように長さについて調整を行った後で
も、ダイシング工程で切断されるチップが、最後にダイ
シングブレードに接触する面は、半導体発光素子14の
チップの固定が他の面を切断する場合と比較して不充分
となるので、振動等によってこの面は他の端面よりも粗
くなってしまう。このため、ダイシング時に半導体発光
素子4のチップがダイシングブレードから受ける力によ
って粘着シートから剥がれるのを防ぐのに必要な最小限
の接着面積しかもたない小さな半導体発光素子14のチ
ップをダイシング装置によって切断する場合、最後に切
断された面のみ他の端面とは異なった切断面の状態とな
ってしまう。Even after the length is adjusted in this way, the surface of the chip to be cut in the dicing step, which comes into contact with the dicing blade lastly, is fixed to the chip of the semiconductor light-emitting element 14 to cut the other surface. Since this is insufficient as compared with the case, this surface becomes rougher than other end surfaces due to vibration and the like. For this reason, the chip of the semiconductor light emitting element 14 having a minimum bonding area required to prevent the chip of the semiconductor light emitting element 4 from being peeled off from the adhesive sheet by the force received from the dicing blade during dicing is cut by the dicing device. In this case, only the last cut surface has a cut surface different from the other end surfaces.
【0009】ダイシング時の切断面は、結晶のダメージ
が大きく、そのままでは電気的なリークや光学的な吸収
が大きくなり、通常はエッチングなどによってダメージ
等の除去を行って平坦にする。ただし、ダメージ等の除
去を充分に行った状態でも、4つの切断面の凹凸の状態
は同じようにはならない。仮に充分長い時間エッチング
を行おうとすると、すでに形成されている電極や、エッ
チング中に電極を保護する膜にダメージを与えてしまう
か、あるいは結晶方位特有のエッチングレートの異方性
が顕在化し、4つの面を同じ状態にすることができなく
なる。The cut surface at the time of dicing has a large crystal damage, and electrical leakage and optical absorption increase as it is, and the damage is usually removed by etching or the like to flatten the surface. However, even if the damage and the like are sufficiently removed, the unevenness of the four cut surfaces does not become the same. If etching is attempted for a sufficiently long time, the electrodes that have already been formed or the film that protects the electrodes during etching will be damaged, or the anisotropy of the etching rate peculiar to the crystal orientation will become apparent. It becomes impossible to make two faces the same state.
【0010】本発明の目的は、ダイシング時に最後に切
断する面の粗度が大きくなることを利用して、発光効率
を高めることができる半導体発光素子の製造方法を提供
することである。An object of the present invention is to provide a method for manufacturing a semiconductor light emitting device, which can improve the light emission efficiency by utilizing the fact that the roughness of the surface to be cut last during dicing increases.
【0011】[0011]
【0012】[0012]
【0013】[0013]
【0014】[0014]
【0015】[0015]
【0016】[0016]
【0017】[0017]
【課題を解決するための手段】本発明は、ウエハ状の半
導体材料に複数個同時に形成される半導体発光素子を切
断して分離する半導体発光素子の製造方法において、各
半導体発光素子の切断を、発光出力が取出される面に切
断が最後となるように行うことを特徴とする半導体発光
素子の製造方法である。SUMMARY OF THE INVENTION The present invention is a method for manufacturing a semiconductor light emitting device in which a plurality of semiconductor light emitting devices simultaneously formed on a wafer-shaped semiconductor material are cut and separated. It is a method for manufacturing a semiconductor light emitting device, characterized in that the cutting is performed last on the surface from which the light emission output is taken out.
【0018】本発明によれば、ウエハ状の半導体材料か
ら半導体発光素子を切断して分離する際に、発光出力が
取出される面の切断が最後となるように各半導体発光素
子の切断を行うので、発光出力が取出される面の切断を
行う際に、吸着シートなどによる保持力が弱くなり、切
断面の粗さが他の切断面に比較して大きくなる。粗さが
大きい切断面から発光出力を取出すので、半導体発光素
子内部での減衰が少ない状態で発光出力を外部に取出す
ことができ、発光効率を高めることができる。According to the present invention, when the semiconductor light emitting element is cut and separated from the wafer-shaped semiconductor material, each semiconductor light emitting element is cut so that the surface from which the light emission output is taken is the last cut. Therefore, when the surface from which the light emission output is taken out is cut, the holding force of the suction sheet or the like becomes weak, and the roughness of the cut surface becomes large as compared with other cut surfaces. Since the light emission output is taken out from the cut surface having a large roughness, the light emission output can be taken out to the outside with a small attenuation inside the semiconductor light emitting element, and the light emission efficiency can be improved.
【0019】また本発明で、前記半導体発光素子は直方
体の形状を有し、前記ウエハ状の半導体材料に対して、
前記発光出力が取出される面に垂直な方向の切断を先に
行い、該発光出力が取出される面に平行な方向の切断
は、各半導体発光素子に対して、該発光出力が取出され
る面に対向する面が先に切断されるように行うことを特
徴とする。Further, in the present invention, the semiconductor light emitting element has a rectangular parallelepiped shape, and with respect to the wafer-shaped semiconductor material,
The cutting in the direction perpendicular to the surface from which the light emission output is taken out is performed first, and the cutting in the direction parallel to the surface from which the light emission output is taken out is taken out for each semiconductor light emitting element. It is characterized in that the surface opposite to the surface is cut first.
【0020】本発明に従えば、ウエハ状の半導体材料か
ら複数の半導体発光素子を切断して分離する際に、発光
出力が取出される面に平行な方向の切断は、発光出力が
取出される面に垂直な方向の切断の後で行い、各半導体
発光素子については、発光出力を取出す面の切断が最後
となるように切断するので、ウエハ状の半導体材料から
順に発光効率を高めた半導体発光素子を得ることができ
る。According to the present invention, when a plurality of semiconductor light emitting elements are cut and separated from a wafer-shaped semiconductor material, the light emission output is taken out by cutting in the direction parallel to the plane from which the light emission output is taken out. It is performed after cutting in the direction perpendicular to the surface, and for each semiconductor light emitting element, the cutting is performed so that the surface from which the light emission output is extracted becomes the last, so that semiconductor light emission in which the light emission efficiency is increased in order from the wafer-shaped semiconductor material. An element can be obtained.
【0021】[0021]
【発明の実施の形態】図1は、本発明の実施の一形態の
光半導体素子の実装状態を示す。本実施形態では、表面
実装基板21の導電パターン22に、導電ペースト23
で横置型の半導体発光素子24を実装する。半導体発光
素子24は、たとえばLEDであり、ウエハ状の半導体
材料に多数個が同時に形成され、ダイシング工程で機械
的に切断されて分離される。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a mounted state of an optical semiconductor element according to an embodiment of the present invention. In this embodiment, the conductive pattern 23 on the surface-mounting substrate 21 is applied to the conductive paste 23.
Then, the lateral semiconductor light emitting device 24 is mounted. The semiconductor light emitting element 24 is, for example, an LED, and a large number of semiconductor light emitting elements 24 are simultaneously formed on a wafer-shaped semiconductor material, and are mechanically cut and separated in a dicing process.
【0022】半導体発光素子24は、ウエハの状態で表
面および裏面となる側に、電極25,26をそれぞれ有
する。発光を行うPN接合面27は、ウエハの状態の表
面に平行であり、横置型の実装状態では、表面実装基板
21の表面に対して垂直となる。発光光28は、PN接
合面27から発生され、チップ天面29から外部に取出
される。チップ天面29は、チップ底面30や他の側面
に比較して、表面の粗度が大きい状態となっている。図
1では、チップ天面29の粗度が大きいことを誇張して
いる。半導体発光素子24は、たとえばガリウムリン
(GaP)やガリウムひ素リン(GaAsP)のような
屈折率が約3.5程度と大きな結晶を利用して形成する
ために、発光光28が半導体発光素子24のチップ外部
に出てくるには、結晶界面にほぼ直角に入射する必要が
ある。屈折率3.5の場合には、約17°以内の入射角
が必要である。チップ天面29がラフになっているの
で、チップ天面29で発光光28が何回か全反射を繰返
したとしも、全反射から全反射までのパスが短い状態で
外部に出てくることができる。このため、半導体発光素
子24内部での前進の程度が小さな状態で出射すること
ができる確率が高くなり、したがってチップ光度を向上
させることができる。The semiconductor light emitting device 24 has electrodes 25 and 26 on the front and back sides in the wafer state, respectively. The PN junction surface 27 that emits light is parallel to the surface of the wafer, and is perpendicular to the surface of the surface mounting substrate 21 in the horizontal mounting state. The emitted light 28 is generated from the PN junction surface 27 and taken out from the chip top surface 29. The top surface 29 of the chip has a higher surface roughness than the bottom surface 30 of the chip and other side surfaces. In FIG. 1, the high roughness of the chip top surface 29 is exaggerated. Since the semiconductor light emitting device 24 is formed by using a crystal having a large refractive index of about 3.5, such as gallium phosphide (GaP) or gallium arsenide phosphide (GaAsP), the emitted light 28 is emitted from the semiconductor light emitting device 24. In order to come out of the chip, it is necessary to enter the crystal interface at a substantially right angle. For a refractive index of 3.5, an angle of incidence within about 17 ° is required. Since the top surface 29 of the chip is rough, even if the emitted light 28 is repeatedly totally reflected on the top surface 29 of the chip, the path from the total reflection to the total reflection should come out in a short state. You can For this reason, the probability that light can be emitted in a state where the degree of advancement inside the semiconductor light emitting element 24 is small becomes high, and therefore the chip luminous intensity can be improved.
【0023】図7に示すように、光半導体素子14のチ
ップ天面19を平坦にしておくと、発光光18が半導体
発光素子14内部で全反射を繰返し、半導体発光素子1
4のチップ内で吸収を受けながら出射可能な角度で半導
体発光素子14のチップ表面に入射するようになるまで
減衰してしまう。本実施形態では、図2に拡大して示す
ように、チップ天面29の細かな凹凸を利用して、発光
光28を効率よく外部に取出すことができる。As shown in FIG. 7, when the chip top surface 19 of the optical semiconductor element 14 is flattened, the emitted light 18 repeats total reflection inside the semiconductor light emitting element 14, and the semiconductor light emitting element 1
While being absorbed in the chip of No. 4, it is attenuated until it enters the chip surface of the semiconductor light emitting device 14 at an angle at which it can be emitted. In the present embodiment, as shown in an enlarged view in FIG. 2, the fine unevenness of the chip top surface 29 can be used to efficiently take out the emitted light 28 to the outside.
【0024】図3は、半導体発光素子24を表面実装法
でアセンブリするときの設置状態を示す。半導体発光素
子24はチップ底面30で図1に示す表面実装基板21
に接触する。アセンブリ時のチップ天面29およびチッ
プ底面30と、側面31,32とが、ウエハ状の半導体
材料からの切断面である。電極25,26は、ウエハ面
の両側に形成される。ウエハ面はきわめて平坦に仕上げ
られている。FIG. 3 shows an installation state when the semiconductor light emitting element 24 is assembled by the surface mounting method. The semiconductor light emitting element 24 is a bottom surface 30 of the chip, and the surface mounting substrate 21 shown in FIG.
To contact. The chip top surface 29, the chip bottom surface 30, and the side surfaces 31 and 32 at the time of assembly are cut surfaces from the wafer-shaped semiconductor material. The electrodes 25 and 26 are formed on both sides of the wafer surface. The wafer surface is extremely flat.
【0025】図4は、半導体材料のウエハ40から、本
実施形態の半導体発光素子24を切出す際の分割状態を
示す。先に切断を行うダイシングライン41は、図3の
側面31,32に対応する切断を行う。後に切断を行う
ダイシングライン42は、図3のチップ底面30および
チップ天面29に対応する切断を行う。切断順序43
は、各半導体発光素子24について、チップ底面30側
が先に切断され、チップ天面29側が最後に切断される
ような順序にする。FIG. 4 shows a divided state when the semiconductor light emitting device 24 of the present embodiment is cut out from the semiconductor material wafer 40. The dicing line 41 which is cut first is cut corresponding to the side surfaces 31 and 32 of FIG. The dicing line 42 to be cut later cuts corresponding to the chip bottom surface 30 and the chip top surface 29 of FIG. Cutting order 43
For each semiconductor light emitting element 24, the chip bottom surface 30 side is cut first, and the chip top surface 29 side is cut last.
【0026】図5は、本実施形態による光半導体素子2
4の製造工程の概要を示す。ステップs1から製造工程
を開始し、ステップs2では、ウエハプロセスでウエハ
40上に複数の半導体発光素子24を同時に形成する。
ステップs3からダイシング工程を開始し、ステップs
3ではウエハ40の裏面に粘着シートを貼付ける。ステ
ップs4では、図4の先に切断を行うダイシングライン
41の切断を行う。次にステップs5で後に切断を行う
ダイシングライン42の切断を行う。この際の順序は、
図4の切断順序43に従う。ステップs6では、粘着シ
ートから各半導体発光素子24を分離し、たとえば向き
を揃えてキャリアテープなどに貼付ける。また、性能試
験なども行って、ステップs7で手順を終了する。FIG. 5 shows an optical semiconductor device 2 according to this embodiment.
An outline of the manufacturing process of No. 4 will be shown. The manufacturing process starts from step s1, and in step s2, a plurality of semiconductor light emitting elements 24 are simultaneously formed on the wafer 40 by a wafer process.
Start the dicing process from step s3, and then step s
At 3, an adhesive sheet is attached to the back surface of the wafer 40. In step s4, the dicing line 41 for cutting shown in FIG. 4 is cut. Next, in step s5, the dicing line 42 to be cut later is cut. The order at this time is
The cutting order 43 of FIG. 4 is followed. In step s6, the respective semiconductor light emitting elements 24 are separated from the adhesive sheet and, for example, aligned and attached to a carrier tape or the like. Further, a performance test and the like are also performed, and the procedure ends in step s7.
【0027】図6は、図4で後に切断を行うダイシング
ライン42を切断する状態を示す。ウエハ40は粘着シ
ート44に貼付けられ、ダイシングブレード45によっ
て切断される。後に切断を行うダイシングライン42に
関して、切断順序43の後方側の半導体発光素子24a
については、最後の切断となる。チップ底面30側はす
でに切断されているので、ダイシングブレード45から
受ける力を半導体発光素子24aのみで受けなければな
らない。このため、チップ天面29は粗度が大きくなっ
てしまう。一方、切断順序43で後から切断される半導
体発光素子24bについては、ダイシングブレード45
が切断している後に切断を行うダイシングライン42
は、チップ底面30の切断となる。この時点で、チップ
天面29は、さらに後から切断される半導体発光素子の
チップ底面30と分離していない状態となり、大きな面
積でダイシングブレード45からの力を受けることがで
き、半導体発光素子24bのチップ底面30は半導体発
光素子24aのチップ天面29よりも粗度を小さくする
ことができる。FIG. 6 shows a state in which the dicing line 42 to be cut later in FIG. 4 is cut. The wafer 40 is attached to the adhesive sheet 44 and cut by the dicing blade 45. Regarding the dicing line 42 to be cut later, the semiconductor light emitting element 24a on the rear side of the cutting sequence 43
Is the last disconnect. Since the chip bottom surface 30 side has already been cut, the force received from the dicing blade 45 must be received only by the semiconductor light emitting element 24a. Therefore, the chip top surface 29 has a large roughness. On the other hand, for the semiconductor light emitting element 24b to be cut later in the cutting order 43, the dicing blade 45
Dicing line 42 for cutting after cutting
Cuts the bottom surface 30 of the chip. At this point, the chip top surface 29 is not separated from the chip bottom surface 30 of the semiconductor light emitting element that will be further cut, and the force from the dicing blade 45 can be received in a large area. The roughness of the bottom surface 30 of the chip can be made smaller than that of the top surface 29 of the semiconductor light emitting element 24a.
【0028】図6では、ダイシングブレード45でダイ
シングラインの全部を切断するフルダイシングについて
説明しているけれども、ダイシングラインの全部を切断
せずに、図5のステップs6でスクライブを行い、残り
の部分を折曲げて切断するような場合であっても最後に
切断する面の粗度は他の切断面に比較して大きくなるの
で、本発明を同様に適用することができる。また、発光
光を取出す面がチップ天面29ではなく、側面31,3
2などとなる場合であっても、そのような側面31,3
2の切断を最後に行うようにすれば、本発明を同様に適
用することができる。また、薄形化を目的とせず、単に
表面実装を行うために横置型を採用する場合であって
も、本発明を同様に適用することができる。Although FIG. 6 describes full dicing in which all of the dicing lines are cut by the dicing blade 45, the entire dicing line is not cut, and scribing is performed in step s6 in FIG. Even in the case of bending and cutting, the roughness of the surface to be cut last is higher than that of the other cut surfaces, so that the present invention can be similarly applied. Further, the surface from which the emitted light is extracted is not the chip top surface 29 but the side surfaces 31 and 3.
Even if it becomes 2, etc., such side surfaces 31, 3
The present invention can be similarly applied if the cutting of 2 is performed last. Further, the present invention can be similarly applied even in the case of adopting a horizontal type for simply performing surface mounting without the purpose of thinning.
【0029】本発明によって、従来問題となっている切
断面の粗さによる見栄えや光学的特性のばらつきを解消
することができ、さらに取出し効率の向上によって光度
も向上させることができる。According to the present invention, the appearance and variations in optical characteristics due to the roughness of the cut surface, which have been a problem in the past, can be eliminated, and the luminous efficiency can be improved by improving the extraction efficiency.
【0030】[0030]
【0031】[0031]
【0032】[0032]
【0033】[0033]
【発明の効果】本発明によれば、ウエハ状の半導体材料
から個々の半導体発光素子を分離する際に、切断する順
序を、発光出力を取出す面が最後となるようにするだけ
で、発光効率の良好な半導体発光素子を製造することが
できる。According to the present invention, when the individual semiconductor light emitting elements are separated from the wafer-shaped semiconductor material, the cutting order is such that the surface from which the light emission output is taken out is the last. It is possible to manufacture a good semiconductor light emitting device.
【0034】また本発明によれば、ウエハ状の半導体材
料から、複数の半導体発光素子を、発光効率の良好な状
態で効率よく製造することができる。Further, according to the present invention, it is possible to efficiently manufacture a plurality of semiconductor light emitting devices from a wafer-shaped semiconductor material in a state where the luminous efficiency is good.
【図1】本発明の実施の一形態の実装状態を示す簡略化
した断面図である。FIG. 1 is a simplified cross-sectional view showing a mounted state of an embodiment of the present invention.
【図2】図1のチップ天面29の部分での発光光28の
反射状態を示す部分的な断面図である。FIG. 2 is a partial cross-sectional view showing a reflection state of emitted light 28 at a chip top surface 29 portion of FIG.
【図3】図1の実施形態の半導体発光素子24のアセン
ブリ状態を示す斜視図である。3 is a perspective view showing an assembled state of the semiconductor light emitting device 24 of the embodiment of FIG. 1. FIG.
【図4】図1の半導体発光素子24をウエハ40から分
離するためのダイシングライン41,42を示す簡略化
した平面図である。4 is a simplified plan view showing dicing lines 41 and 42 for separating the semiconductor light emitting device 24 of FIG. 1 from a wafer 40. FIG.
【図5】図1の実施形態の半導体発光素子24を製造す
る工程を示すフローチャートである。5 is a flowchart showing a process of manufacturing the semiconductor light emitting device 24 of the embodiment of FIG. 1. FIG.
【図6】図2の後に切断を行うダイシングライン42を
切断する状態を示す部分的な断面図である。FIG. 6 is a partial cross-sectional view showing a state in which a dicing line 42 for cutting after FIG. 2 is cut.
【図7】従来からの縦置型の半導体発光素子の実装状態
を示す簡略化した断面図である。FIG. 7 is a simplified cross-sectional view showing a mounted state of a conventional vertical semiconductor light emitting device.
【図8】従来からの横置型の半導体発光素子の実装状態
を示す簡略化した断面図である。FIG. 8 is a simplified cross-sectional view showing a mounting state of a conventional horizontal semiconductor light emitting device.
21 表面実装基板 22 導電パターン 23 導電ペースト 24,24a,24b 半導体発光素子 25,26 電極 27 PN接合面 28 発光光 29 チップ天面 30 チップ底面 40 ウエハ 41 先に切断を行うダイシングライン 42 後に切断を行うダイシングライン 43 切断順序 44 粘着シート 45 ダイシングブレード 21 Surface mount board 22 Conductive pattern 23 Conductive paste 24, 24a, 24b Semiconductor light emitting device 25,26 electrodes 27 PN junction surface 28 emitted light 29 chip top surface 30 chip bottom 40 wafers 41 Dicing line for cutting first 42 Dicing line for cutting after 43 cutting order 44 Adhesive sheet 45 dicing blade
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 33/00 ─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 33/00
Claims (2)
成される半導体発光素子を切断して分離する半導体発光
素子の製造方法において、 各半導体発光素子の切断を、発光出力が取出される面の
切断が最後となるように行うことを特徴とする半導体発
光素子の製造方法。1. A method of manufacturing a semiconductor light-emitting device, comprising cutting a plurality of semiconductor light-emitting devices simultaneously formed on a wafer-shaped semiconductor material to separate the semiconductor light-emitting devices from each other. A method for manufacturing a semiconductor light emitting device, characterized in that cutting is performed last.
し、 前記ウエハ状の半導体材料に対して、前記発光出力が取
出される面に垂直な方向の切断を先に行い、 該発光出力が取出される面に平行な方向の切断は、各半
導体発光素子に対して、該発光出力が取出される面に対
向する面が先に切断されるように行うことを特徴とする
請求項2記載の半導体発光素子の製造方法。2. The semiconductor light emitting element has a rectangular parallelepiped shape, and the wafer-shaped semiconductor material is first cut in a direction perpendicular to a surface from which the light emission output is taken out, and the light emission output is 3. The cutting in the direction parallel to the extraction surface is performed so that, for each semiconductor light emitting element, the surface opposite to the surface from which the emission output is extracted is cut first. Manufacturing method of semiconductor light emitting device of.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12262399A JP3534647B2 (en) | 1999-04-28 | 1999-04-28 | Method for manufacturing semiconductor light emitting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12262399A JP3534647B2 (en) | 1999-04-28 | 1999-04-28 | Method for manufacturing semiconductor light emitting device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000315816A JP2000315816A (en) | 2000-11-14 |
| JP3534647B2 true JP3534647B2 (en) | 2004-06-07 |
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| JP5378184B2 (en) * | 2009-12-07 | 2013-12-25 | シャープ株式会社 | Bar-shaped structure light emitting device, backlight, illumination device and display device |
| KR102546307B1 (en) * | 2015-12-02 | 2023-06-21 | 삼성전자주식회사 | Light emitting device and display device including the same |
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