JP3542973B2 - High-speed signal circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a signal synchronization technique for synchronizing a signal of a module system including a plurality of LSIs connected to the same bus, and more particularly, to synchronizing a high-speed clock signal with a low-speed clock synchronization signal to convert a high-speed clock signal of the LSI. It relates to a high-speed signal circuit to be generated.
[0002]
[Prior art]
Conventionally, a technique for synchronizing clock signals of a plurality of modules is disclosed in, for example, Japanese Utility Model Laid-Open No. 01-27722. In this technology, a plurality of modules are connected by a common bus, a clock signal of a predetermined frequency is input to each module, and the clock signal is synchronized by multiplying each module to a synchronization frequency. I'm trying. Japanese Patent Application Laid-Open No. 2000-207050 discloses that in a system including a plurality of LSIs, an enable signal of a specific frequency is generated, a reference signal is generated based on the enable signal, and a system is further configured based on the reference signal. The internal clock signal is generated. Thus, signals between clock pulses used in a plurality of LSIs can be synchronized.
[0003]
FIG. 5 is a block diagram of a conventional high-speed signal circuit. In FIG. 5, in order to operate the signals of a plurality of LSIs 22, 23, 24 connected to a common synchronization bus 21 at high speed and in a synchronized manner, the bus interfaces 25, 26, 27 of the respective LSIs 22, 23, 24 are connected. In addition, the clock signal generation circuit 28 supplies a low skew clock signal (EX_CLK1, 2, 3) such that the rising edge arrives at the same time. Further, in order to make the propagation delay time of each of the clock signals EX_CLK1, EX_CLK2, and EX_CLK3 distributed to each of the LSIs 22, 23, 24 the same, the length of the clock signal line from the clock signal generation circuit 28 to each of the LSIs 22, 23, 24 is changed. Adjusting the length. That is, actually, the clock signals (EX_CLK1,2,3) are supplied through the pattern on the substrate, so that the clock signals (EX_CLK1,2,3) are synchronized to synchronize the clock signals EX_CLK1, EX_CLK2, EX_CLK3. In consideration of the propagation delay time, the pattern length from the clock signal generation circuit 28 to each of the LSIs 22, 23, and 24 is adjusted to be equal.
[0004]
[Problems to be solved by the invention]
However, in order to supply a high quality clock signal from the clock signal generation circuit 28 such that the rising edges of the clock signal arrive at the same time, a plurality of LSIs 22 and 23 are supplied from one clock supply IC in the clock signal generation circuit 28. , 24 to one-to-one corresponding clock signals, which complicates the resulting circuit. Further, it is necessary to adjust the length of the clock signal line in order to make the propagation delay time of the clock signal distributed to each of the LSIs 22, 23, and 24 the same. Since the LSIs cannot be arranged close to each other due to a limitation, the pattern wiring length of a high-speed clock signal may be tens of centimeters. In addition, since the number of LSIs may exceed ten, the number of signals increases accordingly, and it becomes difficult to adjust the length of each clock signal line.
[0005]
Further, it is generally known that a high-speed clock signal is one of the causes of radiation noise. As a countermeasure against this, a board design has been taken with measures such as adding a filter in the middle of a clock signal line. However, such a noise suppression technique requires know-how of a special pattern design, and the noise has not been eliminated. In particular, the time interval of other bus signals is random, while the clock signal always operates at a constant frequency, so that a noise peak is easily generated, which is a factor for generating large radiation noise.
[0006]
In the technique disclosed in Japanese Utility Model Laid-Open Publication No. Hei 01-27722, the wiring length from a signal generator for generating a clock signal of a predetermined frequency to each module is generally non-uniform, and as a result, a clock signal distributed to each module is generated. Propagation delay time varies. Therefore, since the rising edge of the clock signal is shifted for each module, the phase of the multiplied synchronization frequency may be shifted for each module. Furthermore, it is quite difficult to take measures against radiation noise generated from each signal line as described above. Also, in the technique disclosed in Japanese Patent Application Laid-Open No. 2000-207050, at the stage of distributing the internal clock generated based on the reference signal to each LSI, the clock signal is varied due to the variation in the length of each signal wiring as described above. The problem that the rising edge is shifted is still not solved.
[0007]
The present invention has been made in view of such circumstances, and an object thereof is to maintain a high operating frequency of a synchronous bus by distributing a low-speed synchronous signal instead of a high-speed clock signal. Another object of the present invention is to provide a high-speed signal circuit that does not require measures against radiation noise radiated from a substrate.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, the high-speed signal circuit of the present invention, a plurality of modules, individually, in a high-speed signal circuit for transmitting a high-speed clock signal to the common bus, the internal clock generation provided to each of the plurality of modules When the circuit receives a low-speed synchronization pulse from the outside, it generates a high-speed clock signal individually in synchronization with the low-speed synchronization pulse signal, and starts transmitting each of the generated high-speed clock signals to the common bus. Features. Therefore, according to the high-speed signal circuit of the present invention, the synchronizing signal flowing through the signal line of the board becomes low while the operating frequency of the common bus to which each module is connected is kept high, so that radiation noise from the board is reduced. be able to.
[0009]
Further, the high-speed signal circuit according to the present invention, in the above-mentioned invention, comprises: a synchronizing signal generating means for generating a low-speed synchronizing signal; a low-speed synchronizing signal received from the synchronizing signal generating means; , And a plurality of modules for transmitting the generated high-speed clock signal to the common bus. As a result, a high-speed clock signal is generated inside the module and transmitted to the common bus while synchronizing with the low-speed signal flowing through the signal line, so that the occurrence of noise can be reduced, and as a result, noise countermeasures for the board, etc. Becomes unnecessary.
[0010]
Further, in the high-speed signal circuit of the present invention, in the above-mentioned invention, each of the plurality of modules includes high-speed clock generating means for generating a high-speed clock signal in synchronization with a low-speed synchronizing signal. The high-speed clock signal is generated by multiplying the oscillation frequency of the slave. That is, since the high-speed clock signal is generated by multiplying the oscillation frequency of the crystal oscillator as the reference signal and multiplying the reference signal, the frequency stability of the bus clock signal transmitted to the common bus is extremely high.
[0011]
Further, in the high-speed signal circuit according to the present invention, in the above-mentioned invention, the synchronization signal generation means transmits the low-speed synchronization signal collectively to the high-speed clock generation means provided in each of the plurality of modules. Alternatively, the synchronization signal generation means may distribute the low-speed synchronization signal to the high-speed clock generation means included in each of the plurality of modules in a one-to-one correspondence. That is, according to the high-speed signal circuit of the present invention, the low-speed synchronization signal can be transmitted to each module collectively, but the low-speed synchronization signal can also be distributed and transmitted to each module. In other words, if the low-speed synchronization signal is distributed and transmitted to each module, the skew of the rising waveform between the low-speed synchronization signals input to each module can be reduced, and as a result, the quality of the synchronization signal of the system bus can be reduced. Can be improved.
[0012]
Further, in the high-speed signal circuit of the present invention, in the above-mentioned invention, the frequency of the low-speed synchronizing signal generated by the synchronizing signal generating means is lower than the operating frequency of the common bus, and the low-speed synchronizing signal is periodically output from the high-speed clock generating means. Is transmitted to That is, if the low-speed synchronization signal is transmitted periodically, the phase shift of the clock of the high-speed clock signal generated by the high-speed clock generation means can be corrected, and as a result, the synchronization signal of the system bus can be corrected. Quality can be improved. Note that a preferred embodiment of the module used in each of the above means can be an LSI.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the high-speed signal circuit according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of a high-speed signal circuit according to the first embodiment of the present invention. First, the high-speed signal circuit according to the first embodiment of the present invention will be described with reference to FIG. The high-speed signal circuit shown in FIG. 1 is connected to a synchronous bus 1 and operates in synchronization with a plurality of LSIs 2, 3, and 4, and bus clock signals (CLK1, 2, and 3) generated by the respective LSIs 2, 3, and 4 themselves. ) And a clock synchronization signal generation circuit 14 that outputs a clock synchronization signal (SYNC_PULSE) for synchronizing them. The synchronous bus 1 is a bus that operates in synchronization with the bus clock signals (CLK1, CLK2, CLK3). In this embodiment, a system for connecting three LSIs 2, 3, and 4 will be described for ease of explanation. However, the operation is the same regardless of how many LSIs are connected. In other words, the LSI system using the high-speed signal circuit is not dependent on the number of LSIs except for the physical restrictions imposed by the number of input / output pins of the clock synchronization signal generation circuit 14.
[0014]
Each of the LSIs 2, 3, and 4 has bus interfaces 5, 6, and 7 for connecting to the synchronous bus 1, crystal oscillators 8, 9, and 10, and internal clock generation circuits 11, 12, and 13, respectively. ing. Note that the crystal units 8, 9, and 10 may be externally attached. Further, each of the crystal oscillators 8, 9, and 10 needs to have the same frequency in order to determine the frequency of the internal clock generation circuits 11, 12, and 13 that generate the bus clock signals (CLK1, 2, and 3). is there. Further, the internal clock generation circuits 11, 12, and 13 apply a voltage to the crystal oscillators 8, 9, and 10 to amplify the oscillations and generate bus clock signals (CLK1, 2, and 3). At this time, the internal clock generation circuits 11, 12, and 13 multiply the frequency to generate bus clock signals (CLK1, 2, and 3) higher than the frequency of the crystal oscillators 8, 9, and 10 for each of the LSIs 2, 3, and 4. The bus clock signals (CLK1, 2, 3) are generated internally and supplied to the respective bus interfaces 5, 6, 7.
[0015]
Each of the internal clock generation circuits 11, 12, and 13 is provided with one output pin and one input pin. From the output pin, oscillation preparation completion signals (CLK_EN1, 2, 3) indicating completion of oscillation preparation of the internal clock generation circuits 11, 12, 13 are output. The input pin receives a clock synchronization signal (SYNC_PULSE) from the external clock synchronization signal generation circuit 14. Further, the clock synchronization signal generation circuit 14 generates an oscillation preparation completion signal (CLK_EN1, 2, 3) for notifying that the internal clock generation circuits 11, 12, 13 included in the LSIs 2, 3, 4 have completed preparation for oscillation. Have a pin to receive. Further, the clock synchronization signal generation circuit 14 oscillates the bus clock signals (CLK1, 2, 3) of the respective LSIs 2, 3, and 4 at the same timing after confirming the completion of the transmission preparation of all the LSIs 2, 3, and 4. There is a pin for transmitting a synchronizing signal for transmitting the clock synchronizing signal (SYNC_PULSE) to the internal clock generating circuits 11, 12, and 13 built in the LSIs 2, 3, and 4.
[0016]
The internal clock generation circuits 11, 12, and 13 refer to the rising edge of the clock synchronization signal (SYNC_PULSE) received from the clock synchronization signal generation circuit 14 to determine the timing of the high-speed bus clock obtained from the crystal oscillators 8, 9, and 10. Has a function of synchronizing the bus clock signals (CLK1, 2, 3) generated for each of the LSIs 2, 3, and 4. By supplying the bus clock signals (CLK1, 2, 3) to the bus interfaces 5, 6, and 7 in the respective LSIs 2, 3, and 4, the synchronous bus 1 can perform high-speed operation synchronously. become.
[0017]
That is, in the system of the high-speed signal circuit according to the present invention, the plurality of LSIs 2, 3, and 4 having the bus interfaces 5, 6, and 7 for the bus clock signals (CLK1, 2, and 3) are connected to one synchronous bus 1. Internal clock generation circuits 11, 12, and 13 provided with an input pin for receiving a synchronization signal and an output pin for transmitting an oscillation ready signal indicating that the internal clock generation circuits 11, 12, and 13 are ready for oscillation, respectively. LSIs 2, 3, and 4. Furthermore, a clock synchronization signal generation circuit 14 is added to the outside, and a clock synchronization signal (CLK1, 2, 3) for oscillating the bus clock signals (CLK1, 2, 3) which are the internal clock signals of the respective LSIs 2, 3, 4 at the same timing. SYNC_PULSE) is transmitted to each of the LSIs 2, 3, and 4. The clock synchronization signal (SYNC_PULSE) may be a low-speed signal for synchronizing the bus clock signals (CLK1, 2, 3) instead of a high-speed signal for clocking the bus clock signals (CLK1, 2, 3). .
[0018]
Therefore, a low-speed clock synchronization signal (SYNC_PULSE) is transmitted to a signal line connecting the clock synchronization signal generation circuit 14 and each of the internal clock generation circuits 11, 12, and 13, so that a noise countermeasure which has been conventionally implemented is taken. The radiation noise radiated from the substrate can be reduced without performing the special substrate design. That is, the feature of the high-speed signal circuit according to the present invention is mainly that the bus clock signal (without reducing the operating frequency of the synchronous bus 1 to which the plurality of LSIs 2, 3, and 4 are connected and without taking measures against noise in the board design). CLK1, 2, 3).
[0019]
Next, the operation of the high-speed signal circuit shown in FIG. 1 after the power is turned on will be described using a time chart waveform. FIG. 2 is a time chart waveform showing the operation of the high-speed signal circuit shown in FIG. 1 from power-on. When operable power is supplied to each of the LSIs 2, 3, and 4, first, the internal clock generation circuits 11, 12, and 13 use the crystal oscillators 8, 9, and 10 inside the LSIs 2, 3, and 4, respectively. , An internal clock to be a bus clock signal (CLK1, 2, 3) is prepared. In this state, since the clock signals of the LSIs 2, 3, and 4 are not synchronized, no signals are supplied to the bus interfaces 5, 6, and 7 yet.
[0020]
After the preparation for oscillating the bus clock signals (CLK1, 2, 3), which are the internal clocks, is completed, the LSIs 2, 3, and 4 output the oscillation preparation completion signals (from the respective internal clock generation circuits 11, 12, 13). CLK_EN1, 2, 3) to transmit an oscillation preparation completion notification to the clock synchronization signal generation circuit 14. The clock synchronization signal generation circuit 14 has a multi-gate AND circuit configuration that can receive a notification of completion of oscillation preparation for each of the LSIs 2, 3, and 4.
[0021]
In the time chart waveform of FIG. 2, when the internal clock generation circuits 11, 12, and 13 complete the oscillation preparation, the respective oscillation preparation completion signals CLK_EN1, CLK_EN2, and CLK_EN3 change from the inactive state to the active state. At this time, as shown in the figure, the timing of the state change of each oscillation preparation completion signal CLK_EN1, CLK_EN2, CLK_EN3 is different. Therefore, at time TA after all the state changes, all the LSIs 2, 3, and 4 of this system complete the preparation for oscillation. That is, the clock synchronization signal generation circuit 14 can recognize at this time TA that all the oscillation preparation completion signals CLK_EN1, CLK_EN2, and CLK_EN3 have been activated. Therefore, the clock synchronization signal generation circuit 14 transmits the clock synchronization signal (SYNC_PULSE) to the internal clock generation circuits 11, 12, and 13 of the LSIs 2, 3, and 4 at time TA.
[0022]
Then, each of the internal clock generation circuits 11, 12, and 13 receiving the clock synchronization signal (SYNC_PULSE) adjusts the bus clock signals (CLK1, 2, 3) so as to synchronize with the clock synchronization signal (SYNC_PULSE). The supply to the interfaces 5, 6, and 7 is started. As a result, the bus clock signals (CLK1, 2, 3) which are the internal clocks of the LSIs 2, 3, 4 are synchronized, and by supplying those signals to the respective bus interfaces 5, 6, 7, The LSIs 2, 3, and 4 can transmit the synchronized bus clock signals CLK1, CLK2, and CLK3 to the synchronous bus 1.
[0023]
Next, a high-speed signal circuit according to a second embodiment of the present invention will be described. FIG. 3 is a block diagram of a high-speed signal circuit according to the second embodiment of the present invention. The configuration of the second embodiment shown in FIG. 3 is different from that of the first embodiment shown in FIG. 1 in that the clock synchronization signal generation circuit 14 has a one-to-one clock synchronization signal ( Dedicated pins are provided so that SYNC_PULSE1, 2, 3) can be distributed. As described above, by distributing the clock synchronization signal (SYNC_PULSE1, 2, 3) to each of the LSIs 2, 3, and 4, the clock synchronization signals SYNC_PULSE1, SYNC_PULSE2, and SYNC_PULSE3 input to the LSIs 2, 3, and 4 are separated. The skew of the rising waveform can be reduced, and as a result, the quality of the synchronization signal of the system bus can be improved.
[0024]
FIG. 4 is a time chart waveform further applying the high-speed signal circuit of the second embodiment shown in FIG. That is, like the clock synchronization signal (SYNC_PULSE1, 2, 3) of the time chart waveform of FIG. If the clock is transmitted periodically, the phase shift of the clocks of the bus clock signals (CLK1, 2, 3) generated by the internal clock generation circuits 11, 12, 13 is corrected for each predetermined timing. As a result, the quality of the synchronization signal of the system bus can be improved as a result.
[0025]
The embodiment described above is an example for describing the present invention, and the present invention is not limited to the above embodiment, and various modifications are possible within the scope of the invention. That is, in each of the embodiments described above, a case where a high-speed bus clock signal is transmitted from a plurality of LSIs to a common synchronous bus has been described. It goes without saying that the present invention is also applied to the embodiment in which the data is transmitted to the synchronous bus.
[0026]
【The invention's effect】
As described above, according to the high-speed signal circuit of the present invention, the clock synchronization signal transmitted through the wiring on the board is operated at a low speed, so that the radiation noise of the board can be reduced. This eliminates the need for radiation noise countermeasures, thereby eliminating the need for a conventionally required ferrite part for a filter and the like, and simplifies the circuit, thereby reducing costs. Further, special know-how such as noise countermeasures is not required in the board design, and as a result, the cost of the entire board can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram of a high-speed signal circuit according to a first embodiment of the present invention.
FIG. 2 is a time chart waveform showing an operation of the high-speed signal circuit shown in FIG. 1 from power-on.
FIG. 3 is a block diagram of a high-speed signal circuit according to a second embodiment of the present invention.
FIG. 4 is a time chart waveform further applying the high-speed signal circuit of the second embodiment shown in FIG.
FIG. 5 is a block diagram of a conventional high-speed signal circuit.
[Explanation of symbols]
1,21 Synchronous bus 2,3,4,22,23,24 LSI
5, 6, 7, 25, 26, 27 Bus interface 8, 9, 10 Crystal oscillator 11, 12, 13 Internal clock generation circuit 14 Clock synchronization signal generation circuit 28 Clock signal generation circuit CLK_EN1, 2, 3 Oscillation preparation completion signal CLK1,2,3 bus clock signal SYNC_PULSE clock synchronization signal EX_CLK1,2,3 clock signal

Claims (7)

In a high-speed signal circuit for individually transmitting a high-speed clock signal from a plurality of modules to a common bus, when an internal clock generation circuit provided in each of the plurality of modules receives a low-speed synchronization pulse signal from the outside, the low-speed synchronization A high-speed signal circuit , wherein a high- speed clock signal is individually generated in synchronization with a pulse signal, and transmission of each generated high-speed clock signal to the common bus is started . Synchronization signal generating means for generating a low-speed synchronization signal;
A plurality of modules for receiving a low-speed synchronization signal from the synchronization signal generation means, generating a high-speed clock signal in synchronization with the low-speed synchronization signal, and transmitting the high-speed clock signal to the common bus. 2. The high-speed signal circuit according to claim 1, wherein The plurality of modules each include a high-speed clock generation unit that generates a high-speed clock signal in synchronization with a low-speed synchronization signal,
3. The high-speed signal circuit according to claim 2, wherein the high-speed clock generation unit generates a high-speed clock signal by multiplying an oscillation frequency of the crystal unit. 4. The high-speed signal circuit according to claim 3, wherein the synchronization signal generation unit transmits the low-speed synchronization signal to the high-speed clock generation units included in each of the plurality of modules. 4. The high-speed signal circuit according to claim 3, wherein the synchronization signal generation means distributes the low-speed synchronization signal to the high-speed clock generation means provided in each of the plurality of modules in a one-to-one correspondence. The low-speed synchronizing signal generated by the synchronizing signal generating means has a lower frequency than the operating frequency of the common bus, and the low-speed synchronizing signal is periodically transmitted to the high-speed clock generating means. The high-speed signal circuit according to claim 2. 7. The high-speed signal circuit according to claim 1, wherein said module is an LSI.

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