JP3545444B2 - Read-only storage device - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a semiconductor read-only storage device (hereinafter, referred to as a ROM), and more particularly to a read circuit using a sense amplifier that reads cell data by comparing a read potential from a memory cell with a read potential from a dummy cell.
[0002]
[Prior art]
By using an N + type buried layer in a semiconductor substrate for the source / drain of the cell transistor in order to reduce the pattern size of the memory cell of the ROM, it becomes possible to eliminate the element isolation region in the cell array. A ground-type memory cell (for example, “read-only memory” of Japanese Patent Application No. 3-332701 filed by the present applicant) has been used.
[0003]
The programming of the data "0" and "1" for the memory cell of the virtual ground system is performed by controlling the threshold value VTH of the cell transistor depending on whether boron ions are implanted into the channel region of the memory cell.
[0004]
FIG. 5 is a circuit diagram showing a part of a CMOS type mask ROM using memory cells of a virtual ground system.
In FIG. 5, a cell transistor (body cell) 51 composed of an N-channel MOS transistor is arranged in a matrix to form a memory cell array 50, and this memory cell array is divided into a plurality of memory cell blocks.
[0005]
Reference numeral 52 denotes a word line commonly connected to the gates of the ROM cells 51 in the same row in the memory cell array, and only one word line is typically shown. The word line 52 is selected by a row decoder (not shown), and is supplied with a word line drive signal.
[0006]
Reference numeral 53 denotes a bit line commonly connected to the drains of the ROM cells in the same column in the memory cell array 50, and only one bit line is typically shown.
In the ROM, for example, one memory cell block shares one bit line (metal wiring) 53 and one virtual ground line (metal wiring) 54.
[0007]
Then, in order to alternatively select the two memory cell blocks, block selection transistors 55 are connected in series so as to selectively connect one end of each memory cell block and the bit line 53, Block selection transistors 56 are connected in series so as to selectively connect the other end of each memory cell block and the virtual ground line. The block selecting transistors 55 and 56 are controlled by block selecting lines 57 and 58.
[0008]
As a result, an "H" level or "L" level read output is obtained from the selected memory cell block in accordance with the write state / non-write state of the selected cell.
[0009]
Reference numeral 10 denotes an enhancement N-channel transistor for selecting a column, 11 denotes an enhancement N-channel transistor for a bit line transfer gate, 12 denotes a bit line potential and a power-down control signal PD, and outputs the bit line transfer gate transistor. This is a two-input NOR gate for feedback supplied to 11 gates.
[0010]
Reference numeral 13 denotes an enhancement-type P-channel transistor for a bit line load whose gate and drain are connected to each other, and 14 denotes a sense line.
The above-described bit line transfer gate transistor 11, feedback NOR gate 12, and load transistor 13 have a function of level-shifting and amplifying the potential amplitude of the bit line.
[0011]
Reference numeral 15 denotes a differential type that determines whether or not the main body cell 51 is in a write state by amplifying a read potential from the main cell 51 by comparing it with a read potential (reference potential Vref) from the dummy cell circuit side. It is a sense amplifier.
[0012]
On the dummy cell circuit side, 51a is a dummy cell, 53a is a dummy bit line, 10a is an enhancement N-channel transistor for selecting a dummy bit line, and a read potential VCC is applied to its gate.
[0013]
11a is an enhancement type N-channel transistor for a transfer gate inserted and connected in series with the dummy bit line, 12a is a two-input NOR gate for feedback to the transfer gate, and 13a is a dummy bit line load having a gate and a drain connected to each other. 14a is a dummy cell side sense line.
[0014]
Next, the read potential from the main body cell 51 and the reference potential Vref from the dummy cell circuit side in the read circuit of FIG. 5 will be briefly described.
When the selected main body cell 51 is in the write state (off state), the potential of the bit line 53 becomes high level “H” when the column selection transistor 10 is in the on state. Conversely, when the selected main body cell 51 is in the non-writing state (ON state), the potential of the bit line 53 becomes low level “L” when the column selection transistor 10 is in the ON state.
[0015]
Here, the respective sizes (channel width W / channel length L) of the dummy cell 51a, the dummy bit line selection transistor 10a, and the dummy bit line transfer gate transistor 11a correspond to the main cell 51 and the column on the main cell side, respectively. The size of each of the selection transistor 10 and the bit line transfer gate transistor 11 is set to be the same.
[0016]
Thus, by providing a read potential VCC to the control gate and sets the dummy cells 51 a to a non-write state, the same to the bit line 53 and the dummy bit line 53a when the body cell 51 selected is non-written state An amount of current flows.
[0017]
Therefore, the size of the dummy cell-side bit line load transistor 13a is set to be larger than the size of the main body cell-side bit line load transistor 13 (for example, the channel width W is set to twice), so that the dummy cell-side bit line load transistor 13a is set. The conductance of the transistor 13a is set higher than the conductance of the transistor 13 for the bit line load on the main body cell side. Accordingly, the reference potential Vref of the dummy cell side sense line 14a is higher than the low level of the main body cell side sense line 14 and lower than the high level of the main body cell side sense line 14 (low level of the main body cell side sense line 14). And a high level).
[0018]
In the above-mentioned ROM, it is desirable to set the threshold value VTH of the cell transistor 51 as high as possible in consideration of a circuit operation margin. In addition, in a burn-in test or the like at the time of manufacturing, the upper limit of the power supply voltage specification (for example, 5. In the specification of 0 ± 0.5 V, the ROM is required to operate normally even at 5.5 V), so the threshold value VTH of the cell transistor is desirably 8 V or more.
[0019]
However, if high-concentration ion implantation is performed to increase the threshold value VTH of the cell transistor 51 to 8 V or more, the crystal lattice of the substrate is damaged, and a leak current flows between the source and the drain of the cell transistor 51. It is known that the yield decreases, and in practice, the threshold value VTH of the cell transistor 51 is set to about 5V.
[0020]
FIG. 6 shows the power supply potential (VCC) dependence of the "H" level and "L" level of the read potential from the main body cell 51 and the reference potential Vref from the dummy cell circuit side.
[0021]
The VCC dependency when reading the “H” level from the main body cell 51 is such that, when the threshold VTH of the cell transistor in the written state is about 5 V, when VCC exceeds 5 V, a leak current starts flowing through the cell transistor in the written state. The H "level decreases, and the characteristic slope becomes gentle from the middle (the characteristic is bent).
[0022]
On the other hand, when the "L" level is read from the main body cell 51, the dependence on VCC is such that even if VCC exceeds 5 V, almost no leakage current flows through the non-written cell transistor, so that the characteristics are bent. There is no.
[0023]
On the other hand, the VCC dependency of the reference potential Vref is such that almost the same current flows to the dummy cell as when the "L" level is read from the main cell 51, and almost no leak current flows to the dummy cell. It will not bend.
[0024]
Therefore, when the power supply potential VCC is increased, the "H" level of the read potential from the main cell 51 crosses the reference potential Vref, so that normal operation cannot be expected, and the upper limit of the usable power supply potential is low. Become.
[0025]
Therefore, in order to increase the operation margin when reading the "H" level from the main body cell 51, it is necessary to set the VCC dependency of the reference potential Vref to bend in the same manner as the VCC dependency at the time of reading the "H" level. It is conceivable, however, that the operation margin at the time of "L" level reading is reduced, which is not preferable.
[0026]
[Problems to be solved by the invention]
As described above, in the conventional ROM, when the power supply potential VCC exceeds the threshold value VTH of the cell transistor when the threshold value VTH of the cell transistor is set relatively low, the "H" level of the read potential from the main body cell and the reference potential There is a problem that normal operation cannot be expected due to the intersection of Vref and the upper limit of the power supply potential at which stable operation is possible.
[0027]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and provides a read-only memory device capable of increasing the upper limit of a power supply potential that enables stable operation even when the threshold value VTH of a cell transistor is set relatively low. The purpose is to:
[0028]
[Means for Solving the Problems]
The present invention relates to a read-only memory device using a sense amplifier for reading cell data by comparing a potential read from a memory cell to a bit line with a potential read from a dummy cell to a dummy bit line. by control the bit line load threshold states of the cell transistor equivalently detect and, with characterized by including the power-dependent compensation circuitry for compensating the power supply voltage dependency of the read potential from cell transistor I do.
[0029]
[Action]
When the threshold value VTH of the cell transistor is set relatively low and the power supply potential VCC exceeds the threshold value VTH of the cell transistor, a leak current flows through the cell transistor in the written state. Since this state is detected by the power supply dependency compensating circuit and the bit line load transistor is turned on, the leak current of the cell transistor is compensated.
Therefore, the VCC dependency at the time of reading the "H" level from the main body cell does not bend, and the upper limit of the power supply potential at which stable operation is possible is increased .
[0030]
【Example】
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 shows a part of a CMOS type mask ROM using a virtual ground type memory cell as a first embodiment of the present invention.
[0031]
Compared to the conventional ROM described above with reference to FIG. 5, this ROM detects the threshold value of the cell transistor in the written state and controls the bit line load (and, if necessary, the dummy bit line load). The difference is that a power supply dependency compensating circuit for compensating the power supply potential dependency of the read potential from the cell transistor is added, and the other components are the same.
[0032]
That is, in FIG. 1, reference numeral 50 denotes a memory cell array in which ROM cells 51 are arranged in a matrix, and a word line 52 is commonly connected to the gates of the cell transistors 53 in the same row in the memory cell array 50. , The bit line 53 is commonly connected to the drains of the cell transistors 51 in the same column.
[0033]
In this example, the memory cell array 50 is divided into a plurality of memory cell blocks. For example, one memory cell block shares one bit line (metal wiring) 53 and one virtual ground line (not shown). ) Are shared, and a block selection transistor (not shown) is connected to select the two memory cell blocks alternatively.
[0034]
Reference numeral 10 denotes an enhancement N-channel transistor for selecting a column, 11 denotes an enhancement N-channel transistor for a bit line transfer gate, 12 denotes a bit line potential and a power-down control signal PD, and outputs the bit line transfer gate transistor. This is a two-input NOR gate for feedback supplied to 11 gates.
[0035]
Reference numeral 13 denotes an enhancement-type P-channel transistor for a bit line load whose gate and drain are connected to each other, and 14 denotes a sense line.
Numeral 15 denotes a differential type sense circuit that determines whether or not the main body cell 51 is in a write state by amplifying a read potential from the main body cell 51 by comparing it with a read potential (reference potential Vref) from the dummy cell circuit side. It is an amplifier.
[0036]
On the side of the dummy cell circuit, 51a has the same structure as the memory cell 51, has a threshold value equivalent to that of the memory cell 51 in a non-written state, and is a first dummy cell transistor having a gate to which a read potential is applied. The first dummy bit line 10a connected to the source or drain of the first dummy cell transistor 51a is an enhancement N-channel transistor for selecting the first dummy bit line, and the read potential VCC is applied to its gate. Is done. 11a is an enhancement type N-channel transistor for a transfer gate inserted in series with the first dummy bit line 53a, 12a is a two-input NOR gate for feedback to the transfer gate 11a, and 13a is a gate-drain connected to each other. An enhancement type P-channel transistor for loading a dummy bit line, 14a is a sense line on the dummy cell side.
[0037]
A row decoder for selecting the word line 52 of the memory cell array 50, a column decoder for controlling the column selection transistor 10, and the like are not shown.
On the other hand, the power supply dependency compensation circuit includes a cell transistor threshold value detection circuit 22 and a load control circuit 24, and is configured as shown in FIG. 2, for example.
[0038]
In the power supply dependency compensating circuit shown in FIG. 2, 53b is a second dummy bit line, 51b is connected to the source or drain of the second dummy bit line 53b, and has the same structure as the memory cell 51. Ion implantation is performed so as to have the same threshold value as that of the memory cell in the state, and the read potential VCC is applied to the gate. The second dummy cell transistor 10b is an enhancement N-channel transistor for selecting a second dummy bit line. The read potential VCC is applied to the gate. 11b is an enhancement type N-channel transistor for a transfer gate inserted in series with the second dummy bit line 53b, and 12b is a two-input NOR gate for feedback to the transfer gate 11b.
[0039]
21 is an enhancement type P-channel transistor for the second dummy bit line load Gate is connected to the ground potential VSS, and is generated when "H" level read from the second dummy cell transistors 51b as described below In order to improve the detection sensitivity of the leak current, it is desirable to make the size sufficiently small.
[0040]
Reference numeral 22 denotes a cell transistor threshold detection circuit that detects the threshold of the cell transistor 51 equivalently by detecting the threshold of the second dummy cell transistor 51b based on the current flowing through the second dummy bit line 53b during data reading. is there.
[0041]
The cell transistor threshold value detection circuit 22 includes, for example, a two-stage connected inverter circuit 23 to which the drain potential of the second dummy bit line load transistor 21 is input, and outputs a control signal B.
[0042]
Reference numeral 24 denotes a load control circuit that receives the detection output B of the cell transistor threshold value detection circuit 22 and controls the load on the bit line 53 and the load on the first dummy bit line 53a. The load control circuit 24 includes two PMOS transistors P1 and P2 connected in series between a VCC node and the sense line 14, and a series connection between the VCC node and the dummy sense line 14a. It consists of two PMOS transistors P1a and P2a.
[0043]
In this case, of the two PMOS transistors P1 and P2, the gate of the transistor P1 is supplied with the control signal B, and the gate of the transistor P2 is connected to its drain (connection node to the sense line 14). Further, of the two PMOS transistors P1a and P2a, the gate of the transistor P1a is supplied with the control signal B, and the gate of the transistor P2a is connected to its drain (connection node with the dummy sense line 14a).
[0044]
Next, the data read operation of the ROM will be described with reference to FIGS.
FIG. 3 shows the VCC dependency of the control signal B output of the cell transistor threshold value detection circuit 22. FIG. 4 shows the "H" level and "L" level of the read potential from the cell transistor 51 and the dummy cell circuit. It shows the VCC dependence of the reference potential Vref from the side.
[0045]
The operation of reading data from the ROM is basically the same as the operation of the ROM shown in FIG. 5, but additionally includes the operation of a newly added power supply dependency compensation circuit.
That is, in the above mask ROM, when the threshold voltage VTH of the cell transistor 51 is set relatively low and the power supply potential VCC exceeds the threshold value VTH of the cell transistor 51, a leak current flows through the cell transistor in the written state.
[0046]
At this time, when VCC exceeds VTH, the control signal B output of the cell transistor threshold value detection circuit 22 is inverted from "H" level to "L" level. As a result, the PMOS transistors P1 and P1a are turned on, and the load current of the bit line 43 and the load current of the first dummy bit line 53a increase. In this case, if the sizes of the four PMOS transistors of the load control circuit 24 are appropriately set, the leak current of the cell transistor 51 will be compensated.
[0047]
Accordingly, the "H" level does not decrease due to the start of the flow of the leak current, the characteristic slope does not become gentle from the middle (the characteristic is bent), and the upper limit of the power supply potential at which stable operation can be performed is reduced. .
[0048]
The two PMOS transistors P1a and P2a connected to the first dummy sense line 14a in the load control circuit 24 need not always be used.
[0049]
Further, the power supply dependency compensating circuit includes at least the second dummy bit line 53b and the second dummy cell transistor 51b, so that the cell transistor threshold value detecting circuit 22 detects the threshold value of the cell transistor 51 equivalently. Is possible.
[0050]
In the above-described embodiment, the ROM using the memory cell of the virtual ground system is described. However, the present invention can be applied to a conventional NOR type ROM when the threshold value VTH of the cell transistor is set near VCC.
[0051]
【The invention's effect】
As described above, according to the present invention, even when the threshold value VTH of the cell transistor is set to a relatively low value, it is possible to realize a ROM capable of increasing the upper limit of the power supply potential that enables stable operation.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a part of a mask ROM according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a specific example of a power supply dependency compensation circuit in FIG. 1;
FIG. 3 is a diagram showing VCC dependence of a control signal B output of the cell transistor threshold value detection circuit in FIG. 2;
FIG. 4 is a diagram showing VCC dependency of “H” level and “L” level of a read potential from a cell transistor and a reference potential Vref from a dummy cell circuit side in the mask ROM of FIG. 1;
FIG. 5 is a circuit diagram showing a part of a conventional mask ROM.
FIG. 6 is a diagram showing VCC dependency of “H” level and “L” level of a read potential from a cell transistor and a reference potential Vref from a dummy cell circuit side in the mask ROM of FIG. 5;
[Explanation of symbols]
10: column selection transistor, 11: bit line transfer gate transistor, 12: NOR gate, 13: bit line load transistor, 14: sense line, 10a: first dummy bit line selection transistor, 11a: first dummy Bit line transfer gate transistors, 12, 12a: NOR gate, 13a: Dummy bit line load transistor, 14a: Dummy sense line, 15: Sense amplifier, 10b: Second dummy bit line selection transistor, 11b: Second dummy Bit line transfer gate transistor, 22: cell transistor threshold detection circuit, 24: load control circuit, 51: cell transistor, 51a: first tammy cell transistor, 51b: second tammy cell transistor, 53: bit line, 53a ... the first dam Bit line, 53b ... second dummy bit line.

Claims (3)

A memory cell array in which read-only memory cell transistors are arranged in a matrix,
A bit line commonly connected to drains of memory cell transistors in the same column in the memory cell array;
A bit line load circuit connected to the bit line;
A first dummy bit line;
A first dummy cell transistor having a drain connected to the first dummy bit line, having the same structure as the memory cell, having a threshold value equivalent to that of a non-written memory cell, and having a gate to which a read potential is applied; When,
A dummy bit line load circuit connected to the first dummy bit line;
A sense amplifier for sensing and amplifying a potential difference between the bit line and the first dummy bit line during data reading;
Wherein detecting the threshold of the cell transistor in a write state in the memory cell array, to control the load of the bit line so as to compensate for the leakage current flowing through the cell transistors of the write state on the basis of the detection output, the read potential of the cell transistor A power-supply-dependency compensating circuit for compensating the power-supply potential dependence of the read-only memory device. The read-only storage device according to claim 1,
The power supply dependency compensation circuit includes:
A second dummy bit line;
A second dummy cell transistor having a drain connected to the second dummy bit line, having a bit line driving capability equivalent to that of a memory cell transistor in a written state in the memory cell array, and a read potential applied to a gate;
A cell transistor threshold value detection circuit for equivalently detecting a threshold value of the cell transistor by detecting a threshold value of the second dummy cell transistor based on a current flowing through the second dummy bit line during data reading;
A read-only memory device comprising: a load control circuit that receives a detection output of the cell transistor threshold value detection circuit and controls a load on the bit line. The read-only storage device according to claim 2 ,
The read-only memory device, wherein the load control circuit further controls a load on the dummy bit line in response to a detection output of the cell transistor threshold value detection circuit.

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