JP3545879B2 - Display element manufacturing method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a display element, and more particularly to a method for manufacturing a display element suitable for application to an active matrix type liquid crystal display device.
[0002]
[Prior art]
In a display device such as a liquid crystal display device, an EL display device, and a plasma display device, a display pattern is formed on a screen by selecting display picture elements arranged in a matrix on an insulating transparent substrate.
[0003]
Here, as a method of selecting a display picture element, individual picture elements are arranged by independent electrodes, a switching element is connected to each of the picture element electrodes, a picture element electrode is selected by the switching element, and display driving is performed. There is an active matrix driving method for performing this. According to this active matrix driving method, a high-contrast display is possible, and it has been put to practical use in liquid crystal televisions, word processors, computer terminal displays, and the like.
[0004]
Here, as the switching element, a TFT (Thin Film Transistor), an MIM element, a MOS transistor element, a diode, and the like are generally used.
[0005]
Meanwhile, recently, a field effect transistor (FET) using amorphous silicon for a semiconductor layer has been used as a switching element provided for each picture element of a liquid crystal display device. The switching element switches a voltage applied between the picture element electrode and a counter electrode facing the picture element electrode. Thereby, the optical modulation of the liquid crystal filled as the display medium during that time is visually recognized as a display pattern.
[0006]
The amorphous silicon FET has advantages such as being able to be formed uniformly on a large transparent substrate and having a large on / off current ratio, and is suitable as a switching element of this type of display device. The amorphous silicon FET is also a type of TFT, and will be described below as a TFT.
[0007]
4 and 5 show a conventional method of manufacturing a liquid crystal display device using such a TFT as a switching device.
[0008]
First, a gate wiring film is formed on the insulating transparent substrate 1. Subsequently, the gate wiring film is patterned by photolithography to form a gate electrode 2 and a gate bus line 2. Next, gate insulating films 3 and 4 are formed on the gate electrode 2, a semiconductor layer 5 and contact layers 6 and 7 are formed, and a pattern other than the gap portion 12 of the contact layers 6 and 7 is formed by photolithography. Perform patterning. Next, the gap portions 12 of the contact layers 6 and 7 are patterned by photolithography.
[0009]
At this time, it is also possible to adopt a manufacturing method in which an etching stopper layer is provided in the gap 12 between the semiconductor layer 5 and the contact layers 6 and 7 to form the gap 12.
[0010]
Next, a film for a source bus line (and a source electrode), a drain electrode and a picture element electrode is formed, and then this film is patterned by photolithography to form the source bus lines 8 and 10, the drain electrode 11 and the picture. The elementary electrodes 9 are formed. At this time, as a countermeasure against defects caused by static electricity generated in a state where the display panel is manufactured, patterning is performed so as to form a so-called short ring structure connecting all the source bus lines 8 and 10 around the panel.
[0011]
As shown in FIG. 5, a semiconductor layer 5 and a contact layer 6 are arranged below (below) the source bus lines 8 and 10. This is because, when the source bus lines 8 and 10 are disconnected for some reason, the source signal is transmitted through the contact layer 6 to the portion after the disconnection, and as a result, the disconnection of the source bus lines 8 and 10 is saved. is there.
[0012]
Further, the overlapping portion of the source bus lines 8 and 10 and the gate bus line 2 is covered with the semiconductor layer 5 and the contact layer 6. This is to reduce disconnection of the source electrodes 8 and 10 which occurs at a portion where the source bus lines 8 and 10 are overlapped with the gate bus line 2 during patterning. Further, the contact layer 6 is shared with the semiconductor layer 5 of the TFT, that is, the a-Si-n + layer. This is to reduce the number of film forming steps and increase production efficiency.
[0013]
[Problems to be solved by the invention]
By the way, in order to exhibit advantages such as being able to be formed uniformly on a large transparent substrate and having a large on / off current ratio, the contact layer 6 needs to be a semiconductor film having a high conductivity. When the patterns of the semiconductor layer 5 and the contact layer 6 are formed, the contact layer 6 needs to be separated for each source bus line 8, 10. This is because the a-si-n + layer is a conductive film, and if it is not separated, a current leak will occur in all of the source bus lines 8 and 10.
[0014]
Therefore, the semiconductor layer 5 and the contact layer 6 under the source bus lines (and the source electrodes) 8 and 10 are formed after the pattern formation of the semiconductor layer 5 and the contact layer 6 until the short ring is formed by the source wiring material. Each source bus line 8, 10 has a shape floating above the gate insulating films 2, 3.
[0015]
For this reason, due to the static electricity generated during this time and the influence of the charging in each step, insulation breakdown (electrostatic breakdown) occurring at the overlapping portion of the source bus lines 8 and 10 and the gate bus line 2 causes the point B in FIG. There is a problem that a leak failure occurs at the point C, and a line-like point defect (display defect of a picture element connected to a TFT with a dielectric breakdown) frequently occurs due to a TFT characteristic deviation generated along the source bus lines 8 and 10. There was a point.
[0016]
When such a problem occurs, the display quality of the display device is significantly impaired, so that the liquid crystal display element is defective. For this reason, the above problem has been a major problem from the viewpoint of improving the product yield.
[0017]
The present invention has been made in view of such circumstances, and it is an object of the present invention to provide a method of manufacturing a display element capable of reliably preventing the above-described leak defects and line-shaped defects and improving display quality and yield. Aim.
[0018]
[Means for Solving the Problems]
Method of manufacturing a display device of the present invention, a plurality of scanning lines and a plurality of signal lines arranged in a grid pattern on an insulating substrate, a plurality of switching electrically connected to the scan lines and the signal lines and the element, below the signal lines, the method of manufacturing a display device comprising a plurality of semiconductor films wiring the respective signal lines are wired along each signal line in a state of being separated from each other, the insulating In the process of forming a plurality of scanning lines on a substrate and when arranging each semiconductor film wiring so as to correspond to a signal line that becomes a grid with each scanning line, the semiconductor film wirings are electrically short-circuited with each other. And thereafter, a step of removing the short-circuit portion of each semiconductor film wiring and separating each semiconductor film wiring, thereby achieving the above object. .
[0019]
Preferably, μc-n + Si is used as the material of the semiconductor film wiring.
[0020]
The operation will be described below.
[0021]
As described above, if the semiconductor film wiring disposed below each source bus line is formed in a pattern structure in which each is completely electrically short-circuited in advance and then separated in a subsequent step, It is possible to prevent dielectric breakdown at a superimposed portion of a source bus line (signal line) and a gate bus line (scanning line), which is generated due to static electricity generated during the process until the process is performed and charging at each process. That is, a high voltage is not applied to the overlapping portion of the specific source bus line and the gate bus line due to the short circuit, so that the dielectric breakdown can be prevented.
[0022]
For this reason, it is possible to prevent leak failure due to dielectric breakdown. In addition, it is possible to prevent a linear point defect due to a TFT characteristic deviation generated along the source bus line. Further, since the semiconductor film wiring is separated for each source bus line portion in a later step, a high yield can be achieved without affecting display quality.
[0023]
In addition, since there is no such a problem, it becomes possible to use μc-n + Si having a conductivity 1000 times or more that of the conventional a-Si-n + layer as a material of the semiconductor film wiring. For this reason, when the source bus line is disconnected, it becomes easier to transmit the source signal to the portion after the disconnection.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.
[0025]
(Embodiment 1)
1 and 2 show Embodiment 1 of the manufacturing method of the present invention. FIG. 2 shows a planar structure of a liquid crystal display device manufactured by the manufacturing method of the present invention. A gate bus line 20 and a source bus line 22 are arranged in a grid on a glass substrate (not shown) which is a transparent insulating substrate, and a rectangular bus surrounded by the gate bus line 20 and the source bus line 22 is formed. Pixel electrodes 25 are arranged in a matrix in the region. A gate electrode 20a branched from the gate bus line 20 and a source electrode 23 branched from the source bus line 22 are superimposed on one corner of the pixel electrode 25, and a TFT 30 as a switching element is formed here. Have been. Other configurations will be clarified in the following manufacturing steps.
[0026]
First, as shown in FIG. 1, a metal such as Al, Mo, and Ta is formed on a glass substrate which is a transparent insulating substrate by a sputtering method. Subsequently, this film is patterned by photolithography to form a gate bus line 20 and a gate electrode 20a.
[0027]
Next, the surfaces of the gate bus line 20 and the gate electrode 20a are covered with a gate material oxide film by using an anodic oxidation method, and in order to further enhance the insulating property, a 300 nm SiNx film is laminated by a plasma CVD method or the like. Form a film.
[0028]
Subsequently, a semiconductor layer and a contact layer for improving ohmic contact between the semiconductor layer and the source electrode or the drain electrode are respectively stacked by a plasma CVD method successively to the gate insulating film. Although the gate insulating film, the semiconductor layer and the contact layer are not shown, the laminated structure is the same as that of the conventional example shown in FIG.
[0029]
Here, the semiconductor layer of the first embodiment is an intrinsic semiconductor amorphous silicon film (hereinafter, referred to as an a-Si (i) layer) having a thickness of 60 to 130 nm. The contact layer was made of n + -type microcrystalline silicon to which phosphorus was added (hereinafter referred to as μc-n + Si layer) and had a thickness of 100 nm. In this case, it is also possible to provide an etching stopper layer between the semiconductor layer and the contact layer by patterning.
[0030]
Next, the a-Si (i) layer and the μc-n + Si layer are patterned by photolithography to form a wiring 21 for a semiconductor layer and a contact layer. At this time, the wiring 21 (see FIG. 2) for the semiconductor layer and the contact layer is patterned while leaving the source bus line 22 at a place where the source bus line 22 is to be formed, and as shown in FIG. Is formed in a short-circuited pattern structure. That is, the wirings 21 located below the source bus line 22 are connected to each other by the short-circuiting wiring 21 a parallel to the gate bus line 20. At this point, patterning of the gap portion 31 of the TFT 30 is not performed.
[0031]
Here, the μc-n + Si layer has a conductivity 1000 times or more higher than that of the conventional a-Si-n + layer, and even when the source bus line 22 is disconnected, the source is connected via the μc-n + Si layer. It becomes easier to transmit the signal after the break.
[0032]
Next, in order to form the signal extraction terminal pad portions 26 and 27 of the gate bus line 20 and the source bus line 22, the anodic oxide film and the gate insulating film are etched into a predetermined pattern by photolithography. At this time, as shown in FIG. 2, the intermediate portion D of the short-circuit wiring 21a of the wiring 21 for the semiconductor layer and the contact layer is simultaneously etched. Thus, each wiring 21 is separated for each source line 22 portion.
[0033]
Next, as a source conductor, an ITO (Indium Tin Oxide) film also serving as a pixel electrode later and a metal film of Ti, A1, Cr, Mo, or the like are continuously formed by a vapor deposition method, a sputtering method, or the like, and then photolithography is performed. By patterning, a source bus line 22, a source electrode 23, a drain electrode 24, and a picture element electrode 25 are sequentially formed (see FIG. 2). Note that the source conductor may have a structure of only the ITO film which is a transparent electrode material.
[0034]
Next, the μc-n + Si layer of the TFT 30 is patterned by dry etching to form a gap portion 31 of the TFT 30. Note that the formation of the TFT gap portion 31 can also be performed by photolithography. Further, it can be formed by dry etching using the source electrode 23 and the drain electrode 24 as a mask.
[0035]
Next, a protective film layer made of SiNx or the like is formed on the gap portion 31 of the TFT 30, and thus the liquid crystal display device shown in FIG. 2 is manufactured.
[0036]
(Embodiment 2)
FIG. 3 shows Embodiment 2 of the manufacturing method of the present invention. In the second embodiment, the step of etching the intermediate portion D of the short-circuit wiring 21a of the wiring 21 for the semiconductor layer and the contact layer is performed simultaneously with the step of dry-etching the μc-n + Si layer of the TFT 30. Except for this point, the third embodiment is the same as the first embodiment.
[0037]
Note that the same reference numerals are given to portions corresponding to the first embodiment, and a specific description is omitted.
[0038]
(Other embodiments)
In each of the above embodiments, the case where the present invention is applied to a method of manufacturing a liquid crystal display element has been described. However, the method of the present invention is directed to a method of manufacturing a display element for another display device such as an EL display device and a plasma display device. Is similarly applicable.
[0039]
Further, in each of the above embodiments, a case where a TFT is used as a switching element is described as an example. However, the present invention is also applicable to a display element using a MIM element, a MOS transistor element, a diode, or the like as a switching element. The same applies.
[0040]
【The invention's effect】
According to the present invention described above, the semiconductor film wiring arranged below each source bus line is formed in advance in a pattern structure in which each is completely electrically short-circuited, and is separated in a subsequent step. It is possible to prevent dielectric breakdown at a superimposed portion of a source bus line (signal line) and a gate bus line (scanning line), which is generated due to static electricity generated during the process until the process is performed and charging at each process. That is, a high voltage is not applied to the overlapping portion of the specific source bus line and the gate bus line due to the short circuit, so that the dielectric breakdown can be prevented.
[0041]
For this reason, it is possible to prevent leak failure due to dielectric breakdown. In addition, it is possible to prevent a linear point defect due to a TFT characteristic deviation generated along the source bus line. Further, since the semiconductor film wiring is separated for each source bus line portion in a later step, a high yield can be achieved without affecting display quality.
[0042]
In particular, according to the method of manufacturing a display element according to the second aspect, μc-n + Si having a conductivity 1000 times or more that of the conventional a-Si-n + layer is used as a material of the semiconductor film wiring. When the source bus line is disconnected, there is an advantage that it is easier to transmit the source signal to the portion after the disconnected portion.
[Brief description of the drawings]
FIG. 1 is a plan view of a liquid crystal display element, showing Embodiment 1 of a method for manufacturing a display element of the present invention.
FIG. 2 is a plan view of the liquid crystal display element, showing Embodiment 1 of the method for manufacturing a display element of the present invention.
FIG. 3 is a plan view of a liquid crystal display element, showing Embodiment 2 of the method for manufacturing a display element of the present invention.
FIG. 4 is a plan view showing a conventional liquid crystal display element.
FIG. 5 is a sectional view taken along line AA of FIG. 4;
[Explanation of symbols]
Reference Signs List 20 gate bus line 20a gate electrode 21 wiring 21a for semiconductor layer and contact layer 21a short-circuit wiring 22 source bus line 23 source electrode 24 drain electrode 25 picture element electrode 26 gate bus line signal extraction terminal pad section 27 source bus line signal Leader terminal pad 30 TFT
31 TFT gap

Claims (2)

A plurality of scanning lines and a plurality of signal lines wired in a grid on an insulating substrate,
A plurality of switching elements electrically connected to each scanning line and each signal line,
A method for manufacturing a display element comprising a plurality of semiconductor film wirings arranged along each signal line while being separated from each signal line below each signal line,
Forming a plurality of scanning lines on the insulating substrate,
Forming an insulating film so as to cover the scanning line;
When wiring each semiconductor film wiring so as to correspond to the signal line that becomes a lattice shape with each scanning line, pattern formation so that each semiconductor film wiring is electrically short-circuited mutually in a region that does not overlap with the pixel electrode The process of
Thereafter, a step of removing the short-circuit portion of the semiconductor film wires respectively, separation for each semiconductor film wires,
A method for manufacturing a display element, comprising: 2. The method according to claim 1, wherein μc-n + Si is used as a material of the semiconductor film wiring.

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