JP3546166B2 - Voltage comparison circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a voltage comparison circuit that compares an input signal voltage with a predetermined threshold voltage and outputs the result as a voltage comparison output.
[0002]
[Prior art]
Conventionally,FIG.A voltage comparison circuit described below has been proposed with reference to "K. Maezawa and T. Mizutani," A New Resonant Tunneling Logic Gate Employing Monostable-Bisable Translation, "Jpn. 32, pp. 42-44, 1993).
That is, a first negative resistance element circuit B1 having one two-terminal negative resistance element D1 and a second negative resistance element circuit B2 also having one two-terminal negative resistance element D2 are connected in series. And the drain is connected to a connection point P between the first and second negative resistance element circuits B1 and B2 of the series negative resistance element circuit G, and the source is connected in series. A field effect transistor M connected to one end of the negative resistance element circuit G on the negative resistance element circuit B2 side.
[0003]
One end of the series negative resistance element circuit G on the negative resistance element circuit B1 side is connected to the low voltage V._L "0" in binary display and high voltage V_H The negative resistance element of the series negative resistance element circuit G is connected to a clock signal voltage source terminal Ec that outputs a clock signal voltage Vc that repeats alternately taking a binary display “1” meaning “1”. The other end of the circuit B2 is connected to a constant voltage source terminal E1 that outputs a constant voltage V1, so that the clock signal voltage Vc is applied across the series negative resistance element circuit G. .
[0004]
Further, the gate of the field effect transistor M is connected to the signal input terminal IN where the input signal voltage Vi is obtained, and further, from the connection point P between the negative resistance element circuits B1 and B2 of the series negative resistance element circuit G, An output terminal OUT is derived.
[0005]
In this case, the two-terminal negative resistance element D1 of the negative resistance element circuit B1 and the two-terminal negative resistance element D2 of the negative resistance element circuit B2 are:FIG.Has an N-shaped current-voltage characteristic as shown in FIG.
That is, if the current is increased in the positive direction from the zero value, the voltage becomes a voltage value correspondingly increased in the positive direction from the zero value._P Is reached, the voltage becomes the current voltage value V_p From the higher voltage value V_q And if the current is increased from that state, the voltage is accordingly changed to the voltage value V_q From this state, the voltage value becomes higher in the positive direction, and if the current is further reduced from that state, the voltage value becomes lower in the negative direction accordingly._r Is reached, the voltage becomes the current voltage value V_r From the lower voltage value V_s And if the current is reduced from that state, the voltage has a characteristic that the voltage becomes correspondingly lower in the negative direction from the voltage at that time.
[0006]
Accordingly, the peak current value I as seen from the current-voltage characteristics of the two-terminal negative resistance element D1_P To I_P1And the voltage value V_P , V_q , V_r And V_s Is V_P1, V_q1, V_r1And V_s1And the current value I_r To I_r1Then, the two-terminal negative resistance element D1 and the negative resistance element circuit B1 having only the same areFIG.Have current-voltage characteristics as shown in FIG.
[0007]
Further, the peak current value I seen from the current-voltage characteristics of the two-terminal negative resistance element D2_P To I_P2And the voltage value V_P , V_q , V_r And V_s Is V_P2, V_q2, V_r2And V_s2And the current value I_r To I_r2Then, the two-terminal negative resistance element D2 and the negative resistance element circuit B2 having only the same areFIG.Have current-voltage characteristics as shown in FIG. However, in this case, the peak current value I_P2Is the peak current value I of the two-terminal negative resistance element D1._P1Less than (I_P1> I_P2).
[0008]
Further, the field-effect transistor M is, for example, an n-type. In this case, the field-effect transistor M passes through the middle point P of the connection between the negative resistance element circuits B1 and B2 and the constant voltage source terminal E1 to generate a drain current. There is a characteristic that the drain current value increases as the input signal voltage Vi applied to the gate increases in the positive direction.
[0009]
When a parallel circuit of the negative resistance element circuit B2 and the field-effect transistor M is a composite circuit C, the composite circuit C includes a connection point P between the negative resistance element circuits B1 and B2 and a constant voltage source terminal E1. And a current that flows through the two-terminal negative resistance element D2 and the drain current of the field effect transistor M.
[0010]
Therefore, the composite circuit C has a peak current value I based on the current-voltage characteristics of the two-terminal negative resistance element D2._P2, Voltage value V_P2, V_q2, V_r2And V_s2, Current value I_r2, The respective peak current values I_P2', Voltage value V_P2', V_q2', V_r2'And V_s2', Current value I_r2′,FIG.As shown in FIG. 7, the peak current I depends on the input signal voltage Vi applied to the gate of the field effect transistor M._p2′ Change and have an N-shaped current-voltage characteristic.
[0011]
The above is the configuration of the conventionally proposed voltage comparison circuit.
According to the conventional voltage comparison circuit having such a configuration, as described below, the input signal voltage Vi is set to the predetermined threshold voltage (this is set to V_T ) And outputs the result as a voltage comparison output. Here, the threshold voltage V_T Is the peak current value I of the two-terminal negative resistance element D1._P1And the peak current value I of the two-terminal negative resistance element D2_P2Is equal to (I_P1= I_P2) Is the value of the input signal voltage Vi.
[0012]
First, when the input signal voltage Vi is equal to the threshold voltage V_T (Vi <V_T ) The case will be described.
In this case, the peak current value I of the composite circuit C_p2Is the peak current value I of the negative resistance element circuit B1._p1Less than (I_p2'<I_p1). For this reason, the low voltage value V meaningd to “0” in the binary display taken by the clock signal voltage Vc._L And the high voltage value V meaning "1" in the binary display_H Is appropriately selected at the output terminal OUT, depending on whether the clock signal voltage Vc takes "0" or "1" in binary representation, "0" or "2" in binary representation. An output voltage of "1" is obtained, which situation will be described in detail below.
[0013]
FIG.The conventional voltage comparison circuit shown in FIG. 1 uses the clock signal voltage Vc to calculate the threshold voltage V of the input signal voltage Vi._T And outputs a voltage comparison output to the output terminal OUT. When the clock signal voltage Vc is the current time point t and the sequential time points are t1, t2, t3, t4, t5, t6, and t7. and when,11 and 13As shown in FIG. 5, during the period from time t1 to time t3 (t1 <t <t3), the low voltage value V_L From high voltage value V_H Until the time t3 to the time t4 (t3 <t <t4), the high voltage value V_H During the period from time t4 to time t6 (t4 <t <t6), the high voltage value V_H From low voltage value V_L From time t6 to time t7 (t6 <t <t7), the low voltage value V_L And the same is repeated hereafter.
[0014]
On the other hand, the negative resistance element circuit B1 functions as a load circuit of the composite circuit C. For this reason,FigureAs shown in FIG.FIG.In the diagram showing the current-voltage characteristic shown by the curve H2, the negative resistance element circuit B1FIG.Can be written as the load line H1 as shown by the dotted line, intersecting with the curve H2 representing the current-voltage characteristic of the composite circuit C.
[0015]
Therefore, the peak current value I of the composite circuit C_p2Is the peak current value I of the negative resistance element circuit B1._p1Less than (I_P2'<I_P1), The output voltage obtained at the output terminal OUT is obtained by taking the following voltage value.
[0016]
That is, from the time point t1 to the time point t2 (t1 <t <t2), the intersection Q at which the load line H1 intersects the curve H2 isFIG. 10AAs shown in FIG._L2'From the position V_P2′, So that the output voltage obtained at the output terminal OUT isFIG. 11BAs shown in FIG._L2'To the voltage value V_P2′ Takes a voltage value that increases with time.
[0017]
When the time point t2 is reached (t = t2), the intersection Q becomesFIG. 10BAs shown in FIG._P2'From the position V_A1And the output voltage obtained at the output terminal OUT isFIG. 11BAs shown in FIG._P2'To the voltage value V_A1Transfer to
[0018]
Further, between the time point t2 and the time point t3 (t2 <t <t3), the intersection Q isFIG. 10CAs shown in FIG._A1From the position V_H2′, And the output voltage obtained at the output terminal OUT isFIG. 11BAs shown in FIG._A1From the voltage value V_H2′.
[0019]
Further, from the time point t3 to the time point t4 (t3 <t <t4), the intersection Q does not move, so that the output voltage obtained at the output terminal OUT changes to the voltage value V_H2′.
[0020]
Between the time point t4 and the time point t5 (t4 <t <t5), the intersection Q is at the voltage value V_H2'From the position V_A2And the output voltage obtained at the output terminal OUT isFIG. 11BAs shown in FIG._H2'To the voltage value V_A2To a voltage value that decreases with time.
[0021]
Furthermore, when the time point t5 is reached (t = t5), the intersection Q becomesFIG. 10DAs shown in FIG._A2From the position V_A3And the output voltage obtained at the output terminal OUT isFIG. 11BAs shown in FIG._A2From the voltage value V_A3Transfer to
[0022]
Also, between the time point t5 and the time point t6 (t5 <t <t6), the intersection Q isFIG. 10EAs shown in FIG._A3From the position V_L2′, And the output voltage obtained at the output terminal OUT isFIG. 11BAs shown in FIG._A3From the voltage value V_L2′.
[0023]
Further, after the time point t6 (t6 <t <t7), the intersection Q does not move, so that the output voltage obtained at the output terminal OUT becomesFIG. 11BAs shown in FIG._L2′.
[0024]
From the above,FIG.In the case of the conventional voltage comparison circuit shown in FIG.FIG. 14AAs shown in FIG._T From a lower voltage value than the threshold voltage V_T If the input signal voltage Vi takes a voltage value that increases with time up to a higher voltage value than the threshold voltage V_T Voltage value (Vi <V_T ), The clock signal voltage Vc isFIG. 14BAs shown in FIG. 5, depending on whether the binary value takes "0" or "1", an output voltage that takes "0" or "1" in binary value is output to the output terminal OUT.FIG. 14CAs shown in10 and 11And the above-described voltage value is obtained.
[0025]
Next, when the input signal voltage Vi becomes the threshold voltage V_T Higher than (Vi> V_T ) The case will be described.
In this case, the peak current value I of the composite circuit C_p2Is the peak current value I of the negative resistance element circuit B1._p1Is greater. For this reason, as will be described in detail in [Problems to be Solved by the Invention], regardless of whether the clock signal voltage Vc takes binary "0" or "1" at the output terminal OUT, 2 An output voltage that takes only the value "0" is obtained.
[0026]
From the above,FIG.According to the conventional voltage comparison circuit shown in FIG._T Lower than (Vi> V_T ), Depending on whether the clock signal voltage Vc takes a binary value of “0” or “1”, an output voltage of a binary value of “0” or “1” is obtained at the output terminal OUT. And the input signal voltage Vi is the threshold voltage V_T Higher than (Vi> V_T ), An input signal indicating that an output voltage having a binary value “0” is obtained at the output terminal OUT regardless of whether the clock signal voltage Vc takes a binary value “0” or “1”. Threshold voltage V of voltage Vi_T And a function of outputting a voltage comparison output compared with.
[0027]
[Problems to be solved by the invention]
FIG.In the conventional voltage comparison circuit shown in FIG._T Higher than (Vi> V_T ), The peak current value I of the composite circuit C_p2Is the peak current value I of the negative resistance element circuit B1._p1Greater than (I_p2'> I_p1), The output voltage obtained at the output terminal OUT is obtained by taking the voltage value described below.
[0028]
That is, from the time point t1 to the time point t2 (t1 <t <t2), the intersection Q at which the load line H1 intersects the curve H2 isFIG.As shown in FIG._L2'From the position V_B1Move with time toward the position of, so that the output voltage obtained at the output terminal OUT isFIG. 13BAs shown in FIG._L2'To the voltage value V_B1To take a voltage value that increases with time.
[0029]
When the time point t2 is reached (t = t2), the intersection Q becomesFIG.As shown in FIG._B1From the position V_B2And the output voltage obtained at the output terminal OUT isFIG. 13BAs shown in FIG._B1From the voltage value V_B2Transfer to
[0030]
Further, between the time point t2 and the time point t3 (t2 <t <t3), the intersection Q isFIG. 12CAs shown in FIG._B2From the position V_B3, And the output voltage obtained at the output terminal OUT becomesFIG. 13BAs shown in FIG._B2From the voltage value V_B3Take a voltage value that increases to
[0031]
Further, between the time point t3 and the time point t4 (t3 <t <t4), the intersection Q does not move, so that the output voltage obtained at the output terminal OUT changes to the voltage value V_B3Keep.
[0032]
Between the time point t4 and the time point t5 (t4 <t <t5), the intersection Q is_B3From the position V_B4And the output voltage obtained at the output terminal OUT isFIG. 13BAs shown in FIG._B3From the voltage value V_B4To a voltage value that decreases with time.
[0033]
Furthermore, when the time point t5 is reached (t = t5), the intersection Q becomesFIG. 12DAs shown in FIG._B4From the position V_B5And the output voltage obtained at the output terminal OUT isFIG. 13BAs shown in FIG._B4From the voltage value V_B5Transfer to
[0034]
Also, during the period from time t5 to time t6 (t5 <t <t6), the intersection QFIG. 12EAs shown in FIG._B5From the position V_L2′, And the output voltage obtained at the output terminal OUT isFIG. 13BAs shown in FIG._B5From the voltage value V_H2′.
[0035]
Further, after the time point t6 (t6 <t <t7), the intersection Q does not move, so that the output voltage obtained at the output terminal OUT becomesFIG. 13BAs shown in FIG._L2′.
[0036]
From the above,FIG.In the case of the conventional voltage comparison circuit shown in FIG.FIG. 14AAs shown in FIG._T Voltage value (Vi> V_T ), The clock signal voltage Vc isFIG. 14BAs shown in FIG. 7, an output voltage that takes only binary display “0” regardless of whether it takes binary display “0” or “1” is output terminal OUT,FIG. 14CAs shown in12 and 13And the above-described voltage value is obtained.
[0037]
For this reason, especially, when the input signal voltage Vi becomes the threshold voltage V_T In the section having a higher voltage value, the output voltage that takes only “0” in binary display is the high voltage value V_H Therefore, it has a drawback that it may be regarded as "1" in binary display, and that it can be obtained only with a spike.
Therefore, the present invention proposes a novel voltage comparison circuit that does not have the above-mentioned disadvantages.
[0038]
[Means for Solving the Problems]
Application1The voltage comparison circuit according to the present invention comprises: (A) a first negative resistance element circuit having one two-terminal negative resistance element or a plurality of n two-terminal negative resistance elements connected in series; One two-terminal negative resistance element or a plurality of n two-terminal negative elements connected in series depending on whether the first negative resistance element circuit has one or two n-terminal negative resistance elements. A first series negative resistance element circuit in which a second negative resistance element circuit having a negative resistance element is connected in series, and a drain connected to the first and second negative resistance element circuits of the first series negative resistance element circuit. And a first field-effect transistor having a source connected to one end of the first series negative resistance element circuit or a power supply terminal supplied with a constant voltage. "0" and "1" in binary notation between both ends of the first series negative resistance element circuit. A clock signal voltage that repeats the above operation is applied, and an input signal voltage is applied to the gate of the first field-effect transistor. A first voltage output circuit having a connection point of the second negative resistance element circuit as a first output terminal from which a first output voltage is output; and (B) the first and second voltage output circuits. One two-terminal negative resistance element or a plurality of n-terminal two-terminal negative resistance elements connected in series depending on whether the negative resistance element circuit has one or two n-terminal negative resistance elements. A third negative resistance element circuit having an element, and one two-terminal negative resistance element depending on whether the third negative resistance element circuit has one or a plurality of n two-terminal negative resistance elements. Element or a plurality of n two-terminal negative resistance elements connected in series A second series negative resistance element circuit in which the fourth series negative resistance element circuit is connected in series, and a third and fourth negative resistance element circuit of the second series negative resistance element circuit. And a second field-effect transistor having a source connected to one end of the second series negative resistance element circuit or a power supply terminal to which a constant voltage is applied, and The clock signal voltage is applied between both ends of the series negative resistance element circuit, the input signal voltage is applied to the gate of the second field effect transistor, and the second series negative resistance is applied. A second voltage output circuit configured such that a connection point between the third and fourth negative resistance element circuits of the negative resistance element circuit is a second output terminal from which a second output voltage is output; C) output from the first output terminal of the first voltage output circuit And a differential circuit configured to receive a first output voltage and a second output voltage output from a second output terminal of the second voltage output circuit, and output a difference voltage between the two. And (D) outputting the difference voltage output from the differential circuit as a voltage comparison output that is compared with a predetermined threshold voltage of the input signal voltage.
[0039]
The voltage comparison circuit according to the second invention of the present application is:A plurality of n units connected in seriesA first negative resistance element circuit having a two-terminal negative resistance element,A plurality of n units connected in seriesA first series negative resistance element circuit in which a second negative resistance element circuit having a two-terminal negative resistance element is connected in series; and a drain connected to the first negative resistance element circuit of the first series negative resistance element circuit. And a field-effect transistor connected to a connection midpoint of the second negative resistance element circuit and having a source connected to one end of the first series negative resistance element circuit or a power supply terminal to which a constant voltage is applied. Then, a clock signal voltage that repeatedly takes "0" and "1" in binary display is applied between both ends of the first series negative resistance element circuit, and is applied to the gate of the field effect transistor. An input signal voltage is applied, and a connection midpoint between the first and second negative resistance element circuits of the first series negative resistance element circuit isTake (n + 1) value(B) a first voltage output circuit configured to be a first output terminal from which a first output voltage is output;A plurality of n units connected in seriesA third negative resistance element circuit having a two-terminal negative resistance element,A plurality of n units connected in seriesA second series negative resistance element circuit in which a fourth negative resistance element circuit having a two-terminal negative resistance element is connected in series, between both ends of the second series negative resistance element circuit; The clock signal voltage is applied to the second series negative resistance element circuit, and the connection middle point of the third and fourth negative resistance element circuits is connected to the second series negative resistance element circuit.Take (n + 1) valueA second voltage output circuit configured to serve as a second output terminal from which a second output voltage is output; and (C) a first voltage output from the first output terminal of the first voltage output circuit. And a differential circuit configured to receive the output voltage of the second voltage output circuit and the second output voltage output from the second output terminal of the second voltage output circuit, and output a difference voltage between the two. (D) The differential voltage output from the differential circuit is output as a voltage comparison output that is compared with a predetermined threshold voltage of the input signal voltage.
[0040]
[The first of this applicationFirst Embodiment of the Invention
Next, with reference to FIG.First invention of the present applicationA first embodiment of the voltage comparison circuit according to the present invention will be described.
In FIG.FIG.The same reference numerals are given to the parts corresponding to and the detailed description is omitted.
[0041]
Shown in FIG.First invention of the present applicationVoltage comparison circuitFirst EmbodimentHas a first voltage output circuit U1, a second voltage output circuit U2, and a differential circuit F.
In this case, the voltage output circuit U1FIG.The negative resistance element circuit B1 having the two-terminal negative resistance element D1 and the negative resistance element circuit B2 having the two-terminal negative resistance element D2 are connected in series, as described in the conventional voltage comparison circuit shown in FIG. And a field-effect transistor M connected in the same manner.
[0042]
AndFIG.Similarly, one end of the series negative resistance element circuit G is connected to the clock signal voltage source end Ec, the other end is connected to the constant voltage source end E1, and the field-effect transistor The gate of M is connected to the signal input terminal IN, and the output terminal OUT (hereinafter, referred to as OUT1) is derived from the connection point P between the negative resistance element circuits B1 and B2.
In this case, the two-terminal negative resistance element D1 and the negative resistance element circuit B1 having only the same are also provided.FIG.As in the case of the conventional voltage comparison circuit shown in FIG.FIG.Have current-voltage characteristics as shown in FIG.
[0043]
Further, a two-terminal negative resistance element D2 and a negative resistance element circuit B2 having only the same are also provided.FIG.As in the case of the conventional voltage comparison circuit shown in FIG.FIG.Have current-voltage characteristics as shown in FIG.
Further, the field effect transistor MFIG.Has the same characteristics as those of the conventional voltage comparison circuit shown in FIG.
Further, a composite circuit C, which is a parallel circuit of the negative resistance element circuit B2 and the field effect transistor M,FIG.As in the case of the conventional voltage comparison circuit shown in FIG.FIG.Have current-voltage characteristics as shown in FIG.
[0044]
Further, the voltage output circuit U2 includes a third negative resistance element circuit B3 having one two-terminal negative resistance element D3 and a fourth negative resistance element having the same two-terminal negative resistance element D4. There is a second series negative resistance element circuit G2 connected to the element circuit B4 in series.
[0045]
One end of the series negative resistance element circuit G2 on the side of the negative resistance element circuit B3 is connected to the clock signal voltage source end Ec, and the other end of the series negative resistance element circuit B4 is connected to the constant voltage source end E1. The output terminal OUT2 is derived from a connection point P2 between the negative resistance element circuits B3 and B4.
In this case, the two-terminal negative resistance elements D3 and D4, andThoseHave the same current-voltage characteristics as the two-terminal negative resistance elements D1 and D2, but have their peak current values of I_P3And I_P4And I_P3<I_P4Has the relationship
[0046]
In the voltage output circuit U2, the drain is connected to the connection point P2 between the negative resistance element circuits B3 and B4, and the source is connected to one end of the series negative resistance element circuit G2 on the negative resistance element circuit B4 side. And the gate of the field-effect transistor M2 is connected to the signal input terminal IN.
[0047]
Therefore, like the voltage output circuit U1, the voltage output circuit U2 changes the input signal voltage Vi to a predetermined threshold voltage (this is referred to as V_T2) And outputs the result as a voltage comparison output.
However, in this case, the peak current value I of the negative resistance element circuit B3 is_P3And the peak current value I of the negative resistance element circuit B4_P4Is the threshold voltage V_T2Is the threshold voltage V of the voltage output circuit U1._T , For example, the threshold voltage V_T It is chosen to take a smaller value.
[0048]
Further, although the differential circuit F may have various configurations known per se, as shown, for example, the differential circuit F has two field-effect transistors Q1 and Q2, and their sources are shared by them. , And the drains of the field effect transistors Q1 and Q2 are connected to the voltage source terminal EF through load resistors R1 and R2, respectively.
[0049]
The gates of the field effect transistors Q1 and Q2 are connected to the output terminal OUT1 of the voltage output circuit U1 and the output terminal OUT2 of the voltage output circuit U2, respectively, and the connection between the drain of the field effect transistor Q2 and the load resistor R2. From the point, the output terminal OUT is derived.
In this case, the differential circuit F receives the output voltage output from the output terminal OUT1 of the voltage output circuit U1 and the output voltage output from the output terminal OUT2 of the voltage output circuit U2, and outputs the difference voltage between the two. It has the characteristic of outputting to the terminal OUT.
[0050]
More than,First invention of the present applicationOf the voltage comparison circuit1It is a configuration of the embodiment.
Having such a configurationFirst invention of the present applicationVoltage comparison circuitFirst EmbodimentAccording to FIG.5It has a configuration similar to that of the voltage comparison circuit.
[0051]
Therefore, although detailed description is omitted, the clock signal voltage Vc isSimilar to that shown in FIG. 14BWhen a voltage value as shown in FIG. 2B is taken, the input signal voltage Vi becomesFIG. 14AAs shown in FIG. 2A similar to that shown in FIG._T From a lower voltage value than the threshold voltage V_T If the input signal voltage Vi takes a voltage value that increases with time up to a higher voltage value than the threshold voltage V_T In the lower section, the output voltage that takes on “0” or “1” in binary display depends on whether the clock signal voltage Vc takes “0” or “1” in binary display. OUT1FIG. 14CAs shown in FIG. 2C, the same voltage value is obtained.
[0052]
Further, the voltage output circuit U2 detects the threshold voltage V of the voltage output circuit U1._T Threshold voltage V which is smaller_T2Except that it has the same configuration as the voltage output circuit U1.
For this reason, although the detailed description is omitted, the input signal voltage Vi is equal to the threshold voltage V_T2Voltage value (Vi <V_T2), The output voltage at which the clock signal voltage Vc takes “0” or “1” in binary display, depending on whether the clock signal voltage Vc takes “0” or “1” in binary display, OUT2, as shown in FIG. 2D, the input signal voltage Vi is applied to the output terminal T1 at the threshold voltage V_T Lower sectionFIG. 14CAnd the same voltage value as obtained as shown in FIG.
[0053]
Further, when the input signal voltage Vi is equal to the threshold voltage V_T2Voltage value (Vi> V_T2), An output voltage that takes only binary “0” is output to the output terminal OUT2 regardless of whether the clock signal voltage Vc takes “0” or “1” in binary. As shown in FIG. 2C, the input signal voltage Vi is applied to the output terminal T1 by the threshold voltage V_T Higher sectionFIG. 14CAnd the same voltage value as obtained as shown in FIG.
[0054]
Further, the differential circuit F performs a differential operation by using the output voltage as shown in FIG. 2C and the output voltage as shown in FIG. 2D as inputs.
Therefore, the input voltage Vi becomes the threshold voltage V_T2Lower voltage values (Vi <V_T2), An output voltage that takes only binary display “0” is output to the output terminal OUT regardless of whether the clock signal voltage Vc takes “0” or “1” in binary display. It is obtained by taking a voltage value without spikes as shown in FIG. 14C.
[0055]
Further, when the input signal voltage Vi is equal to the threshold voltage V_T2Higher than the threshold voltage V_T Voltage value (V_T2<Vi <V_T ), The output voltage at which the clock signal voltage Vc takes “0” or “1” in binary display depending on whether the clock signal voltage Vc takes “0” or “1” in binary display, OUT is obtained by taking a voltage value without spikes, as shown in FIG. 2E, almost similar to that shown in FIG. 14C.
[0056]
Further, when the input voltage Vi is equal to the threshold voltage V_T Higher voltage value (Vi> V_T ), An output voltage that takes only binary display “0” is output to the output terminal OUT regardless of whether the clock signal voltage Vc takes “0” or “1” in binary display. It is obtained by taking a voltage value without spikes as shown in FIG. 14C.
[0057]
From the above, according to the voltage comparison circuit of the present invention shown in FIG. 1, the two threshold voltages V of the input voltage Vi_T And V_T2Can be easily obtained without spikes.
[0058]
[The first of this applicationEmbodiment of the Invention2]
next,FIG.WithFirst invention of the present applicationOf the voltage comparison circuitSecondAn embodiment will be described.
FIG.AtFIG.The same reference numerals are given to the parts corresponding to and the detailed description is omitted.
[0059]
FIG.Shown inFirst invention of the present applicationVoltage comparison circuit2nd Embodiment ofIs, except for the following:FIG.Has the same configuration as the voltage comparison circuit according to the present invention shown in FIG.
That is, a field effect transistorM1 and M2Source is a series negative resistance element circuitG1 and G2At one endRespectivelyInstead of being connected, it is connected to another constant voltage source terminal E1 'corresponding to the constant voltage source terminal E1.
[0060]
The output voltages of the voltage output circuits U1 and U2 are supplied to the differential circuit F via the level shift circuits SH1 and SH2.
In this case, the level shift circuits SH1 and SH2 may have various configurations known per se.
For example, a field effect transistor Q11, diodes d11 and d12, and a field effect transistor Q12 are connected in series in this order between a level shift circuit SH1 and voltage sources ES1 and ES1 ', and the gate of the field effect transistor Q11 is connected to a voltage output circuit. U1 is connected to the output terminal OUT1, the gate of the field effect transistor Q12 is connected to the control voltage source terminal ECN, and the connection point between the diode d11 and the field effect transistor Q12 is connected to the gate of the field effect transistor Q1 of the differential circuit F. The configuration may be as follows.
[0061]
Similarly to the level shift circuit SH1, the level shift circuit SH2 includes a field effect transistor Q21, diodes d21 and d22, and a field effect transistor Q22 connected in series between the voltage sources ES2 and ES2 'in that order. The gate of the transistor Q21 is connected to the output terminal OUT2 of the voltage output circuit U2, the gate of the field effect transistor Q22 is connected to the control voltage source terminal ECN, and the connection point between the diode d21 and the field effect transistor Q22 is connected to the differential circuit F. It may be configured to be connected to the gate of the field effect transistor Q2.
[0062]
More than,First invention of the present applicationOf the voltage comparison circuit2It is a configuration of the embodiment.
Having such a configurationFirst invention of the present applicationVoltage comparison circuit2nd Embodiment ofAccording toFIG.Shown inFirst invention of the present applicationHas the same configuration as that of the voltage comparison circuit according to the first embodiment.
[0063]
For this reason, detailed description is omitted,FIG.The same operation and effect as those of the voltage comparison circuit according to the present invention shown in FIG.
In this case, however, the sum of the currents flowing from the connection point of the negative resistance element circuits B1 and B2 to the constant voltage source terminals E1 and E1 'is shown in FIG.First invention of the present applicationCorresponds to the current flowing from the midpoint of connection between the negative resistance element circuits B1 and B2 to the constant voltage source terminal E1.
[0064]
FIG. 1 shows the sum of the currents flowing from the connection point P2 between the negative resistance element circuits B3 and B4 to the constant voltage source terminals E1 and E1 '.First invention of the present applicationCorresponds to the current flowing from the midpoint of connection between the negative resistance element circuits B3 and B4 to the constant voltage source terminal E1.
[0065]
Further, the output voltages obtained at the output terminals OUT1 and OUT2 can be supplied to the differential circuit F in a level-shifted manner so that the differential operation is effectively performed.
[0066]
Embodiment of the first invention of the present application3]
next,FIG.WithFirst invention of the present applicationOf the voltage comparison circuit3An embodiment will be described.
FIG.In the figure, the same reference numerals are given to parts corresponding to those in FIG. 1 and detailed description is omitted.
[0067]
FIG.Shown inFirst invention of the present application, The negative resistance element circuits B1, B2, B3, and B4 are connected in series instead of having one two-terminal negative resistance element D1, D2, D3, and D4, respectively. Except for having two two-terminal negative resistance elements D11 and D12, D21 and D22, D31 and D32, and D41 and D42, the configuration is the same as that of the voltage comparison circuit according to the present invention shown in FIG. Have.
[0068]
However, in this case, the two-terminal negative resistance elements D11 and D12 have current-voltage characteristics having peak current values at different voltage positions, so that the negative resistance element circuit B1 has two peak currents. It has a current-voltage characteristic having a value.
Similarly, each of the two-terminal negative resistance elements D21 and D22, D31 and D32, and D41 and D42 has a current-voltage characteristic having a peak current value at a different voltage position. Each of the circuits B2, B3, and B4 also has a current-voltage characteristic having two peak current values.
[0069]
More than,First invention of the present applicationOf the voltage comparison circuit3It is a configuration of the embodiment.
Having such a configurationFirst invention of the present applicationHas the same configuration as that of the voltage comparison circuit according to the present invention shown in FIG. 1 except for the matters described above.
[0070]
For this reason, although a detailed description is omitted, it is clear that a ternary output voltage can be obtained as a voltage comparison output by taking a voltage value without a spike at the output terminal OUT.
[0071]
[Embodiment of the second invention of the present application]
Next, an embodiment of the voltage comparison circuit according to the second invention of the present application will be described.
The embodiment of the voltage comparison circuit according to the second invention of the present application is similar to the third embodiment of the first invention of the present application shown in FIG. 4 except that the field effect transistor M2 included in the power output circuit U2 is omitted. It has a configuration similar to that of the embodiment.
The above is the embodiment of the voltage comparison circuit according to the second invention of the present application.
According to the embodiment of the voltage comparison circuit according to the second invention of the present application having such a configuration, the same as the third embodiment according to the first invention of the present application shown in FIG. Although the detailed description is omitted, it is apparent that the ternary output voltage can be obtained as a voltage comparison output by taking a voltage value without a spike at the output terminal OUT.
[0072]
In the above, only a few embodiments of the present invention have been shown, and various modifications can be made without departing from the spirit of the present invention.
For example, FIG.Shown inFirst invention of the present applicationIn the voltage comparison circuit byFIG.Shown inFirst invention of the present applicationAccording to the configuration of the voltage comparison circuit described above, the sources of the field effect transistors M and M2 are connected to a constant voltage source terminal different from the constant voltage source terminal E1,FIG.Shown inFirst invention of the present applicationThe same operation and effect as described in the voltage comparison circuit described above can be obtained.
[0073]
Also,FIG.Shown inFirst invention of the present application, The sources of the field effect transistors M and M2 may be connected to the constant voltage source terminal E1 according to the voltage comparison circuit according to the present invention shown in FIG.
[0074]
Further, FIG.3 and 4Shown inFirst invention of the present application, Each of the negative resistance element circuits B1 to B4 has a plurality of n two-terminal negative resistance elements connected in series, and outputs an (n + 1) -valued output voltage. It is also possible to output to the output terminal OUT as a voltage comparison output.
[0075]
Also, the second invention of the present applicationIn the voltage comparison circuit according to the above, one end of the series negative resistance element circuits U1 and U2 is connected to a constant voltage source terminal from which constant voltages different from each other are obtained instead of being connected to a common constant voltage source terminal E1. ,Second invention of the present applicationThe same operation and effect as described in the voltage comparison circuit described above can be obtained.
[0076]
Further, the second invention of the present applicationIn the voltage comparison circuit byFIG.Shown inFirst invention of the present applicationThe source of the field effect transistor M is connected to the constant voltage source terminal E1 'Second invention of the present applicationThe same operation and effect as in the case of the voltage comparison circuit byFIG.Shown inFirst invention of the present applicationCan be obtained with the features described in the voltage comparison circuit described above.
[0077]
Also, the second invention of the present application, Each of the negative resistance element circuits B1 to B4 has a plurality of n two-terminal negative resistance elements connected in series, and outputs an (n + 1) -valued output voltage to an output terminal. OUT may be output as a voltage comparison output.
[0078]
Further, in the above description, the case where the field effect transistor is connected to the negative resistance element circuit side of the series negative resistance element circuit opposite to the clock signal voltage source terminal Vc side has been described. The same operation and effect can also be obtained by connecting to the clock signal voltage source terminal Vc side of the series negative resistance element circuit according to the above.
[0079]
【The invention's effect】
According to the voltage comparison circuit of the present invention, a voltage comparison output of the input signal voltage compared with the threshold voltage can be easily obtained without spikes.
[Brief description of the drawings]
FIG.First invention of the present application1 is a connection diagram showing a first embodiment of a voltage comparison circuit according to the present invention.
FIG. 2 shows in FIG.First invention of the present applicationFIG. 6 is a voltage waveform diagram for explaining a voltage comparison circuit according to the first embodiment.
FIG. 3First invention of the present applicationFIG. 5 is a connection diagram showing a second embodiment of the voltage comparison circuit according to the present invention.
[Figure]4]First invention of the present applicationOf the voltage comparison circuit3It is a connection diagram showing an embodiment.
[Figure]5FIG. 10 is a connection diagram showing a conventional voltage comparison circuit.
[Figure]6FIG. 11 is a diagram showing current-voltage characteristics of a two-terminal negative resistance element for describing a voltage comparison circuit according to the present invention and a conventional voltage comparison circuit.
[Figure]7FIG. 4 is a diagram showing current-voltage characteristics of a two-terminal negative resistance element, a negative resistance element circuit, and a composite circuit for describing a voltage comparison circuit according to the present invention and a conventional voltage comparison circuit.
[Figure]8FIG. 3 is a diagram showing current-voltage characteristics of a two-terminal negative resistance element and a negative resistance element circuit for describing a voltage comparison circuit according to the present invention and a conventional voltage comparison circuit.
[Figure]9FIG. 9 is a diagram showing current-voltage characteristics of a voltage comparison circuit according to the present invention and a composite circuit for explaining a conventional voltage comparison circuit.
[Figure]10FIG. 11 is a diagram showing a current-voltage characteristic curve for explaining the operation of the voltage comparison circuit according to the present invention and the conventional voltage comparison circuit.
[Figure]11FIG. 9 is a voltage waveform diagram for explaining the operation of the voltage comparison circuit according to the present invention and the conventional voltage comparison circuit.
[Figure]12FIG. 11 is a diagram showing a current-voltage characteristic curve for explaining the operation of the voltage comparison circuit according to the present invention and the conventional voltage comparison circuit.
[Figure]ThirteenFIG. 9 is a voltage waveform diagram for explaining the operation of the voltage comparison circuit according to the present invention and the conventional voltage comparison circuit.
[Figure]14FIG. 11 is a voltage waveform chart for explaining the operation of a conventional voltage comparison circuit.
[Explanation of symbols]
B1 to B4 ... Negative resistance element circuit
C ……………… Composite circuit
D1 to D4, D11, D12, D21, D22, D31, D32, D41,
D42 ...... Two-terminal negative resistance element
E1, E2 ... Constant voltage source end
Ec: Clock signal voltage source terminal
ECN: Control voltage source end
EF …………… Voltage source end
F ………………… Differential circuit
G, G2 ..... series negative resistance element circuit
H ……………… Constant current circuit
M ……………… Field effect transistor
IN ............ Signal input terminal
OUT, OUT1, OUT2 ...... Output terminal
Q1, Q2, Q11, Q12, Q21, Q22 ... field-effect transistor
R1, R2 ... Load resistance
SH1, SH2 ... level shift circuit
U1, U2 ... voltage output circuit

Claims (5)

A first negative resistance element circuit having one two-terminal negative resistance element or a plurality of n two-terminal negative resistance elements connected in series, and the first negative resistance element circuit having a two-terminal negative resistance Negative resistive element having one two-terminal negative resistive element or a plurality of n two-terminal negative resistive elements connected in series depending on whether it has one or a plurality of n negative resistive elements A first series negative resistance element circuit in which a circuit is connected in series; and a drain connected to a connection midpoint between the first and second negative resistance element circuits of the first series negative resistance element circuit. A first field-effect transistor having a source connected to one end of the first series negative resistance element circuit or a power supply terminal to which a constant voltage is applied, and A clock signal voltage that alternates between "0" and "1" in binary display between both ends is And an input signal voltage is applied to the gate of the first field effect transistor, and the first and second negative resistance element circuits of the first series negative resistance element circuit A first voltage output circuit configured to set a connection middle point of the first output terminal as a first output terminal from which a first output voltage is output;
One two-terminal negative resistance element or a plurality of n connected in series depending on whether the first and second negative resistance element circuits have one or two or more two-terminal negative resistance elements. A third negative resistance element circuit having the two-terminal negative resistance element, and one third resistance element circuit depending on whether the third negative resistance element circuit has one or a plurality of n two-terminal negative resistance elements The second series negative resistance element circuit in which the two-terminal negative resistance element circuit described above or the fourth negative resistance element circuit having a plurality of n two-terminal negative resistance elements connected in series is connected in series And a drain connected to a connection midpoint between the third and fourth negative resistance element circuits of the second series negative resistance element circuit, and a source connected to one end or a constant of the second series negative resistance element circuit. A second field effect transistor connected to a power supply terminal to which a voltage is applied. The clock signal voltage is applied between both ends of the series negative resistance element circuit, the input signal voltage is applied to the gate of the second field effect transistor, and the second series negative resistance is applied. A second voltage output circuit configured such that a connection point between the third and fourth negative resistance element circuits of the negative resistance element circuit is a second output terminal from which a second output voltage is output;
Inputting a first output voltage output from a first output terminal of the first voltage output circuit and a second output voltage output from a second output terminal of the second voltage output circuit; A differential circuit configured to output a difference voltage between the two,
A voltage comparison circuit configured to output a difference voltage output from the differential circuit as a voltage comparison output that is compared with a predetermined threshold voltage of the input signal voltage. 2. The voltage comparison circuit according to claim 1,
Two terminals of the first and second negative resistance element circuits of the first series negative resistance element circuit and the third and fourth negative resistance element circuits of the second series negative resistance element circuit Since the number of the negative resistance elements is n, the first output voltage output from the first voltage output circuit and the second output voltage output from the second voltage output circuit become ( (n + 1) value. 2. The voltage comparison circuit according to claim 1,
Two terminals of the first and second negative resistance element circuits of the first series negative resistance element circuit and the third and fourth negative resistance element circuits of the second series negative resistance element circuit Since the number of the negative resistance elements is one, the first output voltage output from the first voltage output circuit and the second output voltage output from the second voltage output circuit are binary. A voltage comparison circuit. 2. The voltage comparison circuit according to claim 1,
The two-terminal negative terminals of the first and second negative resistance element circuits of the first series negative resistance element circuit and the third and fourth negative resistance element circuits of the second series negative resistance element circuit It is assumed that there are a plurality of n resistive elements. When n is 2, the first output voltage output from the first voltage output circuit and the second output voltage are output from the second voltage output circuit. A voltage comparison circuit, wherein the second output voltage has three values. A first negative resistance element circuit having a plurality of n two-terminal negative resistance elements connected in series, and a second negative resistance having a plurality of n two-terminal negative resistance elements connected in series A first series negative resistance element circuit in which the element circuits are connected in series, and a drain connected to a connection midpoint between the first and second negative resistance element circuits of the first series negative resistance element circuit. And a field effect transistor having a source connected to one end of the first series negative resistance element circuit or a power supply terminal to which a constant voltage is applied, and both ends of the first series negative resistance element circuit. A clock signal voltage that alternates between "0" and "1" in binary display is applied between the input and the input signal voltage is applied to the gate of the field effect transistor. And second negative of the series negative resistance element circuit of FIG. A first voltage output circuit adapted to the first output terminal a first output voltage taking the (n + 1) values the connection midpoint is the output of the anti-element circuit,
A third negative resistance element circuit having a plurality of n two-terminal negative resistance elements connected in series, and a fourth negative resistance having a plurality of n two-terminal negative resistance elements connected in series A second series negative resistance element circuit connected in series with the element circuit, wherein the clock signal voltage is applied across both ends of the second series negative resistance element circuit; The midpoint of connection between the third and fourth negative resistance element circuits of the second series negative resistance element circuit is set as a second output terminal from which a second output voltage having a value (n + 1) is output. A second voltage output circuit made,
Inputting a first output voltage output from a first output terminal of the first voltage output circuit and a second output voltage output from a second output terminal of the second voltage output circuit; A differential circuit configured to output a difference voltage between the two,
A voltage comparison circuit configured to output a difference voltage output from the differential circuit as a voltage comparison output that is compared with a predetermined threshold voltage of the input signal voltage.

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