JP3546326B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor memory equipment, and more particularly to a technology effective respect mask ROM.
[0002]
[Prior art]
In recent years, along with the high integration of memory cell arrays, MOS transistors constituting the memory cells have been greatly reduced, and the necessity of MOS transistors having a small element area and a large driving capability has been increasing. In particular, in a memory cell such as a mask ROM, one transistor corresponds to one cell, and the on / off state of this transistor corresponds to information “1” and “0”. Is higher.
[0003]
Conventionally, in this type of memory cell array, a flat cell (or planar type) structure is used, but element isolation is formed by PN junction isolation by implantation without using a field oxide film.
[0004]
As a prior art, FIG. 5 shows a semiconductor memory device described in Japanese Patent Application Laid-Open No. 61-288644. 6A is a plan view, FIG. 6B is a cross-sectional view taken along line AA of FIG. 6A, and FIG. 6C is a cross-sectional view taken along line BB of FIG. 6A.
[0005]
5, a plurality of source / drain regions 25 are formed in parallel on the surface of a silicon substrate 21, and a gate electrode 27 is formed on these source / drain regions 25 via a gate insulating film 26. Are formed in parallel in a direction perpendicular to the direction. Further, by implanting ions of the conductivity type opposite to that of the source / drain region 25, the substrate concentration in the region without the source / drain region 25 and the region without the gate electrode 27 is increased to form the element isolation region 30.
[0006]
Further, a method of manufacturing the semiconductor memory device will be described with reference to FIGS.
[0007]
Here, FIG. 7 is a manufacturing process diagram in the AA cross section of FIG. 6A, FIG. 8 is a first half manufacturing process diagram in the BB cross section of FIG. 6A, and FIG. It is a manufacturing process figure of the latter half in the BB cross section of (a).
[0008]
First, as shown in FIG. 7A, after an insulating film 22 is formed on a P-type silicon substrate 21, a plurality of photoresist films 23 are formed in a strip pattern by a photolithography technique. Is used as a mask, N-type impurities are ion-implanted to form source / drain regions 25 of the MOS transistor. Note that reference numeral 24 indicates the implanted impurities.
[0009]
Next, as shown in FIGS. 7B and 8A, after removing the photoresist film 23 and the insulation 22, thermal oxidation is performed to form a gate oxide film 26. Then, a gate electrode material is deposited on the gate oxide film 26, and an N-type impurity such as phosphorus (P) is introduced by thermal diffusion or implantation. Thereafter, as shown in FIG. 8B, a plurality of photoresist films 28 are formed by photolithography in a direction orthogonal to the source / drain regions 25, and then anisotropically using the photoresist film 28 as a mask. The gate electrode 27 on the gate oxide film 36 is formed by etching (FIGS. 7C and 8C).
[0010]
Next, the photoresist film 28 is removed, and an impurity of the same conductivity type as that of the substrate is ion-implanted for element isolation, as shown in FIGS. 7D and 9A. Note that reference numeral 29 indicates the implanted impurities. Then, as shown in FIG. 9B, an interlayer insulating film 31 is formed, a resist pattern 32 is formed by lithography in order to store programmed ROM data, and a desired cell transistor channel portion is formed from above the gate electrode. Implant boron ions. Thereafter, heat treatment is performed to activate boron (FIG. 9C). Note that reference numeral 33 denotes the implanted impurities.
[0011]
[Problems to be solved by the invention]
The method for manufacturing the semiconductor device shown in FIGS. 5 to 7 has the following problems.
[0012]
That is, since the field oxide film is not used for element isolation and the concentration on the substrate surface is increased by ion implantation, the source / drain junction breakdown voltage is reduced. However, if the concentration is reduced, the breakdown voltage between the source and the drain decreases, and the leak current between the source and the drain increases. Therefore, in the PN junction isolation by ion implantation, the element isolation width is not reduced, and the memory cell cannot be miniaturized.
[0013]
Further, the ion implantation for element isolation increases the source / drain junction capacitance, causing a delay in the operation speed of the memory cell. The step of etching the gate electrode (FIGS. 7C and 8C) and the step of ion implantation for element isolation (FIGS. 7D and 9A) are performed by different apparatuses. As the number increases, work efficiency decreases.
[0014]
In order to store ROM data, ions are implanted from above the gate electrode. However, since the element isolation region is on the same plane as the channel portion of the cell, the ion-implanted impurities spread in the horizontal direction, and the adjacent cell transistor Will be affected. Since the concentration of the channel portion of the adjacent cell transistor is increased and the threshold voltage is increased, on / off reading cannot be performed. For this reason, it hinders the improvement of the cell integration.
[0015]
An object of the present invention is to provide a method of manufacturing a semiconductor memory device capable of improving element isolation characteristics, suppressing influence on adjacent cells, and achieving high integration without increasing the number of steps.
[0016]
[Means for Solving the Problems]
The method of manufacturing a semiconductor memory device of the present invention includes the steps of forming a diffusion region comprising a plurality of source / drain over the semiconductor substrate in parallel to each other, the oxide film on the diffusion region by accelerated oxidation on the semiconductor substrate Forming a thicker film than the oxide film in a region other than the diffusion region, and thereafter forming a conductive film to be a gate electrode, and etching the resist pattern so that a plurality of the conductive films are parallel to each other in a direction crossing the diffusion region. Using the mask as a mask, forming a gate electrode by patterning a conductive film, and using the resist pattern as an etching mask, in the region other than the diffusion region, removing the oxide film until the semiconductor substrate surface is exposed. Removing and etching using the oxide film on the resist pattern and the diffusion region as an etching mask Forming a groove in more said semiconductor substrate, and forming an interlayer insulating film on the semiconductor substrate, it is characterized in that a step of burying the interlayer insulating film in the groove.
[0018]
Further , according to the method of manufacturing a semiconductor memory device of the present invention, a plurality of diffusion regions serving as a source / drain are formed on a semiconductor substrate in parallel with each other, and an oxide film on the diffusion region is formed on the semiconductor substrate by accelerated oxidation. Forming a film thicker than the oxide film in the region other than the diffusion region, and then sequentially forming a conductive film and an insulating film to be a gate electrode, so that a plurality of the conductive films and the insulating film are parallel to each other in a direction crossing the diffusion region. Patterning the insulating film using a resist pattern as an etching mask; and removing the resist pattern, and then patterning the conductive film using the patterned insulating film as an etching mask to form a gate electrode. Forming and using the patterned insulating film as an etching mask, in an area other than the diffusion area. Removing the oxide film until the surface of the semiconductor substrate is exposed, and forming a groove in the semiconductor substrate by etching using the oxide film on the resist pattern and the diffusion region as an etching mask. Forming an interlayer insulating film on the semiconductor substrate, and burying the interlayer insulating film in the groove.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a method for manufacturing a ferroelectric capacitor of the present invention will be described in detail based on embodiments.
[0020]
FIG. 1 is a perspective sectional view of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 (a) is a plan view, FIG. 2 (b) is a sectional view taken along line AA of FIG. 2 (a), and FIG. 3) is a sectional view taken along line BB of FIG.
[0021]
In FIG. 2 , a main part of the semiconductor memory device has a plurality of mutually parallel band-shaped N-type diffusion layers 5 serving as source / drain regions formed on a P-type silicon substrate 1. A plurality of gate electrodes 7 are formed on silicon substrate 1 with gate oxide film 6 interposed therebetween in a direction orthogonal to diffusion region 5. On the N-type diffusion layer 5, a gate oxide film 9 (see FIG. 3D) which is thickened by accelerated oxidation is formed. A groove 10 is formed by digging the silicon substrate 1 in a region other than the gate electrode 7 and the diffusion region 5. Thereafter, as shown in FIG. 5 , the trench 10 is buried by the interlayer insulating film 11 to become an element isolation region.
[0022]
The accelerated oxidation is a phenomenon in which, in a region where an oxide film is formed, a predetermined region is heavily doped on a semiconductor substrate, and an oxide film becomes thicker than other regions. The general theory of accelerated oxidation will be briefly described below.
[0023]
Assuming that the intended thickness of the oxide film is Tox (t),
Tox ² (t) + ATox (t) = B (t + to) (1)
Equation (1) holds. In this equation, A and B are rate constants, and A = Po ₂ × Kp / Kl, B = Po ₂ × Kp (Po ₂ is a normalized oxidation partial pressure, Kl is a linear law oxidation coefficient, and Kp is a square law. And to is the correction time. In the formula (1), at low concentrations, Kp and Kl depend only on the oxidizing atmosphere and the crystal direction of the substrate, while at high concentrations, Kp and Kl increase. Therefore, an oxide film having a larger thickness than an oxide film formed under the same conditions can be formed without accelerated oxidation.
[0024]
Next, a method of manufacturing a semiconductor memory device according to the present invention will be described with reference to FIGS. Here, FIG. 3 is a manufacturing process diagram in the AA cross section of FIG. 2A, FIG. 4 is a first half manufacturing process diagram in the BB cross section of FIG. 2A, and FIG. FIG. 3A is a manufacturing process diagram of the latter half of the BB cross section. First, as shown in FIG. 3A, a silicon oxide film as an insulating film 2 is formed on a P-type silicon substrate 1 in a high-temperature oxygen atmosphere by 200 mm. After forming the photoresist film 3 by photolithography, a plurality of photoresist films 3 are formed in a band-like pattern having a width of, for example, 0.15 to 0.6 μm and an interval of 0.15 to 0.6 μm. Using the pattern as a mask, an N-type impurity such as arsenic (As) is ion-implanted under the conditions of an implantation energy of 10 to 80 keV and a dose of about 3 × 10 ¹⁵ cm ⁻² , and the source / drain region 5 of the MOS transistor Form. Note that reference numeral 4 indicates the implanted impurities.
[0025]
Next, as shown in FIGS. 3B and 4A, after the photoresist film and the insulating film 2 are removed, thermal oxidation is performed in a high-temperature oxygen atmosphere to form a gate oxide film other than the source / drain regions. The thickness is increased by the accelerated oxidation as compared with the thickness. For example, oxidation is performed at 800 ° C. for 63 minutes at an O ₂ gas flow rate of 10 liters / minute and an HCl gas flow rate of 0.4 liters / minute, and the film thickness D1 outside the source / drain regions in FIG. When the oxide film is formed, an oxide film having a thickness D2 of 300 ° is formed on the source / drain region 5 into which impurities are implanted at a high concentration.
[0026]
Then, for example, a polysilicon film is deposited on the gate oxide film 6 as the gate electrode 7 by, for example, about 1000 to 2000 ° by a CVD method, and an N-type impurity such as phosphorus (P) is introduced by thermal diffusion or implantation. After that, in order to reduce the resistance of the gate electrode, a polycide layer may be formed by depositing tungsten silicide at about 1000 to 2000 °.
[0027]
Thereafter, as shown in FIG. 4B, a plurality of photoresist films are formed in a band-like pattern having a width of, for example, 0.15 to 0.6 μm and an interval of 0.15 to 0.6 μm by a photolithography technique. As a mask, the gate electrode 7 on the gate oxide film 6 is etched by anisotropic etching (FIG. 3C). The gate electrode is etched using a mixed gas of HBr and O ₂ or a mixed gas of HBr, Cl ₂ and O ₂ .
[0028]
Next, etching is performed until the gate oxide film in the region other than the source / drain is exhausted, that is, the thickness D1 is etched. Note that the gate oxide film is etched using CF4 gas. As shown in FIG. 3D, an oxide film 9 having a thickness of D2-D1 remains in the source / drain region 5. According to the above-described example, the oxide film 9 having a thickness of about 200 ° is formed on the source / drain region 5, and the silicon substrate 1 is exposed in a region other than the gate electrode 7.
[0029]
Next, as shown in FIGS. 3E and 4C, the silicon substrate 1 is dug by anisotropic etching using, for example, an HBr / O ₂ -based gas having a high selectivity to the oxide film. A groove 10 is formed. The depth of the groove 10 is 1000 to 3000 °, and is desirably deeper than the source / drain junction depth. The groove 10 in the region other than the source / drain regions 5 and regions not gate electrode 7, namely the isolation region only in the groove 10 is formed. Thereafter, the photoresist is removed, and an interlayer insulating film 11 is formed as shown in FIG. Note that the etching for forming the groove from the etching of the gate electrode can be continuously performed in one sequence in the same apparatus, and the element isolation region can be formed in a self-aligned manner simultaneously with the etching for forming the gate electrode.
[0030]
Next, as shown in FIG. 5B, a resist pattern is formed by lithography in order to store the programmed ROM data, and ions are implanted into a desired cell transistor channel from above the gate electrode. This ion implantation is performed with boron at an implantation energy of, for example, 180 keV and a dose of about 5 × 10 ^{13 to} 5 × 10 ¹⁴ cm ⁻² .
[0031]
Next, heat treatment is performed to activate boron (FIG. 5C). The threshold voltage of a transistor into which boron is implanted is as high as 4 to 7 V, and the threshold voltage of a transistor into which boron is not implanted is about 0.8 V. Therefore, data is stored in correspondence with the off / on state. .
[0032]
In the above description, the silicon substrate in the element isolation region is etched using the photoresist as a mask. However, after depositing a gate electrode material, an oxide film is formed, for example, at 1500 °, and the photoresist is formed thereon. After coating and patterning into a predetermined shape, the oxide film is etched using the resist pattern as a mask, and after removing the resist pattern, a gate electrode is formed by etching using the oxide film as a mask. The silicon substrate may be etched using the oxide film on the diffusion layer as an etching mask. Etching using an oxide film as a mask is more suitable for fine processing than using a resist pattern as an etching mask. In this embodiment, the formation of the Nch transistor cell on the P-type silicon substrate has been described. However, the same effect can be obtained by forming the Pch transistor on the N-type silicon substrate.
[0033]
【The invention's effect】
As described above in detail, by making the thickness of the oxide film on the diffusion region larger than the thickness of the oxide on the element isolation by the accelerated oxidation than the thickness of the gate insulating film, the thickness difference is utilized. By selectively etching the semiconductor substrate only in the element isolation portion by etching at the time of forming the gate electrode, the source / drain junction leakage is reduced and the withstand voltage is increased without increasing the number of steps, so that the element isolation width is increased. It can be narrowed, and the degree of integration of the cell is improved.
[0034]
Further, since the junction capacitance is reduced, the speed of the memory cell can be increased. From the etching of the gate electrode to the etching for forming the groove, it can be performed in a continuous sequence in the same apparatus, so that an increase in the number of steps can be suppressed and work efficiency can be improved.
[0035]
In order to store ROM data, ions are implanted from above the gate electrode. However, since the silicon substrate is etched between the channels of the adjacent gate electrodes, the impurities implanted and activated by the ion implantation diffuse in the lateral direction. Therefore, the influence on adjacent cells can be eliminated, and the read margin can be improved, and the density of cells can be increased by reducing the gate electrode space.
[Brief description of the drawings]
FIG. 1 is a perspective sectional view of a semiconductor memory device according to an embodiment of the present invention.
2A is a plan view of a semiconductor memory device according to an embodiment of the present invention, FIG. 2B is a cross-sectional view taken along line AA of FIG. 2A, and FIG. 2C is a cross-sectional view taken along line BB of FIG. It is sectional drawing.
FIG. 3 is a manufacturing process diagram in the AA cross section of FIG. 2 (a).
FIG. 4 is a first half of a manufacturing process diagram in a BB cross section of FIG.
FIG. 5 is a manufacturing process diagram of the latter half in the BB section of FIG. 2 (a).
6A is a plan view of a conventional semiconductor memory device, FIG. 6B is a sectional view taken along line AA of FIG. 6A, and FIG. 6C is a sectional view taken along line BB of FIG. .
FIG. 7 is a manufacturing process diagram in an AA section of FIG. 6 (a).
FIG. 8 is a first half of a manufacturing process drawing in a BB cross section of FIG. 6 (a).
FIG. 9 is a manufacturing process diagram of the latter half in the BB section of FIG. 6 (a).
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 Oxide film 3 Photoresist 4 Injected impurity 5 Source / drain region 6 Gate oxide film 7 Gate electrode 8 Photoresist 9 Gate oxide film on source / drain region 10 Groove 11 Interlayer insulating film 12 Photoresist 13 Impurity implanted 14 Activated impurity region

Claims (2)

A step of parallel to each other a diffusion region comprising a plurality of source / drain in the semiconductor substrate,
Forming an oxide film on the diffusion region by accelerated oxidation on the semiconductor substrate to be thicker than an oxide film in a region other than the diffusion region, and thereafter forming a conductive film serving as a gate electrode;
Forming a gate electrode by patterning a conductive film using a resist pattern as an etching mask so that a plurality of the gate electrodes are parallel to each other in a direction intersecting with the diffusion region ;
Using the resist pattern as an etching mask, in a region other than the diffusion region, until the semiconductor substrate surface is exposed, removing the oxide film;
Using the oxide film on the resist pattern and the diffusion region as an etching mask, forming a groove in the semiconductor substrate by etching;
Wherein with an interlayer insulating film on a semiconductor substrate, and having a burying the interlayer insulating film in the groove, the method of manufacturing a semiconductor memory device. Forming a plurality of diffusion regions serving as a source / drain on a semiconductor substrate in parallel with each other;
Forming an oxide film on the diffusion region by the accelerated oxidation on the semiconductor substrate to be thicker than an oxide film in a region other than the diffusion region, and then sequentially forming a conductive film and an insulating film to be a gate electrode;
Patterning the insulating film using a resist pattern as an etching mask so that a plurality of the insulating films are parallel to each other in a direction crossing the diffusion region, and after removing the resist pattern, removing the patterned insulating film. Forming a gate electrode by patterning the conductive film using the etching mask ;
Using the patterned insulating film as an etching mask, in a region other than the diffusion region, until the semiconductor substrate surface is exposed, removing the oxide film;
The resist pattern and using the oxide film on the diffusion region as an etch mask to form a groove in the upper Symbol semiconductor substrate by etching,
Forming an interlayer insulating film on the semiconductor substrate, and burying the interlayer insulating film in the trench.

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