JP3547938B2 - Bias control circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a bias control circuit for controlling the timing of a circuit using an FET having a restriction on the timing of supplying a bias voltage.
[0002]
[Prior art]
In recent years, with the spread of mobile communication devices, the use of high frequency devices has been increasing. For example, in transmission power amplifiers of mobile phones, the use of high-frequency devices called GaAs FETs has become mainstream. In this FET, there is a restriction on the timing of supplying a bias voltage to the three terminals of the gate, drain and source. If this restriction is not respected, an excessive current flows inside the FET, causing performance degradation or destruction of the FET.
[0003]
Therefore, in a bias control circuit used in a conventional mobile phone, the timing of the voltage supplied to the FET is managed by the following method.
FIG. 6 shows a configuration diagram of a bias control circuit according to the first conventional technique.
In the figure, a voltage of +3.6 V is supplied from a battery terminal VBATT to a step-up DC-DC converter 601 and an inverting DC-DC converter 603.
[0004]
The boost DC-DC converter 601 boosts the power supply voltage and outputs a voltage of +5 V, and the inverting DC-DC converter 603 inverts the power supply voltage and outputs a voltage of -3.6 V to the gate.
Switch 602 conducts the output voltage from step-up DC-DC converter 601 to the drain according to the PABAT signal input from control unit 604 via inverter 606.
[0005]
The transmission power amplifier 605 is, for example, a GaAs FET, and has a gate having a voltage of -3.6 V from the inverting DC-DC converter 603 and a drain having a voltage of +5 V from the step-up DC-DC converter 601 via the switch 602. Is supplied.
In the FET of the transmission power amplifier 605, the timing for supplying a voltage to the gate and the drain must be as follows.
(1) When power is supplied, a negative voltage is supplied to the gate, and after the gate voltage reaches a predetermined voltage, a positive voltage is supplied to the drain.
(2) When the power supply is stopped, the voltage supply to the drain is stopped, and then the voltage supply to the gate is stopped.
[0006]
If the voltage supply / supply stop timing is reversed, unlike the above (1) and (2), the drain current will flow excessively in the FET, and as a result, the battery will be consumed and the performance of the FET will be deteriorated or destroyed. .
The control unit 604 is realized by a microcomputer, and outputs a GATE ON signal and a PABAT signal from an output port. Specifically, the operation / non-operation of the inverting DC-DC converter 603 is controlled by the GATE ON signal, and the operation / non-operation of the step-up DC-DC converter 601 and the conduction of the switch 602 are controlled by the PABAT signal.
[0007]
FIG. 7 shows a time chart of the bias control circuit of FIG.
The “L” period of the PABAT signal ((B)) of the control unit 604 is shorter than the “L” period of the GATE ON signal ((A)) of the control unit 604. The control unit 604 outputs a GATE ON signal and a PABAT signal at the timings shown in FIGS. 3A and 3B so as to satisfy the restrictions (1) and (2).
When the GATE ON signal is input to the inversion type DC-DC converter 603, the inversion type DC-DC converter 603 inverts the power supply voltage of + 3.6V to -3.6V while the GATE ON signal is "L". Then, the signal shown in (E) is output.
[0008]
When the PABAT signal is input to the boost DC-DC converter 601, the boost DC-DC converter 601 boosts the power supply voltage of +3.6 V to +5 V while the PABAT signal is “L”, and (D) Is output. The PABAT signal is also input to the switch 602 via the inverter 606, and during the period when the PABAT signal is “L”, the switch 602 conducts the output voltage from the boost DC-DC converter 601 and is shown in FIG. Output a signal.
[0009]
As described above, in the first conventional technique, the voltage supply timing to the FET is controlled by the output timing of the GATE ON signal and the PABAT signal.
Next, FIG. 8 shows a bias control circuit according to a second conventional technique.
In FIG. 8, VBATT + 3.6 V, a control unit 604, a step-up DC-DC converter 601, an inverting DC-DC converter 603, a switch 602, and a transmission power amplifier 605 are the same as those in the first related art.
[0010]
6 is different from FIG. 6 in that the GATE ON signal is input to the boost DC-DC converter 601 instead of the PABAT signal. As a result, the output period of the step-up DC-DC converter 601 becomes longer, so that the determined +5 V voltage is supplied to the drain of the transmission power amplifier 605 while the switch 602 is conducting.
[0011]
FIG. 9 shows a time chart of the bias control circuit of FIG.
In the figure, the boost DC-DC converter 601 operates while the GATE ON signal ((A)) of the control unit 604 is "L", so that as shown in FIG. The output timing of the DC-DC converter 601 is different.
[0012]
[Problems to be solved by the invention]
The first and second prior art bias control circuits have the following problems.
That is, in the first prior art, as shown in the time chart of FIG. 10, the output timing of the GATE ON signal (A) and the output timing of the PABAT signal (B) are reversed due to a malfunction of the control unit 604. In this case, the rising and falling timings of the inverting DC-DC converter 603 ((E)) for supplying the bias voltage to the transmission power amplifier 605 and the switch 602 ((F)) are reversed, and the FET is deteriorated or destroyed. There was a problem. The malfunction occurs, for example, when the control unit 604 runs away due to noise or when the operation becomes unstable due to a decrease in battery voltage.
[0013]
Although the above is a problem that occurs when the control unit 604 malfunctions, there is also a problem when the control unit 604 operates normally.
One is that the step-up DC-DC converter 601 and the inverting DC-DC converter 603 consume useless current in the sections shown in FIGS. 7A and 7B. The reason for this is that in the section (a), an unnecessary time difference is previously taken between the output timings of the two signals in order to prevent the above-mentioned reverse rotation, and in the section (b), This is because the PABAT signal is output earlier than the actual transmission signal period. The reason why the PABAT signal is output at an early point is that, at the start of the transmission signal period, in order to supply a fixed +5 V voltage, its rise time (necessary because there is a capacitor in the output stage of the step-up DC-DC converter 601). It is because it is expected).
[0014]
Another problem is that useless power is consumed in the transmission power amplifier 605 in the section shown in FIG. 7C. This is because the bias voltage is supplied from the boost DC-DC converter 601 via the switch 602 in the section (c).
Next, in the second prior art, as shown in the time chart of FIG. 11, the output period of the GATE ON signal ((A)) and the output period of the PABAT signal ((B)) were reversed due to a malfunction of the control unit 604. In this case, in the section (d), the rising and falling timings of the inverting DC-DC converter 603 ((E)) and the switch 602 ((F)) are reversed, and the timing of supplying power to the transmission power amplifier 605 is changed. Since it is reversed, there is a problem that deterioration or destruction of the FET is caused.
[0015]
In view of the above, it is an object of the present invention to provide a bias control circuit that eliminates the above-mentioned problems of the prior art, protects the FET from deterioration and destruction, and reduces power consumption.
[0016]
[Means for Solving the Problems]
To achieve the above object, a bias control circuit according to the present invention is a bias control circuit that controls supply of a first bias voltage supplied to a gate of a FET and a second bias voltage supplied to a source or a drain. 1, generating means for generating a first signal indicating a supply timing of a second bias voltage, a second signal, a first power supply means for outputting a first bias voltage to a gate when the first signal is valid, and a first signal Second power supply means for outputting a predetermined voltage when is effective, switch means provided between the output of the second power supply and the source or drain, and switch means when both the first signal and the second signal are effective And a control means for supplying a predetermined voltage as the second bias voltage to the source or the drain by conducting the current.
[0017]
Further, the first power supply unit may output a determination signal indicating that the output is determined, and the generation unit may generate the second signal based on the determination signal.
Further, the control means may take a logical product of the first signal and the second signal.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a configuration diagram of the bias control circuit according to the first embodiment.
The bias control circuit includes a step-up DC-DC converter 101, a switch 102, an inverting DC-DC converter 103, a control unit 104, a transmission power amplifier 105, and a NOR gate 106. The supply of the bias voltage to the transmission power amplifier (FET) at the last stage of the transmission unit is controlled.
[0019]
In FIG. 1, VBATT indicates a power supply voltage of +3.6 V supplied from the battery.
The boost DC-DC converter 101 boosts the power supply voltage of +3.6 V and outputs a voltage of +5 V under the control of the control unit 104.
Under the control of the control unit 104, the inversion type DC-DC converter 103 inverts the power supply voltage of + 3.6V and outputs a voltage of -3.6V.
[0020]
The control unit 104 is realized by a microcomputer, and outputs a GATE ON signal and a PABAT signal from an output port. Specifically, the operation / non-operation of the boost DC-DC converter 101 and the inverting DC-DC converter 103 is controlled by the GATE ON signal, and the same signal is output to the NOR gate 106. Further, it outputs a PABAT signal to NOR gate 106. The “L” period of the PABAT signal is shorter than the “L” period of the GATE ON signal, and the fall timing is closer to the start point of the transmission signal period as compared with the related art. Note that this transmission signal period is about 6.67 ms with a 1/3 duty of 20 ms TDMA time slot in a domestic portable telephone (PDC).
[0021]
The NOR gate 106 outputs “H” only when both the GATE ON signal and the PABAT signal are “L”.
The switch 102 conducts while the output of the NOR gate 106 is “H”, and thereby supplies the +5 V voltage of the output of the step-up DC-DC converter 101 to the drain of the transmission power amplifier 105.
[0022]
The transmission power amplifier 105 is an FET such as a GaAs FET. The gate of the transmission power amplifier 105 receives a voltage of −3.6 V from the inverting DC-DC converter 103 and the drain thereof receives a voltage of +5 V from the step-up DC-DC converter 101 via the switch 102. And supplied as a bias voltage.
The operation of the bias control circuit according to the present embodiment configured as described above will be described.
[0023]
FIG. 2 is a time chart when the control unit 104 of the bias control circuit of FIG. 1 operates normally.
The control unit 104 controls the GATE ON signal (PAA) at the timing of the GATE ON signal ((A)) and the PABAT signal ((B)) to satisfy (1) and (2) described in the related art. Output a signal.
[0024]
These two signals are input to the NOR gate 106, and the signal indicated by (C) is output.
On the other hand, when the GATE ON signal ((A)) is input to the boost DC-DC converter 101 and the inverting DC-DC converter 103, the boost DC-DC converter 101 boosts the power supply voltage of + 3.6V to + 5V. Then, the signal shown in (D) is output, and the inverting DC-DC converter 103 inverts the power supply voltage of +3.6 V to -3.6 V and outputs the signal shown in (E).
[0025]
While the signal shown in (C) is being input to the switch 102, the switch 102 conducts the output voltage from the step-up DC-DC converter 101 and outputs the signal shown in (F).
In FIG. 2, the output ((F)) of the switch 102 is the same as the time chart (FIG. 7) of the first conventional technique (FIG. 7), but the time of FIG. Therefore, power can be supplied to the transmission power amplifier 105 without waste. Further, waste of power consumption by the step-up DC-DC converter 101 and the inverting DC-DC converter 103 can be reduced. This is because the timing of supplying a voltage to the transmission power amplifier 105 is guaranteed by the NOR gate, so that the “L” period of the GATE ON output of the control unit 104 can be shortened to the minimum necessary.
[0026]
FIG. 3 is a time chart when the control unit 104 of the bias control circuit of FIG. 1 malfunctions.
This figure is different from FIG. 2 in that the output timings of the GATE ON signal ((A)) and the PABAT signal ((B)) are reversed.
As described above, even when the output timings of (A) and (B) are reversed, since the logical product is obtained by the NOR gate 106, the inverting DC-DC converter 103 ((E)) supplied to the gate and the drain The timing of the rise and fall of the switch 102 ((F)) is not reversed. For this reason, deterioration or destruction of the FET can be avoided, and thereafter, when the control unit 104 operates normally, this circuit can be used as usual.
[0027]
FIG. 4 is a configuration diagram of a bias control circuit according to the second embodiment.
In the figure, the bias control circuit includes a step-up DC-DC converter 101, a switch 102, an inverting DC-DC converter 103, a control unit 104, a transmission power amplifier 105, a NOR gate 106, a delay circuit 307 And an inverter 308, and controls supply of a bias voltage to a transmission power amplifier (FET) at the last stage of the transmission unit in the mobile phone, as in the first embodiment. VBATT indicates a power supply voltage of +3.6 V supplied from the battery. In the figure, VBATT, a step-up DC-DC converter 101, a switch 102, a control unit 104, and a transmission power amplifier 105 are the same as those in the first embodiment.
[0028]
Under the control of the GATE ON signal, the inversion type DC-DC converter 103 inverts the power supply voltage of +3.6 V and outputs a voltage of -3.6 V. In addition, when the voltage is inverted, the inversion type DC-DC converter 103 is between 95% and 100% of a predetermined output (-3.6V in the case of FIG. 3) (-3.42V to -3.6V). , And outputs a logic signal (hereinafter referred to as a REG signal) “H”. This means that a substantially stable voltage is supplied to the gate from the inverting DC-DC converter 103 during the period when the REG signal outputs “H”, so that the drain voltage can be supplied during this period.
[0029]
The inverter 308 inverts the REG signal of the inverting DC-DC converter 103.
The delay circuit 307 outputs a delay signal of the REG signal of the inverting DC-DC converter 103 to the NOR gate 106 via the inverter 308.
The NOR gate 106 outputs “H” only when both the GATE ON signal and the signal of the delay circuit 307 are “L”.
[0030]
FIG. 5 is a time chart of the bias control circuit of FIG.
In the figure, the REG signal of the inverting DC-DC converter 103 is a signal as shown in (B) when the inverting DC-DC converter 103 ((F)) is between -3.42 V and -3.6 V. Is output.
The delay circuit 307 delays the REG signal ((B)) of the inverting DC-DC converter 103 via the inverter 308 and outputs a signal as shown in (C) to the NOR gate 106. At this time, adjustment is made so that the fall of the output (C) of the delay circuit 307 coincides with the start of the transmission signal period.
[0031]
【The invention's effect】
A bias control circuit according to the present invention is a bias control circuit that controls supply of a first bias voltage supplied to a gate of a FET and a second bias voltage supplied to a source or a drain, and includes a first bias voltage and a second bias voltage. Generating means for generating first and second signals indicating supply timing, first power supply means for outputting a first bias voltage to the gate when the first signal is valid, and predetermined voltage when the first signal is valid A second power supply means for outputting a signal, a switch means provided between the output of the second power supply and a source or a drain, and conducting the switch means when both the first signal and the second signal are valid, thereby providing a predetermined And control means for supplying the second voltage as the second bias voltage to the drain, so that the generation timings of the first and second signals of the generation means are reversed due to malfunction. However, since the control means turns on the switch only when the first and second signals are both valid, the supply timing of the first bias voltage supplied to the gate and the second bias voltage supplied to the source or drain is reversed. Without this, there is an effect of preventing deterioration or destruction of the FET. Further, since the supply timing to the FET is guaranteed as described above, the time difference between the generation timings of the first and second signals of the generation unit can be minimized, and power consumption can be reduced. effective.
[0032]
The first power supply means outputs a determination signal indicating that the output is determined, and the generation means is configured to generate the second signal based on the determination signal, so that after the first bias voltage is supplied to the gate, It becomes more reliable that the switch means supplies the second bias voltage to the source or the drain, whereby the supply timing is protected and the FET is prevented from being deteriorated or destroyed. In addition, there is an effect that the number of signals generated by the generation unit becomes one, and control of the generation unit becomes easy.
[0033]
Further, the control means is configured to take a logical product of the first signal and the second signal, whereby the control means can be realized by using only one gate. is there.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a bias control circuit according to a first embodiment.
FIG. 2 shows a time chart when the control unit of the first embodiment operates normally.
FIG. 3 shows a time chart when the control unit of the first embodiment malfunctions.
FIG. 4 is a configuration diagram of a bias control circuit according to a second embodiment.
FIG. 5 is a time chart in the bias control circuit according to the second embodiment.
FIG. 6 is a configuration diagram of a bias control circuit in the first related art.
FIG. 7 is a time chart when the control unit operates normally in the first related art.
FIG. 8 is a configuration diagram of a bias control circuit according to a second conventional technique. FIG. 9 is a time chart when a control unit operates normally in the second conventional technique.
FIG. 10 is a time chart when the control unit malfunctions in the first prior art.
FIG. 11 shows a time chart when a control unit malfunctions in the second conventional technique.
[Explanation of symbols]
101 Boost DC-DC Converter 102 Switch 103 Inverting DC-DC Converter 104 Control Unit 105 Transmission Power Amplifier 106 NOR Gate 306 Inverter 307 Delay Circuit 601 Boost DC-DC Converter 602 Switch 603 Inverting DC-DC Converter 604 Control Unit 605 Transmission power amplifier 606 Inverter

Claims (3)

A bias control circuit for controlling supply of a first bias voltage supplied to a gate of the FET and a second bias voltage supplied to a source or a drain,
Generating means for generating first and second signals indicating supply timings of the first and second bias voltages;
First power supply means for outputting the first bias voltage to the gate only when the first signal is valid;
Second power supply means for boosting and outputting a power supply voltage only when the first signal is valid;
Switch means provided between an output of the second power supply means and a source or drain;
By controlling to output a bias voltage from the power supply unit for a period longer than the period of controlling the conduction of the switch unit, and conducting the switch unit when both the first signal and the second signal are valid, Control means for supplying a voltage output from a second power supply means to the source or drain as a second bias voltage. 2. The bias control circuit according to claim 1, wherein the first power supply unit outputs a determination signal indicating that the output is determined, and the generation unit generates the second signal based on the determination signal. 2. The bias control circuit according to claim 1, wherein said control means calculates a logical product of the first signal and the second signal.

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