JP3551850B2 - Noise cancellation circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a noise canceling circuit, and more particularly, to a noise canceling circuit that can cancel noise that can occur in an input signal having two values due to two different voltages.
[0002]
[Prior art]
Conventionally, as this kind of noise canceling circuit, a circuit provided with a whisker removal circuit for a signal output from a voltage detection circuit has been proposed (for example, Japanese Patent Application Laid-Open No. H10-111323). The whisker removal circuit includes a delay circuit for delaying an input signal, and a logic circuit for calculating a logical product of an output signal from the delay circuit and an input signal. The delay time of the delay circuit is adjusted so as to perform a delay corresponding to "whiskers" due to noise. As a result, it is possible to prevent the system from being reset due to noise due to a sudden load change at the time of power-on.
[0003]
[Problems to be solved by the invention]
However, in such a noise canceling circuit, the signal from the voltage detection circuit is ANDed with the signal from the delay circuit and output, so that the signal change is always delayed, and the signal from the voltage detection circuit is This delay can be problematic if a quick response is required. That is, even if an error is detected and a signal is output from the voltage detection circuit, the reset of the system is delayed, and an unexpected operation may be performed during this delay.
[0004]
It is an object of the present invention to perform noise cancellation and quick signal output as needed.
[0005]
[Means for Solving the Problems and Their Functions and Effects]
The noise cancellation circuit of the present invention employs the following means in order to achieve the above object.
[0006]
The noise canceling circuit of the present invention detects the power supply voltage applied to the system by a voltage detection circuit, and when there is an abnormality in the power supply voltage, the power supply voltage is output from the voltage detection circuit to reset the power supply to the system. that, a cancellation noise canceling circuit noise that may occur in the input signal with a value of two by two different voltages, the delay circuit for outputting the input signal by a predetermined delay time, by two different voltage 2 When the power supply voltage detected by the voltage detection circuit is normal based on the input of the switching signal having two values, the signal output from the delay circuit is compared with the input signal, and the values of both signals match. a state of outputting an output signal of the matched value instead of the value that has been output when, when the voltage detecting circuit detecting power supply voltage is abnormal, the And summarized in that and a signal output circuit for outputting a signal as it is switched between a state for outputting as an output signal a fill power signal.
[0007]
In the noise canceling circuit of the present invention, the signal output circuit outputs the input signal when the power supply voltage detected by the voltage detection circuit is normal based on the input of the switching signal having two values by two different voltages. A state in which a signal output from a delay circuit that outputs the signal after a predetermined delay is compared with an input signal, and the matched value is output as an output signal instead of the value output when the values of both signals match. When the power supply voltage detected by the voltage detection circuit is abnormal , the signal is output by switching between a state in which the input signal is output as an output signal as it is. Therefore, by switching the switching signal according to the state of the system, it is possible to switch between noise cancellation and quick signal output.
[0008]
In the noise canceling circuit according to the present invention, the delay circuit may include one or more flip-flops that output the value of the input signal at a predetermined timing of an input clock. By doing so, the delay time in the delay circuit can be set to a desired time by adjusting the clock frequency and the number of flip-flops connected in series. In the noise canceling circuit according to the aspect of the present invention, the signal output circuit outputs a circuit for inputting the switching signal for resetting the flip-flop, and a signal obtained by inverting a logical product of the input signal and the switching signal. A first NAND circuit, a second NAND circuit that inverts and outputs a logical product of the input signal and the signal output from the delay circuit, and a signal output from the second NAND circuit and the second NAND circuit. And a third NAND circuit which inverts and outputs a logical product of the signal output from one NAND circuit and the output.
[0009]
In the noise canceling circuit according to the present invention, the delay circuit may be formed by connecting an even number of circuits each including an inverter and a capacitor having one terminal grounded in series. Since the inverter (inverting circuit) includes a resistor, a circuit including the inverter and the capacitor constitutes an integrating circuit including the resistor and the capacitor, and delays signal output. In this case, the delay time in the delay circuit can be set to a desired time by adjusting the number of circuits including an even number of inverters and capacitors connected in series and the capacitance of the capacitors. In the noise canceling circuit according to the aspect of the present invention, the signal output circuit includes an AND circuit that performs a logical product of the input signal and a signal output from the delay circuit, and a signal output from the AND circuit and the switching circuit. A first NAND circuit for inverting a logical product of the inverted signal and outputting the inverted signal, a second NAND circuit for inverting and outputting the logical product of the input signal and the switching signal, and the first NAND circuit; And a third NAND circuit that inverts and outputs the logical product of the signal output from the NAND circuit and the signal output from the second NAND circuit.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described using examples. FIG. 1 is a configuration diagram schematically showing a configuration of a noise cancellation circuit 20 according to one embodiment of the present invention. As shown, the noise canceling circuit 20 of the embodiment includes a delay circuit 28 including three D flip-flops FP1, FP2, and FP3 connected in series to an input signal terminal 22 for inputting an input signal. A first NAND circuit 30 that inverts and outputs the logical product of the signal from the input signal and the input signal, and a second NAND circuit that inverts and outputs the logical product of the switching signal input from the switching signal terminal 24 and the input signal The NAND circuit includes a NAND circuit 32 and a third NAND circuit 34 that inverts and outputs a logical product of a signal from the first NAND circuit 30 and a signal from the second NAND circuit 32.
[0011]
A clock input terminal CK of each of the D flip-flops FP1, FP2, FP3 is connected to a clock terminal 26 for inputting a clock. The D flip-flop outputs the signal input to the input terminal D from the output terminal Q at the time of rising of the clock. As described above, in the delay circuit 28 of the embodiment, the D flip-flops FP1, FP2, FP3 are connected in series, that is, the input terminal D of the second and subsequent D flip-flops FP2, FP3 is connected to the output terminal Q of the preceding stage. Therefore, the input signal is delayed by the first-stage D flip-flop FP1 until the rise of the clock, and is delayed by one clock at each of the second-stage and third-stage D flip-flops FP2 and FP3. The output from the delay circuit 28 is delayed by two clocks + α.
[0012]
The reset terminal R of each of the D flip-flops FP1, FP2, FP3 is connected to a switching signal terminal 24 for inputting a switching signal. Accordingly, when the switching signal is Hi, each of the D flip-flops FP1, FP2, FP3 is reset, so that Lo is output from the delay circuit 28.
[0013]
FIG. 2 is an explanatory diagram illustrating the operation of the noise canceling circuit 20 of the embodiment when the input signal and the switching signal are changed. In the figure, points A, B, and C are the output of the delay circuit 28, the output of the first NAND circuit 30, and the output of the second NAND circuit 32, respectively, as shown in FIG.
[0014]
Now, consider the case where the switching signal is Hi. At this time, since the D flip-flops FP1, FP2, FP3 of the delay circuit 28 are reset, the output (point A) from the delay circuit 28 is always Lo. Therefore, the output (point B) from the first NAND circuit 30 is always Hi regardless of the input signal Hi / Lo. Since the second NAND circuit 32 functions as an inverter (inverting circuit) for the input signal when the switching signal is Hi, the output (point C) from the second NAND circuit 32 is an inverted signal of the input signal. The third NAND circuit 34 functions as an inverter with respect to the output from the second NAND circuit 32 when the output from the first NAND circuit 30 is Hi, so that the output from the third NAND circuit 34 (output signal ) Is the inverted version of the output from the second NAND circuit 32, that is, the input signal itself. Therefore, the noise canceling circuit 20 of the embodiment functions as a circuit that outputs the input signal as it is when the switching signal is Hi.
[0015]
Next, consider the case where the switching signal is Lo. At this time, the delay circuit 28 outputs the input signal with a delay of 2 clocks + α. The first NAND circuit 30 inverts and outputs the logical product of the signal output and the input signal delayed by two clocks + α. As shown by the Hi signal 1 in FIG. 2, when the Hi level of the input signal ends in a time less than 2 clocks + α, the Hi level of the output (point A) from the delay circuit 28 and the Hi level of the input signal overlap. Therefore, the output (point B) from the first NAND circuit 30 remains at the Hi level. That is, for a signal which becomes Hi for a short time such as noise, the signal is canceled. However, as shown in Hi signal 2 in FIG. 2, when the Hi level of the input signal lasts longer than 2 clocks + α, the Hi level of the output (point A) from delay circuit 28 and the Hi level of the input signal become higher. Because of the overlap, the output (point B) from the first NAND circuit 30 becomes Lo level by the overlap. The output (point C) of the second NAND circuit 32 is always Hi when the switching signal is Lo, regardless of the input signal Hi / Lo. The third NAND circuit 34 functions as an inverter with respect to the output from the first NAND circuit 30 when the output from the second NAND circuit 32 is Hi, so that the output from the third NAND circuit 34 (output signal ) Is the inverse of the output (point B) from the first NAND circuit 30, that is, the logical product of the output from the delay circuit 28 and the input signal. Therefore, when the switching signal is Lo, the noise canceling circuit 20 of the embodiment functions as a noise canceling circuit that cancels an input signal that becomes Hi only for a short time such as noise.
[0016]
According to the noise canceling circuit 20 of the embodiment described above, the function as a circuit for directly outputting an input signal and the function as a circuit for canceling noise can be switched and used. Therefore, according to the state of the system using this circuit, it is possible to function as a noise canceling circuit when it is necessary to cancel noise and to function as a circuit for directly outputting an input signal when quick response is required.
[0017]
In the noise cancellation circuit 20 of the embodiment, three D flip-flops FP1, FP2, and FP3 are connected in series as the delay circuit 28, but the number of D flip-flops may be any number. Since the delay time in the delay circuit 28 can be determined by the clock frequency and the number of D flip-flops, the number of D flip-flops may be set according to the clock frequency to be used and the target delay time.
[0018]
Next, a noise canceling circuit 120 according to a second embodiment of the present invention will be described. FIG. 3 is a configuration diagram schematically illustrating a configuration of the noise cancellation circuit 120 according to the second embodiment. As shown, the noise cancellation circuit 120 of the second embodiment outputs a logical product of a delay circuit 128 connected to an input signal terminal 122 for inputting an input signal and the signal from the delay circuit 128 and the input signal. AND circuit 129, an inverting circuit 131 for inverting the switching signal input from the switching signal terminal 124, and a first circuit for inverting and outputting the logical product of the signal from the inverting circuit 131 and the signal from the AND circuit 129. , A second NAND circuit 132 that inverts the logical product of the switching signal and the input signal, and outputs the inverted signal, and a signal from the first NAND circuit 130 and a signal from the second NAND circuit 132 A third NAND circuit 134 that inverts and outputs a logical product.
[0019]
The delay circuit 128 includes two inverters (inverting circuits) I1 and I2 connected in series, and two capacitors C1 and C2 connected to the output terminals of the inverters I1 and I2 and the ground. Considering a circuit including a set of an inverter and a capacitor, the inverter includes a resistance component. Therefore, it can be considered that this circuit includes an inverting circuit and an integrating circuit. The delay circuit 128 of the embodiment is formed by connecting two such circuits each composed of a set of inverters and capacitors in series, so that two inverting circuits and two integrating circuits are connected, and the resulting signal Considering only, it can be considered that two integrating circuits are connected.
[0020]
FIG. 4 is an explanatory diagram illustrating the operation of the noise canceling circuit 120 according to the second embodiment when the input signal and the switching signal are changed. 3, points D, E, F, and G correspond to the output of the delay circuit 128, the output of the AND circuit 129, the output of the first NAND circuit 130, and the second point, respectively, as shown in FIG. This is the output of the NAND circuit 132.
[0021]
Now, consider the case where the switching signal is Hi. At this time, Lo, which is an inverted signal of the switching signal, is input to the first NAND circuit 130 from the inverting circuit 131, so that the output from the first NAND circuit 130 is always irrespective of the output from the AND circuit 129. Hi. Since the second NAND circuit 132 functions as an inverter (inverting circuit) for the input signal when the switching signal is Hi, the output (point G) from the second NAND circuit 132 is an inverted signal of the input signal. When the output from the first NAND circuit 130 is Hi, the third NAND circuit 34 functions as an inverter with respect to the output from the second NAND circuit 132, so that the output from the third NAND circuit 134 (the output signal ) Is the inverted output of the second NAND circuit 132, that is, the input signal itself. Therefore, the noise canceling circuit 120 of the second embodiment functions as a circuit that outputs an input signal as it is when the switching signal is Hi.
[0022]
Next, consider the case where the switching signal is Lo. At this time, the delay circuit 128 shows an operation of gradually changing the potential with respect to the input signal by the function of the integration circuit. As shown by the Hi signal 3 in FIG. 4, when the Hi level of the input signal is short, the input signal is output before the potential (point D) from the delay circuit 128 becomes higher than the threshold value Vref determined as Hi. Since the signal becomes Lo level, the AND circuit 129 determines that the signal from the delay circuit 128 is Lo, and the AND circuit 129 outputs Lo. That is, for a signal which becomes Hi for a short time such as noise, the signal is canceled. On the other hand, as shown by the Hi signal 4 in FIG. 4, when the Hi level of the input signal continues for a long time, the potential (point D) from the delay circuit 128 becomes higher than the threshold value Vref determined as Hi. Since there is sufficient time, the AND circuit 129 determines that the signal is Hi when the output (point D) from the delay circuit 128 exceeds the threshold value Vref. The AND circuit 129 calculates the logical product of the signal from the delay circuit 128 and the input signal. Therefore, the output of the AND circuit 129 is output when the input signal is at the Hi level and when the signal from the delay circuit 128 exceeds the threshold value Vref. Becomes Hi when and overlap. When the signal from the inverting circuit 131 is Hi (when the switching signal is Lo), the first NAND circuit 130 functions as an inverter with respect to the output from the AND circuit 129. The output is obtained by inverting the signal from the AND circuit 129, that is, by inverting the logical product of the input signal and the signal from the delay circuit 128. The output (point G) of the second NAND circuit 132 is always high when the switching signal is low. The third NAND circuit 134 functions as an inverter with respect to the output from the first NAND circuit 130 when the signal from the second NAND circuit 132 is Hi, so that the output (output) from the third NAND circuit 134 The signal is a signal obtained by inverting the signal from the first NAND circuit 130, that is, a signal represented by the logical product of the input signal and the signal from the delay circuit 128. Therefore, when the switching signal is Lo, the noise canceling circuit 120 of the second embodiment functions as a noise canceling circuit that cancels an input signal that becomes Hi only for a short time such as noise.
[0023]
According to the noise canceling circuit 120 of the second embodiment described above, the function as a circuit for outputting an input signal as it is and the function as a circuit for canceling noise can be switched and used. Therefore, according to the state of the system using this circuit, it is possible to function as a noise canceling circuit when it is necessary to cancel noise and to function as a circuit for directly outputting an input signal when quick response is required.
[0024]
In the noise canceling circuit 120 of the second embodiment, two circuits each including a set of inverters and capacitors are connected in series as the delay circuit 128. However, an even number of sets may be connected in series. Further, a resistor may be used instead of the inverters I1 and I2. When a resistor is used instead of the inverters I1 and I2, the number of circuits including the resistor and the capacitor may be an odd number instead of an even number.
[0025]
As described above, the embodiments of the present invention have been described with reference to the examples. However, the present invention is not limited to these examples, and may be implemented in various forms without departing from the gist of the present invention. Obviously you can get it.
[Brief description of the drawings]
FIG. 1 is a configuration diagram schematically illustrating a configuration of a noise canceling circuit 20 according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram illustrating the operation of the noise canceling circuit 20 of the embodiment when the input signal and the switching signal are changed.
FIG. 3 is a configuration diagram schematically illustrating a configuration of a noise cancellation circuit 120 according to a second embodiment.
FIG. 4 is an explanatory diagram illustrating an operation state of a noise canceling circuit 120 of a second embodiment when an input signal and a switching signal are changed.
[Explanation of symbols]
20, 120 noise canceling circuit, 22, 122 input signal terminal, 24, 124 switching signal terminal, 26 clock terminal, 28, 128 delay circuit, 30, 130 first NAND circuit, 32, 132 second NAND circuit, 34 , 134 Third NAND circuit, 36, 136 output terminal, 129 AND circuit, 131 inverting circuit, FP1, FP2, FP3 D flip-flop, I1, I2 inverter, C1, C2 capacitor.

Claims (5)

A power supply voltage applied to the system is detected by a voltage detection circuit, and when there is an abnormality in the power supply voltage, two different voltages output from the voltage detection circuit to reset power supply to the system are used. A noise canceling circuit capable of canceling noise that may occur in an input signal having two values,
A delay circuit that delays and outputs the input signal for a predetermined time;
When the power supply voltage detected by the voltage detection circuit is normal based on the input of the switching signal having two values by two different voltages, the signal output from the delay circuit is compared with the input signal. A state in which the value output from the voltage detection circuit is output when the value of the two signals is the same, instead of the value output when the values of the two signals match, and the input signal is output when the power supply voltage detected by the voltage detection circuit is abnormal. And a signal output circuit that outputs a signal by switching between a state in which the signal is output as it is and an output signal as it is. 2. The noise canceling circuit according to claim 1, wherein the delay circuit includes one or more flip-flops that output an input value at a predetermined timing of an input clock. The signal output circuit is a circuit that inputs the switching signal to reset the flip-flop, a first NAND circuit that outputs a signal obtained by inverting a logical product of the input signal and the switching signal, A second NAND circuit that inverts and outputs a logical product of the signal output from the delay circuit and the output of the second NAND circuit, and outputs a signal output from the second NAND circuit and a signal output from the first NAND circuit. 3. The noise cancel circuit according to claim 2, further comprising a third NAND circuit that inverts and outputs a logical product. 2. The noise canceling circuit according to claim 1, wherein the delay circuit is configured by connecting an even number of circuits each including an inverter and a capacitor having one terminal grounded in series. The signal output circuit calculates an AND circuit of the input signal and a signal output from the delay circuit, and calculates a logical product of a signal output from the AND circuit and a signal obtained by inverting the switching signal. A first NAND circuit for inverting and outputting, a second NAND circuit for inverting and outputting a logical product of the input signal and the switching signal, and a signal output from the first NAND circuit and 5. The noise canceling circuit according to claim 4, further comprising a third NAND circuit for inverting a logical product of the signals output from the two NAND circuits and outputting the inverted product.

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