JP3552252B2 - Information signal recording / reproducing apparatus and information signal recording / reproducing method - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to an information signal recording / reproducing apparatus suitable for application to a digital VTR, for example.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, as a digital VTR for recording video and audio information to be recorded in a digital format, there are, for example, those shown in FIGS.
[0003]
FIGS. 11 and 12 show, for example, a recording system and a reproducing system of a digital VTR. The digital VTR will be described below with reference to FIGS.
[0004]
In FIG. 11, a digital video signal input via an input terminal 1 is stored in a buffer memory 2 and then supplied to a DCT (Discrete Cosine Transform) circuit 3, where the DCT circuit 3 outputs a 4 × 4 block. The DC component is converted into coefficient data of a higher-order AC component, and is converted into two-dimensional spatial frequency data (coefficient data).
[0005]
The coefficient data from the DCT circuit 3 is supplied to a quantization circuit 4, and the quantization circuit 4 sequentially reduces the quantization level from low-frequency coefficient data to high-frequency coefficient data to reduce the amount of information. Is done. Quantized coefficient data obtained by quantization by the quantization circuit 4 is supplied to an outer coding circuit 5.
[0006]
The quantized coefficient data supplied to the outer code circuit 5 is added with an outer code parity OP in the outer code circuit 5 and is stored in the field memory 6 by the write address from the address counter 7. The quantized coefficient data stored in the field memory 6 is read by an address counter 7 based on a read address supplied from a ROM 8 and supplied to a coding circuit 9 where the parity IP of the inner code is added and multiplied. After being converted into a code, ID data and sync data are added for each inner code to convert the signal from an 8-bit parallel signal to a 1-bit serial signal having an eight-fold clock frequency, and then a recording head via an amplifier circuit 10 and a rotary transformer 11. 13 and is recorded on the magnetic tape 14 so as to record an inclined track.
[0007]
Here, the format of the product code will be described with reference to FIG. As shown in FIG. 13, the format of the product code includes an inner code and an outer code. The inner code is composed of digital data DA and parity IP of the inner code as shown in FIG. 13A, and the outer code is added to the vertical data of the digital data DA shown in FIG. It is composed of an outer code parity OP. As shown in FIG. 13B, the product code includes the inner code shown in FIG. 13A and the outer code shown in FIG. 13C.
[0008]
Next, a reproduction system of the digital VTR will be described with reference to FIG. The recording signal recorded on the magnetic tape 14 is reproduced by a reproducing head 15 and thereafter supplied to a reproduction equalizing circuit 17 via a rotary transformer 16, where the waveform is equalized and then supplied to a PLL circuit 18.
[0009]
The PLL circuit 18 reproduces a clock signal based on the reproduced data. Further, in the synchronization detecting circuit 19, the reproduced data of the 1-bit serial data is converted into 8-bit parallel data having a clock frequency 1/8 times that of the recording. This converted data is supplied to the inner code error correction circuit 20.
[0010]
The reproduced data supplied to the inner code error correction circuit 20 is subjected to an error correction process using the parity IP of the inner code to correct a random error, and then together with the error flag generated here, the field memory 22 and ID decoding. Each is supplied to the circuit 21.
[0011]
The ID decoding circuit 21 decodes the ID from the output data from the inner code error correction circuit 20, and generates a write address based on the decoded ID. Therefore, the output data from the inner code error correction circuit 20 is stored by the write address from the ID decoding circuit 21.
[0012]
The data written to the field memory 22 is read by the read address generated by the address counter 24 based on the synchronization signal supplied via the input terminal 23, and is supplied to the outer code error correction circuit 25. After the burst error is corrected by the parity OP of the outer code in the correction circuit 25, the burst error is supplied to an IDCT (inverse discrete cosine transform) circuit 26.
[0013]
The output of the outer code error correction circuit 25 supplied to the IDCT circuit 26 is inversely quantized and then subjected to inverse discrete cosine transform to obtain original digital data. After that, it is supplied to the error correction circuit 27 together with the error flag. Then, after performing processing such as interpolation based on the error flag in the error correction circuit 27, the signal is output from the output terminal 28 as a reproduced digital video signal.
[0014]
As is well known, the interpolation processing in the error correction circuit 27 is performed by replacing the bit with an error flag with the previous data. The fact that a bit is set in the error flag means that data corresponding to the error flag could not be completely corrected at the time of error correction. Therefore, in this case, as described above, the past data is replaced.
[0015]
In a digital VTR that does not use compression, correction is performed on erroneous data, for example, by interpolating using surrounding data using the correlation of images. For example, it is common to replace the error data with the average value of the four points of pixel data at the top, bottom, left and right of the error data or replace the error data with the average value of the pixel data of the two points at the left and right of the error data.
[0016]
However, a signal to be recorded as shown in FIGS. 11 and 12 is compressed and recorded, and encoding is performed using a digital VTR such as DCT or orthogonal transform which is expanded during reproduction. In a digital VTR, if even one of the component data in a block has an error, the effect is not limited to the pixel but extends to the entire block. Need to be targeted.
[0017]
Therefore, even if intra-field encoding is performed in encoding, it is difficult to use peripheral pixels belonging to the same field in modification, and as described above, modification is mainly performed using pixel data at the same spatial position in the past. It is to be done.
[0018]
[Problems to be solved by the invention]
By the way, the past correction using pixel data at the same spatial position can be performed almost completely when the image is stationary, but when the image is moving, pixel data having a weak correlation is used. Since the correction is performed using the correction, there is an inconvenience that the image quality of the corrected image is deteriorated.
[0019]
In particular, when the camera itself moves at the time of shooting, such as panning or tilting, there is an inconvenience that the probability of deterioration is extremely high.
[0020]
The present invention has been made in view of such a point, and it is possible to accurately correct an error even when a moving image is recorded and reproduced, thereby obtaining an information signal recording capable of obtaining a good reproduced image. It is intended to propose a playback device.
[0021]
[Means for Solving the Problems]
The present invention relates to a detecting means 40 for detecting information related to an information signal to be recorded at the time of recording an information signal, and a storing means 41 for storing information detected by the detecting means 40 in a storage section 41 of a tape cassette 60. An error correcting means 57 for correcting an error of the information signal based on the related information read from the storage section 41 at the time of reproducing the reproduced signal; The error correction unit 57 includes a reproduction signal storage unit 105 that stores a reproduced information signal, and a past information signal that is an information signal read from the reproduction signal storage unit 105, is read from the storage unit 41 of the cassette 60. A motion compensating unit 101 that performs a motion compensation process based on the motion information as related information, and an output from the motion compensating unit 101 when an error is detected based on information indicating whether or not an error is detected. Otherwise, selecting means 103 for selecting the current information signal; It has.
[0022]
Also, the present invention A detecting step of detecting information related to the information signal to be recorded at the time of recording the information signal; a storing step of storing the information detected by the detecting step in the storage unit 41 of the tape cassette 60; An error correction step of correcting an error of the information signal based on the related information read from the unit 41. The error correction step includes a reproduction signal storage step of storing the reproduced information signal in the reproduction signal storage unit 105. A motion compensation step in which a past information signal, which is an information signal read from the reproduction signal storage means 105, is subjected to motion compensation processing by the motion compensation means 101 based on motion information, which is related information read from the storage section 41 of the cassette 60; And, based on the information indicating whether or not there is an error, when there is an error, select the output from, and when there is no error, the current information signal A selection step of selecting, the Things.
[0023]
[Action]
According to the present invention, the information relating to the information signal to be recorded at the time of recording the information signal is detected by the detection means 40, and the information detected by the detection means 40 is stored in the storage section 41 of the tape cassette 60 by the storage means 41. At the time of storing and reproducing the reproduction signal, the error correction of the information signal is performed by the error correction means 57 based on the related information read from the storage unit 41. In the error correction means 57, the reproduced information signal is stored in the reproduction signal storage means 105, and the past information signal, which is the information signal read from the reproduction signal storage means 105, is read from the storage section 41 of the cassette 60. The motion compensating means 101 performs motion compensation processing based on the motion information as information, and the selecting means 103 selects an output from the motion compensating means 101 when there is an error based on information indicating whether or not there is an error. If no error, select current information signal .
[0024]
According to the present invention, In the detection step, information related to the information signal to be recorded at the time of recording the information signal is detected, and the information detected by the detection step is stored in the storage unit 41 of the tape cassette 60 in the storage step. Based on the related information read from the unit 41, an error correction of the information signal is performed in an error correction step. In the error correction step, the reproduced information signal is stored in the reproduction signal storage unit 105 in the reproduction signal storage step, and the reproduction signal is stored. A past information signal which is an information signal read from the storage means 105 is subjected to a motion compensation process by the motion compensation means 101 in a motion compensation step based on the motion information which is the related information read from the storage section 41 of the cassette 60, and is selected. Based on the information indicating whether or not there is an error in the process, if there is an error, select the output from, and if there is no error, select the current information signal. To-option .
[0025]
【Example】
Hereinafter, an embodiment of the information signal recording / reproducing apparatus of the present invention will be described in detail with reference to FIG.
[0026]
In FIG. 1, reference numeral 30 denotes an input terminal to which an analog video signal from a signal source (not shown) is supplied. The analog video signal is supplied to the A / D converter 31 via the input terminal 30. The analog video signal is converted into a digital video signal by the A / D converter 31 and then supplied to a blocking circuit 32 and a motion vector detection circuit 40 described later.
[0027]
The blocking circuit 32 converts the digital video signal (hereinafter, referred to as image data) from the A / D converter 31 into an area consisting of, for example, (8 pixels in the horizontal direction) × {8 pixels (lines) in the vertical direction} as one image block. Image data of one frame (for one screen) is divided into a plurality of image blocks. In this case, one image block is composed of 64 samples. Further, the blocking circuit 32 eliminates a blanking period in the input video signal, makes the valid data continuous, and forms a data absence period in the data sequence.
[0028]
The image data of each image block from the blocking circuit 32 is supplied to a shuffling circuit 33. The shuffling circuit 33 performs a shuffling process by address control of a memory (not shown), and performs a process of rearranging all the plurality of pixel blocks in the frame in units of image blocks according to a predetermined rule in one frame. Do.
[0029]
The output of the shuffling circuit 33 is supplied to a block encoding circuit 34. In this example, it is assumed that DCT (Discrete Cosine Transform) is adopted for the block encoding circuit 34.
[0030]
Here, the block encoding circuit 34 will be described with reference to FIG.
[0031]
In the figure, reference numeral 80 denotes an input terminal to which the output from the shuffling circuit 33 shown in FIG. 1 is supplied, and the shuffled data is supplied to the DCT conversion circuit 81 via the input terminal 80.
[0032]
The DCT conversion circuit 81 performs DCT conversion processing on the shuffled data for each image block, and converts the data into, for example, 8 × 8 coefficient data corresponding to a plurality of block sizes. The coefficient data includes DC component coefficient data DC and a plurality of AC component coefficient data ACi (i = 1 to 63).
[0033]
The coefficient data from the DCT conversion circuit 81 is supplied to a block scanning circuit 82. The block scanning circuit 82 outputs the coefficient data from the DCT conversion circuit 81 in a zigzag scan for each block. In general, the DCT coefficient is visually more important in the low frequency component than in the high frequency component. In the block scanning circuit 82, the DC component coefficient is regarded as the data having the highest importance. Can be rearranged.
[0034]
The coefficient data from the block scanning circuit 82 is supplied to a requantization circuit 83. The requantization circuit 83 quantizes the coefficient data based on data indicating a quantization step supplied from the buffer control circuit 86.
[0035]
The output of the requantization circuit 83 is supplied to a variable length coding circuit 84. The variable length coding circuit 84 is provided for performing rate conversion so that the coefficient data does not exceed a predetermined transmission rate, that is, the transmission rate of a tape recording / reproducing conversion system in the case of a digital VTR. That is, the data rate on the input side of the buffer memory 85 is variable, but the data rate on the output side is substantially constant.
[0036]
The buffer memory 85 detects a change in the amount of transmission data and supplies a detection output to a buffer control circuit 86. The buffer control circuit 86 controls the quantization step of the requantization circuit 83, and controls the transmission data output from the variable length coding circuit 84 to have a predetermined data amount.
[0037]
The variable-length encoding circuit 84 encodes the coefficient data from the requantization circuit 83 by using a method such as Huffman or run-length encoding. This encoded data is supplied to the buffer memory 85.
[0038]
An output signal from the buffer memory 85, that is, an output signal of the block encoding circuit 34 is supplied to the framing circuit 35 shown in FIG.
[0039]
Here, returning to FIG. The framing circuit 35 generates parity of the error correction code and generates recording data having a structure in which the synchronization blocks are continuous. As the error correction code, for example, a product code for performing an error correction code in each of the horizontal direction and the vertical direction of the data matrix array is used. That is, in the framing circuit 35, the sync (SYNC) block synchronization signal and the ID signal are added to the encoded data and the parity.
[0040]
The output of the framing circuit 35 is supplied to a channel coding circuit 36. The channel encoding circuit 36 performs a channel encoding process for reducing a DC component, and converts data into a bit stream. The output of the channel encoding circuit 36 is supplied to a magnetic head (magnetic head mounted on a rotating drum) 38 via a recording amplifier 37, and is recorded so as to form an inclined track on the recording surface of the magnetic tape 39. Usually, two or more magnetic heads are used, but in this example, only one head is shown for convenience of explanation.
[0041]
The image data from the A / D converter 31 is also supplied to the motion vector detection circuit 40. Here, the motion vector detection circuit 40 will be described with reference to FIG.
[0042]
6, reference numeral 90 denotes an input terminal to which image data from the A / D converter 31 shown in FIG. 1 is supplied, and image data is supplied to the addition circuit 92 and the representative point memory 91 via the input terminal 90, respectively. You.
[0043]
The representative point memory 91 stores image data Ik (0, 0) of representative points for each block obtained by dividing image data supplied from the AD converter 31 via the input terminal 90 into a plurality of blocks for each field. I do. Specifically, for example, as shown in FIG. 8, an image for one field is decomposed into blocks of m pixels × n lines, and as shown in FIG. 9, the central pixel S (0,0) of each block is represented by a representative point. Then, the image data Ik (0, 0) of each representative point pixel is stored in the representative point memory 51 for one field period. Note that the representative points are evenly distributed on the screen. Then, the image data Ik-1 (0,0) of each representative point pixel one field before, which is read from the representative point memory 91, is supplied to the adding circuit 92.
[0044]
The adder circuit 92 performs the following processing on the input video signal supplied from the AD converter 31 via the input terminal 90, that is, the image data of the current field. That is, image data Ik (x, y) of m × n pixels of each block and image data Ik−1 (0, 0) of representative point pixels of the corresponding block in the previous field read from the representative point memory 91. , I.e., the absolute value of the inter-field difference | Ik-1 (0,0) -Ik (x, y) |. Then, the absolute value | Ik-1 (0,0) -Ik (x, y) | of the difference between the fields obtained by the adding circuit 92 is supplied to the correlation integrated value table forming circuit 93.
[0045]
The correlation integrated value table forming circuit 93 calculates the absolute value | Ik-1 (0,0) -Ik (x, y) | of the inter-field difference of each block obtained from the adding circuit 92 for each pixel corresponding to one field. The integration is performed over the period to form a correlation integration value table having m × n integer coordinates corresponding to the pixel arrangement of one block.
[0046]
The correlation integrated value table formed by the correlation integrated value table forming circuit 93 is an integrated value of m × n absolute values | Ik−1 (0,0) −Ik (x, y) | That is, it shows the distribution of the correlation integrated value. Then, m × n correlation integrated values of the correlation integrated value table formed by the correlation integrated value table forming circuit 93 are supplied to the motion vector determination circuit 94.
[0047]
The motion vector determination circuit 94 detects the coordinates of the minimum value of the correlation integrated value in the correlation integrated value table formed by the correlation integrated value table forming circuit 93 and determines the motion vector. The correlation integrated value of the correlation integrated value table formed by the correlation integrated value table forming circuit 93 is represented by image data Ik-1 (0, 0) of a representative point pixel of each block and image data Ik (x, y) of other pixels. ), The smaller the value of the coordinate corresponding to the pixel having a strong correlation, the smaller the integrated value of the correlation of the coordinate corresponding to the motion vector. Therefore, the motion vector can be determined by detecting the coordinates of the minimum value. As the output of the motion vector determination circuit 94, the determined motion vector is output. The output of the motion vector determination circuit 94, that is, the output of the motion vector detection circuit 40, is stored at a predetermined position in the semiconductor memory of the memory unit 43 of the tape cassette described later.
[0048]
Here, the configuration of the tape cassette used in this example will be described with reference to FIGS.
[0049]
As shown in FIG. 3, the tape cassette 60 has a semiconductor memory unit 41 including a memory unit 43 having a semiconductor memory such as an SRAM (Static RAM) and an interface unit 42 incorporated in the cassette body 61. Although not shown, the cassette main body 61 also houses a magnetic tape wound around the reels 62 and 63, and has a structure in which an opening 64 for drawing out the magnetic tape is provided on the entire surface side. I have. The storage position of the semiconductor memory unit 41 may be any position that does not hinder the recording or reproduction of the tape cassette 60 set in a digital VTR or the like. There is no restriction on the position in.
[0050]
Here, the interface section 42 is mainly composed of an interface connector, is connected to the VTR-side connector, and transmits and receives data. The memory unit 43 is electrically connected to the interface unit 42, and transmits and receives data and the like to and from the VTR via the interface unit 42.
[0051]
Here, the interface unit 42 and the memory unit 43 will be described in more detail with reference to FIG.
[0052]
In the figure, reference numeral 70 denotes a read / write (R / W) and chip select (CE) circuit. The read / write and chip select circuit 70 is an address supplied from a VTR (shown by a broken line) via an interface circuit 42. The control signal CON1 is fetched based on the signal AD1, and a control signal for controlling the timing of writing and reading is supplied to the RAM 71 based on the fetched control signal CON1.
[0053]
The RAM 71 may be, for example, an SRAM, a DRAM, an EEPROM, or the like. Here, an SRAM that does not require a refresh circuit is used. Of course, a generally used IC memory may be used.
[0054]
Based on the control signal CON2 supplied from the read / write and chip select circuit 70, the RAM 71 sets the address indicated by the address signal AD2 supplied from the VTR via the interface circuit 42, and similarly controls the interface circuit 42 from the VTR. Write the data DA supplied through the interface. At the time of reading, the data DA stored at the address indicated by the address signal AD2 supplied from the VTR via the interface circuit 42 is read based on the control signal CON2 supplied from the read / write and chip select circuit 70. .
[0055]
Reference numeral 72 denotes a power supply control circuit. The power supply control circuit 72 supplies a power supply VCC supplied from the VTR side via the interface unit 42 to the read / write and chip select circuit 70 and the RAM 71, respectively. An appropriate voltage value VPP of the power supply supplied via the unit 42 and a potential by the ground GND are supplied to the read / write and chip select circuit 70, respectively.
[0056]
The power supply control circuit 72 supplies a normal voltage value signal VBAT to the VTR via the interface unit 42 if the voltage value is appropriate. Further, the power supply control circuit 72 generates a reset signal based on a reference signal (for example, obtained from the VTR side or in a state of a reset switch provided on the tape cassette main body 61) supplied through the input terminal 74, A reset signal is supplied (supplied for a predetermined time) to the read / write and chip select circuit 70 to bring the read / write and chip select circuit 70 into an appropriate driving state and to supply a memory voltage to the RAM 71.
[0057]
Reference numeral 73 denotes a backup battery. The backup battery 73 operates during operation (especially during writing) when the operation stops momentarily while the RAM 71 is operating or when the voltage suddenly drops. Is a backup voltage supply source for maintaining a good state of separation.
[0058]
Next, the reproducing side will be described with reference to FIG. At the time of reproduction, the recorded data on the magnetic tape 39 is reproduced by the magnetic head 50, and the reproduced data is supplied to the channel decoding circuit 52 via the reproduction amplifier 51, and the channel decoding circuit 52 performs the channel decoding process. Is applied.
[0059]
The output from the channel decoding circuit 52 is supplied to a frame decomposition circuit 53. The frame decomposition circuit 53 corrects the error of the data supplied from the channel decoding circuit 52, and sets an error flag in units of bytes for data that cannot be restored even after the error correction processing, thereby distinguishing the data from error-free data. It can be so. Then, various data are separated from the recording data. The output of this frame decomposition circuit 53 is supplied to a block decoding circuit 54.
[0060]
The block decoding circuit 54 performs an inverse DCT on the data supplied from the frame decomposition circuit 53 to generate a decoded value for each pixel. The output of the block decoding circuit 54 is supplied to a de-shuffling circuit 55.
[0061]
The de-shuffling circuit 55 is complementary to the recording-side shuffling circuit 33, and performs processing for returning the spatial position of the block to the original position. The output data of the deshuffling circuit 55 is supplied to a block decomposition circuit 56. The block decomposition circuit 56 returns the data order from the block order to the raster scan order. The output of the block decomposition circuit 56 is supplied to an error correction circuit 57.
[0062]
The error correction circuit 57 performs correction (concealment) on data having an error on a pixel-by-pixel basis with pixel data around the data. In a digital VTR that does not perform compression during recording and does not perform expansion during reproduction, correction is performed on erroneous data by performing interpolation using peripheral data using image correlation. For example, a general method is to replace the error data with the average value of the four points of the pixel data of the upper, lower, left and right of the error data, or replace the error data with the average value of the two points of the pixel data of the error data.
[0063]
However, as described above, when data encoded using an orthogonal transform (DCT or the like) is reproduced, if any one of the component data in the block has an error, the effect is affected by the pixel. Therefore, the correction needs to be performed not on the pixels but on the blocks when performing the correction. This is because the data is converted into coefficient data from the DC component to the high-order AC component for each block during recording.For example, if the DC component or low-order AC component coefficient data becomes an error, it is visually affected. Since a certain DC component or low-order AC component causes an error, the image quality of the entire reproduced block naturally deteriorates.
[0064]
Therefore, in general, it is difficult to use peripheral pixels belonging to the same field in concealment even if intra-field coding is performed, and error correction is mainly performed using pixel data at the same spatial position in the past. It is carried out.
[0065]
However, the past correction using pixel data at the same spatial position can be performed almost completely when the image is still, but when the image is moving, the pixel data having a weak correlation is used. Therefore, image quality degradation tends to be conspicuous. In particular, when the camera itself has movements such as panning and tilting, the deterioration tends to be prominent stochastically.
[0066]
Therefore, in this example, as described above, the semiconductor memory unit 41 is mounted on the tape cassette 60, and motion information is stored in the semiconductor memory unit 41 during recording, and stored in the semiconductor memory unit 41 during reproduction. By performing motion compensation for data having an error based on stored motion information, deterioration of image quality is greatly reduced. The error correction circuit 57 is a circuit that performs these processes during reproduction. Hereinafter, the error correction circuit 57 will be described in detail with reference to FIG.
[0067]
7, reference numeral 100 denotes an input terminal to which the motion information from the semiconductor memory unit 41 described with reference to FIGS. 3 and 4 is supplied, and reference numeral 102 denotes an output (image data) from the block decomposition circuit 56 shown in FIG. An input terminal 104 is an input terminal to which an output (error flag) from the block decomposition circuit 56 shown in FIG. 2 is supplied, and 106 is a motion compensation processing output supplied from a motion compensation circuit 101 to be described later via a switch 103. Or an output terminal for supplying the image data from the block decomposition circuit 56 to the A / D converter 58 shown in FIG.
[0068]
The memory 105 holds the past one frame of image data of the current decoding field. That is, assuming that k fields are currently being decoded, the memory 105 holds output image data of (k-1) fields and (k-2) fields by a control signal from a not-shown write / read circuit or the like. You. The output of the memory 105 is supplied to the motion compensation circuit 101.
[0069]
The motion compensation circuit 101 shifts the data in the memory 105 according to the motion vector of the field of interest read from a predetermined position of the tape cassette 60 via the interface unit 42 of the tape cassette 60 shown in FIGS. For example, the following processing is performed as the shift processing.
[0070]
The motion compensating circuit 101 first obtains (k-1) from the (k-2) field from the output system of the digital VTR (for data output from the memory unit 43 of the tape cassette 60) via the interface unit 42 of the tape cassette 60. ) The data of the inter-field vector up to the field and the data of the inter-field vector from the (k-1) field to the k field are supplied, and the inter-frame vector from the (k-2) field to the k field is calculated.
[0071]
Subsequently, the motion compensation circuit 101 shifts the output data of the (k-2) field of the memory 105 by an inter-frame vector from the (k-2) field to the k field, and outputs the (k-1) field. The data is shifted by the inter-field vector from the (k-1) field to the k field to perform the motion compensation processing. An output signal of the motion compensation circuit 101 is supplied to one fixed contact 103a of the switch 103. When there is no object that moves differently from the vector calculated by the motion compensation processing by the motion compensation circuit 101, the image data of the k field currently used for decoding and the output data of the motion compensation circuit 101 are spatially the same. Will be present at the position.
[0072]
The decoded image data is supplied to the other fixed contact of the switch 103 from the block decomposition circuit 56 via the input terminal 100. The movable contact 103c of the switch 103 is connected to one fixed contact 103a when an error flag supplied from the block disassembling circuit 56 via the input terminal 104 is raised (when there is an error), and the error flag is raised. If there is no error (no error), it is connected to the other fixed contact 103b.
[0073]
That is, when the error flag indicates that there is an error in the decoded image data, the output data of the motion compensation circuit 101 is supplied to the DA converter 58 via the switch 103 and the output terminal 106, and the error flag is added to the decoded image data. When there is no error, the decoded image data from the block decomposition circuit 56 is supplied to the DA converter 58 via the switch 103 and the output terminal 106, and to the memory 105 via the switch 103.
[0074]
In other words, if there is no error in the data, decoded image data in that field is output, and if there is an error in the data, past decoded data whose spatial position has been compensated by motion compensation is output. . At this time, the output data of the (k-2) field held in the memory 105 is replaced with the output of the switch 103, that is, the output data of the k field.
[0075]
The decoded image data output from the error correction circuit 57 in this manner corresponds to each pixel, and is output as an output system of a digital VTR (not shown) via the output terminal 59 of FIG. Supplied to
[0076]
As described above, in this example, the motion vector data is stored in the tape cassette incorporating the semiconductor memory unit 41 when the image data is recorded, and is selected by the switch 103 in the memory 105 of the error correction circuit 57 during the reproduction. In addition to holding the read image data, the motion vector data stored in the semiconductor memory 41 of the tape cassette 60 is read, and a motion compensation process is performed based on the read motion vector data. Outputs the data subjected to the motion compensation processing, and outputs the data decoded by the block decomposition circuit 56 when the error flag is not set. Even if an error occurs in the VTR, image quality degradation can be greatly reduced. It is possible to obtain a good image quality me.
[0077]
That is, by performing the motion compensation process on the past image data, it is possible to correct even a moving image using the past data. Therefore, even when an error occurs, the probability of occurrence of a failure is greatly reduced, and a good reproduced image can be obtained.
[0078]
In the above-described example, the case where DCT is applied to the block encoding circuit 34 and inverse DCT is applied to the block decoding circuit 54 has been described, but data is recorded at the time of recording, such as ADRC (Adaptive Dynamic Range Coding). Any encoding process may be employed as long as it compresses and decompresses the data during reproduction. Even for a digital VTR that does not perform compression / expansion, for example, data (for example, motion vector data) used for error correction is stored in the semiconductor memory unit 41 of the tape cassette 60, and error correction during reproduction is performed in the same manner as described above. Even if a motion vector is used, the same effect as described above can be obtained.
[0079]
Further, in the above-described example, the case of calculating and recording one motion vector per field has been described. For example, as shown in FIG. 10, one screen of image data is divided into a plurality of macroblocks, and A method of detecting and recording a motion vector using a macro block may be used. This can improve the error correction performance for a plurality of movements in the screen.
[0080]
Further, in the above example, the image information is recorded on the magnetic tape of the tape cassette 60, and the motion vector is stored in the semiconductor memory section 41 of the tape cassette 60. However, the semiconductor memory section 41 is provided in the tape cassette 60. Instead, the motion vector may be recorded on the magnetic tape.
[0081]
The above-described embodiment is an example of the present invention, and it goes without saying that various other configurations can be adopted without departing from the spirit of the present invention.
[0082]
【The invention's effect】
According to the present invention, at the time of recording an information signal, information related to the information signal to be recorded is detected by the detection means, and the information detected by the detection means is stored in the storage unit of the tape cassette by the storage means. At the time of reproduction of the information signal, the error of the information signal is corrected by the error correcting means based on the related information read from the storage unit. In the error correction means, the reproduced information signal is stored in the reproduction signal storage means, and the past information signal, which is the information signal read from the reproduction signal storage means, is used as the motion information, which is the related information read from the storage part of the cassette. The motion compensating means performs motion compensation processing based on the information, and the selecting means selects an output from the motion compensating means when there is an error based on information indicating whether or not there is an error. Select information signal Thus, by performing the compensation processing on the past image data, it is possible to perform the correction using the past data without deteriorating the image quality. Therefore, even when an error occurs, the probability of occurrence of a failure is greatly reduced, and a good reproduced image can be obtained.
[0083]
According to the present invention, At the time of recording the information signal, information related to the information signal to be recorded is detected in the detection step, and the information detected by the detection step is stored in the storage unit of the tape cassette in the storage step. Based on the read related information, an error correction of the information signal is performed in an error correction step. In the error correction step, the reproduced information signal is stored in the reproduction signal storage unit in the reproduction signal storage step, and read out from the reproduction signal storage unit. A past information signal, which is an information signal obtained, is subjected to a motion compensation process by a motion compensation means in a motion compensation step based on motion information which is related information read from a storage unit of the cassette, and indicates whether or not an error has occurred in a selection step. Based on the information, if there is an error, select the output from, and if not, select the current information signal Thus, by performing the compensation processing on the past image data, it is possible to perform the correction using the past data without deteriorating the image quality. Therefore, even when an error occurs, the probability of occurrence of a failure is greatly reduced, and a good reproduced image can be obtained.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a recording side showing an embodiment of an information signal recording / reproducing apparatus of the present invention.
FIG. 2 is a configuration diagram on the reproducing side showing an embodiment of the information signal recording / reproducing apparatus of the present invention.
FIG. 3 is a configuration diagram showing an example of a tape cassette for explaining one embodiment of the information signal recording / reproducing apparatus of the present invention.
FIG. 4 is a block diagram showing an example of a semiconductor memory section of a tape cassette which is a main part of an embodiment of the information signal recording / reproducing apparatus of the present invention.
FIG. 5 is a block diagram showing an example of a block encoding circuit which is a main part of an embodiment of the information signal recording / reproducing apparatus of the present invention.
FIG. 6 is a block diagram showing an example of a motion vector detection circuit which is a main part of an embodiment of the information signal recording / reproducing apparatus of the present invention.
FIG. 7 is a block diagram showing an example of an error correction circuit which is a main part of an embodiment of the information signal recording / reproducing apparatus of the present invention.
FIG. 8 is an explanatory diagram for explaining a motion vector detection operation for explaining one embodiment of the information signal recording / reproducing apparatus of the present invention.
FIG. 9 is an explanatory diagram for explaining a motion vector detecting operation for explaining one embodiment of the information signal recording / reproducing apparatus of the present invention.
FIG. 10 is an explanatory diagram for explaining a motion vector detecting operation for explaining one embodiment of the information signal recording / reproducing apparatus of the present invention.
FIG. 11 is a configuration diagram showing an example of a recording system of a digital VTR as a conventional information signal recording / reproducing device.
FIG. 12 is a configuration diagram showing an example of a reproduction system of a digital VTR as a conventional information signal recording / reproduction device.
FIG. 13 is an explanatory diagram for explaining a configuration example of a product code used for describing a conventional information signal recording / reproducing device.
[Explanation of symbols]
40 Motion vector detection circuit
41 Semiconductor memory section
42 Interface section
43 Memory section
57 Error correction circuit
60 tape cassette
101 Motion compensation circuit
103 switch
105 memory

Claims (2)

An information signal recording / reproducing apparatus which records and reproduces an information signal using a cassette having a storage unit,
Detecting means for detecting information related to the information signal to be recorded when recording the information signal,
Storage means for storing the information detected by the detection means in the storage unit of the tape cassette;
Error correction means for correcting an error in the information signal based on the related information read from the storage unit during reproduction of the reproduction signal ,
The above error correction means,
Reproduction signal storage means for storing the reproduced information signal;
A motion compensation unit that performs a motion compensation process on the past information signal that is the information signal read from the reproduction signal storage unit based on the motion information that is the related information read from the storage unit of the cassette;
Based on the information indicating whether there is an error, when there is an error, the output from the motion compensation unit is selected, and when there is no error, a selection unit that selects the current information signal,
An information signal recording / reproducing apparatus comprising: In an information signal recording and reproducing method in which an information signal is recorded and reproduced using a cassette having a storage unit,
A detecting step of detecting information related to the information signal to be recorded when recording the information signal,
A storage step of storing the information detected by the detection step in the storage unit of the tape cassette;
An error correction step of correcting an error of the information signal based on the related information read from the storage unit during reproduction of the reproduction signal,
The error correction process described above
A reproduction signal storage step of storing the reproduced information signal in reproduction signal storage means;
A motion compensation step of performing a motion compensation process by a motion compensation unit based on motion information that is related information read from the storage unit of the cassette, the past information signal being an information signal read from the reproduction signal storage unit;
A selection step of selecting an output from the motion compensation means when an error is detected based on the information indicating whether or not the error is present, and selecting a current information signal when the error is not detected;
An information signal recording / reproducing method comprising:

Images