JP3552870B2 - Oscillation detection circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an oscillation detection circuit that detects whether or not a clock signal is generated normally.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, an oscillation detection circuit has been known as a circuit for detecting whether a clock signal is normally generated. According to the oscillation detection circuit, when the operation of the circuit for generating the clock signal, that is, the operation of the oscillator or the frequency divider is stopped and the clock signal is not output, the operation stop is detected and the oscillation state detection signal is detected. Can be output.
[0003]
[Problems to be solved by the invention]
FIG. 4 is a circuit diagram showing a configuration of a conventional oscillation detection circuit.
[0004]
In the figure, a high-resistance element having a resistance value on the order of giga ohms is used as a resistance element 401, and one end is connected to a power supply V._DDIt is connected to the. The p-type MOS transistor 402 has a gate to which the clock signal CLK is input and a source connected to the other end of the resistance element 401. The n-type MOS transistor 403 has a gate to which the clock signal CLK is input, a source grounded, and a drain connected to the drain of the p-type MOS transistor 402. Further, the drain of the p-type MOS transistor 402 and the power supply V_DDA capacitor 404 is provided between the two.
[0005]
The inversion gate 405 receives the clock signal CLK, inverts the signal value, and outputs the inverted signal. The p-type MOS transistor 406 receives the output signal of the inverting gate 405 from the gate, and has a source connected to the other end of the resistance element 401. The n-type MOS transistor 407 receives the output signal of the inverting gate 405 from the gate, has a source grounded, and has a drain connected to the drain of the p-type MOS transistor 406. Further, the drain of the p-type MOS transistor 406 and the power supply V_DDA capacitor 408 is provided between and.
[0006]
Here, it is assumed that the on-resistances of the n-type MOS transistors 403 and 407 are extremely small and negligible compared to the resistance value of the resistance element 401.
[0007]
In such a circuit, the bulk of the n-type MOS transistors 403 and 407 (the potential of the p-type well in which the transistors are formed) is supplied from the ground.
[0008]
The diodes 410 and 411 are diodes formed parasitically between the ground and the drains of the n-type MOS transistors 403 and 407.
[0009]
A connection point between the drain of the p-type MOS transistor 402 and the drain of the n-type MOS transistor 403 (the node at this connection point is N₄₁) Is connected to one input terminal of an OR gate 409, and further connected to the drain of the p-type MOS transistor 406 and the drain of the n-type MOS transistor 407 (the node at this connection is N₄₂) Is connected to the other input terminal of the OR gate 409.
[0010]
According to such a configuration, when the clock signal CLK input from the outside is oscillating (that is, when the high level and the low level are alternately repeated), the node N₄₁, N₄₂Both become low level, and therefore, the oscillation state detection signal S output from the OR gate 409_OUT  Goes low. On the other hand, when the clock signal CLK is not oscillating (that is, when the clock signal CLK is fixed at the high level or the low level), the node N₄₁, N₄₂Is at a high level and the other is at a low level, so that the oscillation state detection signal S_OUT  Becomes high level.
[0011]
This is based on the following circuit operation.
[0012]
When the clock signal CLK changes from the high level to the low level, the p-type MOS transistor 402 changes from on to off, and the n-type MOS transistor 403 changes from off to on. Therefore, node N₄₁Is the power supply potential V_DDTo the ground potential (ie, low level). Here, the resistance value of the resistance element 401 is R₃₀₁  = 1 GΩ, and the on-resistance of the p-type MOS transistor 402 and the n-type MOS transistor 403 is R₃₀₂  = R₃₀₃  = 1 kΩ and the capacitance of the capacitor 404 is C = 10 pF, the node N₄₁Is the power supply potential V_DDThe time required to change from C to ground potential is C × R₃₀₃  And about 10 ns.
[0013]
On the other hand, when the clock signal CLK changes from a low level to a high level, the p-type MOS transistor 402 changes from off to on, and the n-type MOS transistor 403 changes from on to off. Thereby, the node N₄₁From the ground potential to the power supply potential V_DD(Ie, going to a high level). At this time, the node N₄₁Is from the ground potential to the power supply potential V_DDTime to change to C × R₃₀₁  And about 10 ms.
[0014]
On the other hand, assuming that the frequency of the clock signal CLK is, for example, 32 kHz, the p-type MOS transistor 402 and the n-type MOS transistor 403 repeatedly turn on / off about every 16 μs. Therefore, even if the clock signal CLK changes from low level to high level and the p-type MOS transistor 402 changes from off to on, the node N₄₁Is the power supply potential V from the ground potential_DDCan not rise to On the other hand, when the clock signal CLK changes from the high level to the low level and the p-type MOS transistor 402 is turned off from on, the node N₄₁Can reach ground potential. Therefore, the node N₄₁Maintain a value near the ground potential with almost no change. The value near the ground potential is recognized by the OR gate 409 as being at a low level.
[0015]
The signals input to the gates of p-type MOS transistor 406 and n-type MOS transistor 407 have the opposite phase to clock signal CLK, but are similar to those of p-type MOS transistor 402 and n-type MOS transistor 403. For some reason, node N₄₂Also maintain a low level.
[0016]
Therefore, the oscillation state detection signal output from the OR gate 409 becomes low level.
[0017]
On the other hand, when the oscillation of the clock signal CLK is stopped and fixed at the high level, the p-type MOS transistor 402 is turned on and the n-type MOS transistor 403 is turned off.₄₁Is the power supply potential V_DDIs maintained. In this case, the p-type MOS transistor 406 is turned off and the n-type MOS transistor 407 is turned on, so that the node N₄₂Are maintained at the ground potential. Therefore, the oscillation state detection signal S output from the OR gate 409_OUT  Becomes high level.
[0018]
Conversely, when the oscillation of the clock signal CLK is stopped and fixed at the low level, the p-type MOS transistor 402 is turned off and the n-type MOS transistor 403 is turned on.₄₁Are maintained at the ground potential. In this case, the p-type MOS transistor 406 is turned on and the n-type MOS transistor 407 is turned off.₄₂Is the power supply potential V_DDIs maintained. Therefore, the oscillation state detection signal S output from the OR gate 409_OUT  Becomes high level.
[0019]
For the above reasons, in the oscillation detection circuit shown in FIG. 4, when the clock signal CLK is oscillating, the oscillation state detection signal S_OUT  Becomes low level, and when the clock signal CLK is not oscillating, the oscillation state detection signal S_OUT  Becomes high level. That is, according to the oscillation detection circuit, the oscillation state detection signal S_OUT  The presence or absence of oscillation can be known from the output level of.
[0020]
However, the conventional oscillation detection circuit as shown in FIG._DD, There is a possibility that a malfunction may occur due to a diode parasitically formed in the n-type MOS transistors 403 and 407.
[0021]
That is, as shown in FIG. 4, parasitic diodes 410 and 411 are formed between the ground and the drains of the n-type MOS transistors 403 and 407. Further, these diodes 410 and 411 are formed in a state where the anode is connected to the ground and the cathode is connected to each drain of the n-type MOS transistors 403 and 407, respectively.
[0022]
Such diodes 410 and 411 are formed parasitically because a pn junction formed of a p-type well in which n-type MOS transistors 403 and 407 are formed and an n-type diffusion region as a drain operates as a diode. That's why. And, as shown in FIG. 4, since the bulk electrodes of the n-type MOS transistors 403 and 407 are connected to the ground potential side, the diodes 410 and 411 are connected between the drains of the n-type MOS transistors 403 and 407 and the ground. To be formed.
[0023]
In the circuit configuration as shown in FIG._DDN when variation occurs in₄₁Are shown in FIG.
[0024]
When the p-type MOS transistor 402 is on and the n-type MOS transistor 403 is off when the clock signal CLK is oscillating normally, noise having a waveform as shown in FIG._DDIs rapidly reduced (see reference symbol a in FIG. 5), the node N₄₁Also drops sharply. This is because the resistance of the resistance element 401 can be handled as a high impedance state since the resistance is on the order of giga ohms.₄₁This is because only the capacitor 404 can be handled between the power supply and the power supply. Therefore, as shown in FIG._DDIs very large, the node N₄₁May have a negative value. According to the study of the present inventor, this node N₄₁Drops to, for example, about -3V. And in this way node N₄₁When the potential of the node N becomes a negative value, the node N₄₁, A forward current flows. Then, the node N₄₁Is discharged. Therefore, the power supply potential V_DDRises rapidly (see the symbol b in FIG. 5), the node N₄₁Also follows this and rises above the ground potential. Therefore, noise is eliminated and the power supply potential V_DDIs stable at the original value,₄₁Is stabilized at a potential higher than the ground potential (see reference numeral c in FIG. 5). And the node N at this time₄₁Is higher than the threshold voltage of the OR gate 409, the oscillation detection circuit malfunctions.
[0025]
Node N₄₂, A similar malfunction may occur due to the diode 411.
[0026]
As described above, according to the study of the present inventors, the parasitic diodes 410 and 411 may cause a malfunction of the oscillation detection circuit. Therefore, a technique for eliminating the influence of the diodes 410 and 411 is desired.
[0027]
[Means for Solving the Problems]
(1) An oscillation detection circuit according to a first aspect of the invention relates to an oscillation detection circuit including at least a detection unit that outputs a detection signal when a clock signal input from the outside stops at one of a high level and a low level. It is.
[0028]
The detection unit includes a first transistor of a first conductivity type, in which the control electrode receives a clock signal and the first main electrode is connected to a first power supply via a resistance element, and one end includes a first transistor. A capacitor connected to the first power supply and having the other end connected to the second main electrode of the first transistor; a control electrode receiving a clock signal; and the first main electrode being connected to the second power supply. A second transistor of a second conductivity type connected and having a bulk electrode connected to one of the first main electrode and the second main electrode; a control electrode receiving a clock signal; Are connected to the second main electrode of the second transistor, the second main electrode is connected to the second main electrode of the first transistor, and the bulk electrode is connected to the first main electrode or the second main electrode. A second transistor of a second conductivity type connected to the other of the electrodes. And butterflies.
[0029]
Thus, the influence of the diode parasitically formed on one of the second transistor and the third transistor is removed by the diode parasitically formed on the other transistor, and the malfunction of the oscillation detection circuit is reduced. Can be prevented.
[0030]
(2) An oscillation detection circuit according to a second aspect of the present invention includes: a first detection unit that outputs a first detection signal when a clock signal input from the outside stops at one of a high level and a low level; A second detection unit that outputs a second detection signal when the signal is stopped at the other of the high level and the low level, and oscillates externally when the first detection signal or the second detection signal is input The present invention relates to an oscillation detection circuit including a determination unit that outputs a detection signal.
[0031]
Then, the first detection unit is configured to input a clock signal to the control electrode and to connect the first main electrode to the first power supply via the first resistive element. A transistor, a capacitive element having one end connected to the first power supply and the other end connected to the second main electrode of the first transistor, a control electrode receiving a clock signal, and a first main electrode Are connected to a second power supply, and a second transistor of a second conductivity type whose bulk electrode is connected to one of the first main electrode and the second main electrode; and a control electrode receives a clock signal. , The first main electrode is connected to the second main electrode of the second transistor, the second main electrode is connected to the second main electrode of the first transistor, and the bulk electrode is connected to the first main electrode. A second transistor of the second conductivity type connected to the other of the electrode or the second main electrode. For example,
A second detection unit configured to input a clock signal and output an inverted clock signal; an inverting gate configured to input an inverted clock signal to the control electrode; A fourth transistor of the first conductivity type connected to the first power supply; a capacitive element having one end connected to the first power supply and the other end connected to the second main electrode of the fourth transistor; A control electrode receives an inverted clock signal, a first main electrode is connected to a second power supply, and a bulk electrode is connected to one of the first main electrode and the second main electrode. A fifth transistor, a control electrode receiving an inverted clock signal, a first main electrode being connected to a second main electrode of the fifth transistor, and a second main electrode being connected to the fourth transistor of the fourth transistor. 2 and the bulk electrode is connected to the first main electrode or the first main electrode. And a sixth transistor of the second conductivity type connected to the other second main electrode
It is characterized by having.
[0032]
Thus, the effect of the diode parasitically formed on one of the second transistor or the third transistor is removed by the diode parasitically formed on the other transistor, and further, the fifth transistor or the third transistor is eliminated. The effect of the diode parasitically formed on one of the six transistors can be removed by the diode parasitically formed on the other transistor, thereby preventing malfunction of the oscillation detection circuit.
[0033]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the size, shape, and arrangement relationship of each component are only schematically shown to the extent that the present invention can be understood, and the numerical conditions described below are merely examples. Please understand that.
[0034]
First embodiment
First, a first embodiment of the present invention will be described with reference to FIG.
[0035]
FIG. 1 is an electric circuit diagram showing a configuration of the oscillation detection circuit according to this embodiment.
[0036]
As shown in the figure, the oscillation detection circuit includes a first detection unit 110, a second detection unit 120, and a determination unit 130.
[0037]
The first detection unit 110 has a resistance element 111 (this resistance element 111 is also used as a resistance element of the second detection unit 120). As the resistance element 111, a high resistance element having a resistance value on the order of giga ohms is used._DDIt is connected to the. The p-type MOS transistor 112 (corresponding to the “first transistor” of the present invention) receives the clock signal CLK from the gate, and has the source connected to the other end of the resistance element 111. The n-type MOS transistor 113 (corresponding to the "second transistor" of the present invention) receives a clock signal CLK from a gate and has a source grounded. The n-type MOS transistor 114 (corresponding to the “third transistor” of the present invention) receives the clock signal CLK from the gate, has the source connected to the drain of the n-type MOS transistor 113, and has the drain connected to the p-type MOS transistor 113. It is connected to the drain of the transistor 112. Further, the drain of the p-type MOS transistor 112 and the power supply V_DDA capacitor 115 is provided between the two.
[0038]
In the first detection unit 110, the bulk of the n-type MOS transistor 113 (the potential of the p-type well in which the transistor is formed) is supplied from the source of the n-type MOS transistor 113 (therefore, ground). . On the other hand, the bulk of the n-type MOS transistor 114 is supplied from the drain of the n-type MOS transistor 114. Thus, a diode 116 whose anode is grounded is connected between the drain of the n-type MOS transistor 114 and the ground, a cathode is connected to the cathode of the diode 116, and the anode is connected to the drain of the n-type MOS transistor 114. Diode 117 is formed parasitically. Note that, of these diodes 116 and 117, the diode 116 is formed between the n-type diffusion region serving as the drain of the n-type MOS transistor 113 and the p-type well, and the diode 117 is the drain of the n-type MOS transistor 114. Formed between the n-type diffusion region and the p-type well.
[0039]
As described above, the second detection unit 120 uses the resistance element 111 of the first detection unit 110 as a resistance element. The inversion gate 121 outputs a signal obtained by inverting the clock signal CLK input from the outside (hereinafter, referred to as an inverted clock signal / CLK). The p-type MOS transistor 122 (corresponding to the “fourth transistor” of the present invention) receives the inverted clock signal / CLK from the gate, and has the source connected to the other end of the resistance element 111. The n-type MOS transistor 123 (corresponding to the “fifth transistor” of the present invention) receives the inverted clock signal / CLK from the gate and has the source grounded. An n-type MOS transistor 124 (corresponding to a “sixth transistor” of the present invention) receives an inverted clock signal / CLK from a gate, has a source connected to the drain of the n-type MOS transistor 123, and has a drain It is connected to the drain of the type MOS transistor 122. Further, the drain of the p-type MOS transistor 122 and the power supply V_DDA capacitor 125 is provided between the two.
[0040]
In the second detector 120, the bulk of the n-type MOS transistor 123 (the potential of the p-type well in which the transistor is formed) is supplied from the source of the n-type MOS transistor 123 (therefore, ground). . On the other hand, the bulk of the n-type MOS transistor 124 is supplied from the drain of the n-type MOS transistor 124. As a result, a diode 126 whose anode is grounded is connected between the drain of the n-type MOS transistor 124 and the ground, a cathode is connected to the cathode of the diode 126, and the anode is connected to the drain of the n-type MOS transistor 124. Diode 127 is formed parasitically. Of these diodes 126 and 127, diode 126 is formed between the n-type diffusion region serving as the drain of n-type MOS transistor 123 and the p-type well, and diode 127 is the drain of n-type MOS transistor 124. Formed between the n-type diffusion region and the p-type well.
[0041]
The determination unit 130 is configured by an OR gate 131. Here, one input terminal of the OR gate 131 has a connection point between the drain of the p-type MOS transistor 112 and the drain of the n-type MOS transistor 114 (the node at this connection point is N₁₁Is connected). On the other hand, the other input terminal of the OR gate 131 has a connection point between the drain of the p-type MOS transistor 122 and the drain of the n-type MOS transistor 124 (the node at this connection point is N₁₂Is connected).
[0042]
In the oscillation detection circuit having such a configuration, the principle of detecting the stop of the oscillation is substantially the same as that of the conventional case (see FIG. 4), and thus the description thereof is omitted. In this operation, the n-type MOS transistors 113 and 114 are always turned on / off simultaneously. Further, the n-type MOS transistors 123 and 124 are always turned on / off at the same time.
[0043]
In this embodiment, the oscillation detection circuit is provided with new n-type MOS transistors 114 and 124, and the bulk of these n-type MOS transistors 114 and 124 is connected to a node N.₁₁, N₁₂By taking it on the side, the diodes 117 and 127 are parasitically generated, thereby preventing malfunction of the oscillation detection circuit.
[0044]
Hereinafter, the reason why a malfunction of the oscillation detection circuit can be prevented by such a configuration will be described with reference to FIG.
[0045]
FIG. 2 shows that in the circuit configuration as shown in FIG._DDN when variation occurs in₁₁It shows the change of
[0046]
When the clock signal CLK is oscillating normally and the p-type MOS transistor 112 is on and the n-type MOS transistors 113 and 114 are off, noise having a waveform as shown in FIG. Potential V_DDIs rapidly reduced (see reference symbol a in FIG. 2), the node N has the same reason as in the conventional case (see FIG. 5).₁₁Also follows this. Therefore, as shown in FIG._DDIs very large, the node N₁₁May have a negative value.
[0047]
Here, in the oscillation detection circuit according to this embodiment, of the diodes 116 and 117 formed parasitically, the diode 117 is connected in the opposite direction. As a breakdown voltage of the diode 117, for example, about 10V can be obtained. Therefore, a potential difference larger than the sum of the breakdown voltage of diode 117 and the forward voltage of diode 116 (about 0.6 V in a silicon chip) is applied to ground and node N.₁₁(Ie, here node N₁₁Node -10.6V or less), node N₁₁Is negative from the ground even if the potential of₁₁No current flows into the device.
[0048]
Therefore, noise is eliminated and the power supply potential V_DDIs stable at the original value, the node N₁₁Is stabilized at the original ground potential (see reference numeral c in FIG. 2).
[0049]
For this reason, node N₁₁Does not become higher than the threshold voltage of the OR gate 131, and the oscillation detection circuit does not malfunction.
[0050]
Node N₁₂Also for node N₁₁As in the case of, malfunction can be prevented by providing the diode 127.
[0051]
As described above, according to the oscillation detection circuit of this embodiment, the influence of the parasitic diodes 116 and 126 can be eliminated by intentionally providing the parasitic diodes 117 and 127. Thus, malfunction of the oscillation detection circuit can be prevented.
[0052]
Second embodiment
Next, an oscillation detection circuit according to a second embodiment of the present invention will be described.
[0053]
FIG. 3 is an electric circuit diagram showing a configuration of the oscillation detection circuit according to this embodiment. In the figure, the components denoted by the same reference numerals as in FIG. 1 indicate the same components as those in FIG.
[0054]
The oscillation detection circuit according to this embodiment differs from the first embodiment in the manner of taking the bulk of the n-type MOS transistors 313, 314, 323, and 324.
[0055]
That is, the bulk of the n-type MOS transistor 313 (the potential of the p-type well in which the transistor is formed) is supplied from the drain of the n-type MOS transistor 313. On the other hand, the bulk of the n-type MOS transistor 314 is supplied from the source of the n-type MOS transistor 314. Thus, a diode 316 whose cathode is grounded is connected between the drain of the n-type MOS transistor 314 and the ground, an anode is connected to the anode of the diode 316, and the cathode is connected to the drain of the n-type MOS transistor 314. Diode 317 is formed parasitically.
[0056]
Similarly, the bulk of the n-type MOS transistor 323 (the potential of the p-type well in which the transistor is formed) is supplied from the drain of the n-type MOS transistor 323. On the other hand, the bulk of the n-type MOS transistor 324 is supplied from the source of the n-type MOS transistor 324. Thus, a diode 326 whose cathode is grounded is connected between the drain of the n-type MOS transistor 324 and the ground, an anode is connected to the anode of the diode 326, and the cathode is connected to the drain of the n-type MOS transistor 324. Diode 327 is parasitically formed.
[0057]
Also in the oscillation detection circuit according to this embodiment, of the diodes 316 and 317 formed parasitically, the diode 316 is connected in the opposite direction. As the breakdown voltage of the diode 316, for example, about 10 V can be obtained as in the case of the first embodiment. Therefore, a potential difference (here, -10.6 V) larger than the sum of the breakdown voltage of the diode 316 and the forward voltage (about 0.6 V in a silicon chip) of the diode 317 is applied to the ground and the node N.₁₁Unless it occurs between₁₁Is negative from the ground even if the potential of₁₁No current flows into the device.
[0058]
Therefore, the power supply voltage V_DDIs lowered from the ground to the node N₁₁Does not flow into the power supply voltage V, as shown by reference numeral c in FIG._DDIs stable when node N₁₁Is also stabilized at the ground potential. Thereby, the node N₁₁Does not become higher than the threshold voltage of the OR gate 131, and the oscillation detection circuit does not malfunction.
[0059]
Node N₁₂Also for node N₁₁As in the case of, malfunction can be prevented by providing the diode 326.
[0060]
As described above, also in the oscillation detection circuit according to this embodiment, by providing the parasitic diodes 316 and 326 intentionally, exactly the same effect can be obtained according to the same principle as in the above-described first embodiment. be able to.
[0061]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to eliminate the influence of a parasitic diode formed in a transistor, thereby preventing a malfunction of the oscillation detection circuit.
[Brief description of the drawings]
FIG. 1 is an electric circuit diagram showing a configuration of an oscillation detection circuit according to a first embodiment.
FIG. 2 is a diagram for explaining an operation of the oscillation stop circuit according to the first embodiment.
FIG. 3 is an electric circuit diagram illustrating a configuration of an oscillation detection circuit according to a second embodiment.
FIG. 4 is an electric circuit diagram showing a configuration of a conventional oscillation detection circuit.
FIG. 5 is a diagram for explaining an operation of a conventional oscillation stop circuit.
[Explanation of symbols]
110 first detector
111 resistance element
112 p-type MOS transistor
113,114 n-type MOS transistor
115 Capacitor
116,117 Diode
120 second detector
121 inversion gate
122 p-type MOS transistor
123, 124 n-type MOS transistors
125 capacitor
126,127 Diode
130 Judgment unit
131 OR gate

Claims (8)

In an oscillation detection circuit including at least a detection unit that outputs a detection signal according to an oscillation state of a signal input from the outside, the detection unit includes:
A first transistor of a first conductivity type, a control electrode receiving the clock signal, and a first main electrode connected to a first power supply via a resistance element;
A capacitor having one end connected to the first power supply and the other end connected to a second main electrode of the first transistor;
A second conductive electrode having a control electrode inputting the clock signal, a first main electrode connected to a second power supply, and a bulk electrode connected to one of the first main electrode or the second main electrode; A second transistor of type
A control electrode inputs the clock signal, a first main electrode is connected to a second main electrode of the second transistor, and a second main electrode is connected to the second main electrode of the first transistor. A third transistor of a second conductivity type, connected and having a bulk electrode connected to the other of the first main electrode or the second main electrode;
An oscillation detection circuit comprising: 2. The oscillation detection circuit according to claim 1, wherein the second power supply is a ground. 3. The oscillation detection circuit according to claim 1, wherein the first to third transistors are MOS transistors. A first detection unit that outputs a first detection signal when a clock signal input from the outside stops at one of a high level and a low level, and a case where the clock signal stops at the other of a high level and a low level A second detection unit that outputs a second detection signal, and a determination unit that outputs an oscillation state detection signal to the outside when the first detection signal or the second detection signal is input. In the oscillation detection circuit,
The first detection unit includes a first conductive type first electrode in which a control electrode receives the clock signal and a first main electrode is connected to a first power supply via a first resistive element. A transistor, a capacitive element having one end connected to the first power supply, and the other end connected to a second main electrode of the first transistor, and a control electrode receiving the clock signal; A second transistor of a second conductivity type having a main electrode connected to a second power supply and a bulk electrode connected to one of the first main electrode or the second main electrode; Inputting the clock signal, a first main electrode is connected to a second main electrode of the second transistor, a second main electrode is connected to the second main electrode of the first transistor, And a bulk electrode is provided on the other of the first main electrode and the second main electrode. And a third transistor of a second conductivity type continued,
The second detection unit receives the clock signal and outputs an inverted clock signal, an inverting gate that inputs the inverted clock signal, a control electrode that inputs the inverted clock signal, and a first main electrode that connects the second resistive element. A fourth transistor of a first conductivity type connected to the first power supply via the first power supply, and one end connected to the first power supply and the other end connected to a second main electrode of the fourth transistor. A connected capacitor element and a control electrode input the inverted clock signal, a first main electrode is connected to the second power supply, and a bulk electrode is the first main electrode or the second main electrode. A fifth transistor of a second conductivity type connected to one of the electrodes, a control electrode receiving the inverted clock signal, and a first main electrode connected to the second main electrode of the fifth transistor; , The second main electrode being in front of the fourth transistor A sixth transistor of a second conductivity type connected to a second main electrode and having a bulk electrode connected to the other of the first main electrode or the second main electrode. Oscillation detection circuit. The determination unit includes an OR gate having one input terminal connected to the second main electrode of the first transistor and the other input terminal connected to the second main electrode of the fourth transistor. 5. The oscillation detection circuit according to claim 4, wherein: The oscillation detection circuit according to claim 4, wherein one resistance element is shared as the first resistance element and the second resistance element. 7. The oscillation detection circuit according to claim 4, wherein the second power supply is a ground. 8. The oscillation detection circuit according to claim 4, wherein said first to sixth transistors are MOS transistors.

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