JP3553196B2 - Method for manufacturing SOI substrate - Google Patents
Method for manufacturing SOI substrate Download PDFInfo
- Publication number
- JP3553196B2 JP3553196B2 JP10990895A JP10990895A JP3553196B2 JP 3553196 B2 JP3553196 B2 JP 3553196B2 JP 10990895 A JP10990895 A JP 10990895A JP 10990895 A JP10990895 A JP 10990895A JP 3553196 B2 JP3553196 B2 JP 3553196B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- active substrate
- bonded
- active
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 title claims description 99
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 238000000034 method Methods 0.000 title claims description 15
- 235000012431 wafers Nutrition 0.000 claims description 40
- 238000005498 polishing Methods 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 12
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 230000000694 effects Effects 0.000 description 4
- 230000002411 adverse Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000000994 depressogenic effect Effects 0.000 description 1
Images
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
- Weting (AREA)
Description
【0001】
【産業上の利用分野】
本発明は、活性基板となる半導体ウェハと支持基板となる半導体ウェハを貼り合わせて得られるSOI基板の製造方法に関するものである。
【0002】
【従来の技術】
近年、集積回路の開発技術が向上するにともない、デバイス工程からのSOI基板製造における品質向上の要求は厳しくなる一方である。特に、集積回路の作動速度の高速化を図るために、活性層を可能な限り薄膜化させる必要がある。
従来、活性基板となる半導体ウェハと支持基板となる半導体ウェハを貼り合わせて得られるSOI基板は次の工程により製造されている。
(1)支持基板となる半導体ウェハの表面に酸化膜を発生させ、その上面に活性基板となる半導体ウェハを貼り合わせ、さらにこの活性基板の表面にも酸化膜を発生させて貼合ウェハを得る。
(2)次に、この貼り合せウェハの周縁部の未接着部分を研削またはエッチングにより除去する。
(3)活性基板の表面を平面研削し、その厚みを減らす。
(4)支持基板の裏面を貼付ブロックに貼り付けて活性基板の表面を研磨し、活性基板をさらに薄くする。
ところが、この研磨によって薄くされた活性基板はその厚さが2〜3μm程度であり、高速集積回路の製造に使用されるSOI基板においては、活性基板の厚さを0.1μm程度まで薄膜化させることが要求される。この薄膜化にはPACE加工を使用している。すなわち、上記した方法により研磨された活性基板の表面をこのPACE加工により均一に薄膜化するものである。
【0003】
【発明が解決しようとする課題】
しかしながら、このように活性基板を貼り付け研磨した後にPACE加工する方法では、研磨のために支持基板の裏面を貼付ブロックに貼り付けるため、貼付ブロックの貼付面と支持基板の裏面の間に異物や凹みがあると、研磨後の活性基板の表面に微小な凹凸が発生する。
例えば、貼付ブロック4の貼付面に異物5があった場合〔図2(a)〕、この貼付面に支持基板1aを貼り付けると、支持基板1aの裏面に異物5による凹み5aが発生し、この凹み5aはさらに支持基板1aの上面を介して酸化膜3aと活性基板2aにもおよび、このままの状態で活性基板2aの上面を研磨されることとなり、活性基板2aに極薄部分5bが発生する〔図2(b)〕。研磨終了後に、貼付ブロック4から剥がし、ワックス4aを除去すると、支持基板1aは元の状態に戻り、これにより活性基板2aの極薄部分5bは凹んだ状態で残存することとなる〔図2(c)〕。
また、支持基板1bの裏面に凹み6があった場合〔図3(a)〕、この支持基板1bを貼付ブロック4に貼り付けて研磨すると、酸化膜3bと活性基板2bの凹み6に対応する部分がこの研磨圧により窪んだまま研磨され、この部分が極厚部分6aとなる〔図3(b)〕。研磨終了後に、貼付ブロック4から剥がしてワックス4aを除去すると、支持基板1bは元の状態に戻り、これにより極厚部分6aは活性基板2bの表面に突出した状態で残存することとなる〔図3(c)〕。
ところが、上記したような微小な凹凸が活性基板の表面に局在した場合は、PACE加工を行っても平坦化することができず、均一な厚さの活性基板を得ることができないという問題がある。
本発明は、上記問題に鑑みなされたもので、均一に薄膜化された活性基板を有するSOI基板の製造方法を提供することを目的とするものである。
【0004】
【課題を解決するための手段】
このため本発明では、SOI基板の製造方法を、支持基板となる半導体ウェハの両面を両面研磨装置により同時に研磨し、両面研磨された支持基板の上面に活性基板となる半導体ウェハを貼り合わせて貼合ウェハを得、貼合ウェハの周縁部の未接着部分を取り除き、未接着部分を除去された貼合ウェハの活性基板の表面を平面研削して厚みを減じ、平面研削された活性基板の表面をスピンエッチングによりエッチングし、スピンエッチングされた活性基板をPACE加工により薄膜化するようにしたものである
また、SOI基板の製造方法を、支持基板となる半導体ウェハの両面を両面研磨装置により同時に研磨し、両面研磨された支持基板の上面に活性基板となる半導体ウェハを貼り合わせて貼合ウェハを得、貼合ウェハの周縁部の未接着部分を取り除き、未接着部分を除去された貼合ウェハの活性基板の表面を平面研削して厚みを減じ、平面研削された貼合ウェハを一枚ずつトップリングにより保持して活性基板を枚葉研磨し、枚葉研磨された活性基板をPACE加工により薄膜化するようにしたものである。
【0005】
【実施例】
以下、本発明の実施例を図面に基づいて説明する。
図1は本発明に係るSOI基板の製造方法の各工程における側面断面図、図2及び図3は従来技術の製造方法により製造されたSOI基板の側面断面図である。
【0006】
本実施例のSOI基板は次の方法に製造される。
(1)支持基板1となる半導体ウェハの両面を両面研磨装置により同時に研磨し、表裏面ともに平坦な半導体ウェハを得る〔図1(a)〕。この両面研磨された支持基板1の裏面には、最終工程である活性基板の薄膜化において悪影響を与える凹みなどの欠陥はない。
(2)両面研磨された支持基板1の表面に酸化膜3を発生させ、その上面に活性基板2となる半導体ウェハを貼り合わせ、さらに活性基板2にも酸化膜3を発生させ貼り合せウェハを得る〔図1(b)〕。
(3)貼合ウェハの周縁部の未接着部分を取り除き、活性基板2と支持基板1の間の酸化膜3以外の酸化膜を除去し、さらに活性基板2の上面を平面研削してその厚みを減ずる〔図1(c)〕。
(4)平面研削された活性基板2の表面をスピンエッチングによりエッチングし、活性基板2をさらに薄くする〔図1(d)〕。このスピンエッチングでの取り代は約10.0〜20.0μm程度で、その厚さムラは取り代に対して±5.0%以内であり、次の工程のPACE加工により除去できる厚さである。また従来技術の研磨レートが0.8μm/分であったのに対し、スピンエッチングによるエッチングレートは30μm/分と非常に速く、作業効率が著しく向上する。
(5)スピンエッチングされた活性基板1の表面をPACE加工により薄膜化する〔図1(e)〕。スピンエッチングで発生した厚さムラは従来技術の貼り付け研磨で発生していた小さい凹凸と違って滑らかであることから、PACE加工の分解能で十分処理できるので、活性基板1を均一に薄膜化することができる。また、このPACE加工で薄膜化された活性基板1における厚さムラは±10.0nm程度である。
【0007】
尚、上記実施例では、平面研削された活性基板2をスピンエッチングにより薄く加工していたが、これに限定されるものではなく、スピンエッチングに替わり平面研削された貼合ウェハを一枚ずつトップリングにより保持して、枚葉研磨されるものでもよい。この方法においても両面研磨された半導体ウェハが支持基板として使用されるため、枚葉研磨でその裏面の不具合による活性基板への悪影響を与えることがない。
【0008】
【発明の効果】
本発明では以上のように構成したので、PACE加工の前工程において発生する厚さムラを防止することができ、均一な薄膜化された活性基板を有するSOI基板を得られるという優れた効果がある。
また、両面研磨された半導体ウェハを支持基板として使用するため、その裏面には凹みなどの不具合は存在せず、活性基板の薄膜化において悪影響を与えることがないという優れた効果がある。
さらに、従来技術の貼り付け研磨に比較し、スピンエッチングはレートが速いため、生産効率が良いという優れた効果がある。
【図面の簡単な説明】
【図1】本発明に係るSOI基板の製造方法の各工程における側面断面図ある。
【図2】従来技術に製造方法により製造されたSOI基板の側面断面図である。
【図3】従来技術に製造方法により製造されたSOI基板の側面断面図である。
【符号の説明】
1 支持基板
1a 支持基板
1b 支持基板
2 活性基板
2a 活性基板
2b 活性基板
3 酸化膜
3a 酸化膜
3b 酸化膜
4 貼付ブロック
4a ワックス
5 異物
5a 凹み
5b 極薄部分
6 凹み
6a 極厚部分[0001]
[Industrial applications]
The present invention relates to a method for manufacturing an SOI substrate obtained by bonding a semiconductor wafer serving as an active substrate and a semiconductor wafer serving as a support substrate.
[0002]
[Prior art]
In recent years, as the development technology of integrated circuits has improved, the demand for quality improvement in SOI substrate manufacturing from device processes has been stricter. In particular, in order to increase the operating speed of the integrated circuit, it is necessary to make the active layer as thin as possible.
Conventionally, an SOI substrate obtained by bonding a semiconductor wafer serving as an active substrate and a semiconductor wafer serving as a support substrate has been manufactured by the following steps.
(1) An oxide film is generated on the surface of a semiconductor wafer serving as a support substrate, and a semiconductor wafer serving as an active substrate is bonded on the upper surface thereof. Further, an oxide film is also generated on the surface of the active substrate to obtain a bonded wafer. .
(2) Next, the unbonded portion at the periphery of the bonded wafer is removed by grinding or etching.
(3) The surface of the active substrate is ground to reduce its thickness.
(4) The back surface of the support substrate is attached to the attachment block, and the surface of the active substrate is polished to further reduce the thickness of the active substrate.
However, the active substrate thinned by this polishing has a thickness of about 2 to 3 μm. In an SOI substrate used for manufacturing a high-speed integrated circuit, the thickness of the active substrate is reduced to about 0.1 μm. Is required. PACE processing is used for this thinning. That is, the surface of the active substrate polished by the method described above is uniformly thinned by the PACE processing.
[0003]
[Problems to be solved by the invention]
However, in the method of performing PACE processing after attaching and polishing the active substrate in this way, since the back surface of the support substrate is attached to the attachment block for polishing, there is no foreign matter or foreign matter between the attachment surface of the attachment block and the back surface of the support substrate. If there is a dent, minute irregularities occur on the surface of the active substrate after polishing.
For example, when there is a
Also, when there is a
However, when the fine irregularities as described above are localized on the surface of the active substrate, there is a problem that even if PACE processing is performed, the surface cannot be flattened, and an active substrate having a uniform thickness cannot be obtained. is there.
The present invention has been made in view of the above problems, and has as its object to provide a method for manufacturing an SOI substrate having an active substrate uniformly thinned.
[0004]
[Means for Solving the Problems]
For this reason, in the present invention, the method for manufacturing an SOI substrate is based on a method in which both surfaces of a semiconductor wafer serving as a support substrate are simultaneously polished by a double-side polishing apparatus, and a semiconductor wafer serving as an active substrate is attached to the upper surface of the support substrate polished on both surfaces. The bonded wafer is obtained, the unbonded portion of the peripheral portion of the bonded wafer is removed, and the surface of the active substrate of the bonded wafer from which the unbonded portion is removed is reduced by surface grinding to reduce the thickness. Is spin-etched, and the spin-etched active substrate is thinned by PACE processing. Also, the method for manufacturing an SOI substrate is such that both surfaces of a semiconductor wafer serving as a support substrate are simultaneously polished by a double-side polishing apparatus. Then, a semiconductor wafer serving as an active substrate is bonded to the upper surface of the support substrate polished on both sides to obtain a bonded wafer, and the peripheral edge of the bonded wafer is not bonded. Then, the surface of the active substrate of the bonded wafer from which the unbonded portion has been removed is reduced by surface grinding to reduce the thickness, and the surface-ground bonded bonded wafers are held one by one by a top ring, and the active substrate is removed. The active substrate, which has been polished and polished, is thinned by PACE processing.
[0005]
【Example】
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a side sectional view showing each step of a method of manufacturing an SOI substrate according to the present invention, and FIGS. 2 and 3 are side sectional views of an SOI substrate manufactured by a conventional manufacturing method.
[0006]
The SOI substrate of this embodiment is manufactured by the following method.
(1) Both surfaces of a semiconductor wafer serving as a support substrate 1 are simultaneously polished by a double-side polishing apparatus to obtain a semiconductor wafer having flat front and back surfaces (FIG. 1A). On the back surface of the support substrate 1 polished on both sides, there is no defect such as a dent which adversely affects the thinning of the active substrate in the final step.
(2) An oxide film 3 is generated on the surface of the support substrate 1 which has been polished on both sides, and a semiconductor wafer to be the
(3) An unbonded portion at the peripheral edge of the bonded wafer is removed, an oxide film other than the oxide film 3 between the
(4) The surface of the
(5) The surface of the active substrate 1 that has been spin-etched is thinned by PACE processing (FIG. 1E). The thickness unevenness generated by the spin etching is smooth unlike the small unevenness generated by the pasting polishing of the prior art, so that it can be sufficiently processed with the resolution of the PACE processing, so that the active substrate 1 is uniformly thinned. be able to. The thickness unevenness of the active substrate 1 thinned by the PACE processing is about ± 10.0 nm.
[0007]
In the above embodiment, the
[0008]
【The invention's effect】
Since the present invention is configured as described above, it is possible to prevent thickness unevenness occurring in a pre-process of PACE processing, and to obtain an excellent effect of obtaining an SOI substrate having a uniform thinned active substrate. .
In addition, since a semiconductor wafer polished on both sides is used as a support substrate, there is no problem such as a dent on the back surface, and there is an excellent effect that it does not adversely affect the thinning of the active substrate.
Furthermore, since the rate of spin etching is higher than that of the conventional bonding polishing, there is an excellent effect that production efficiency is good.
[Brief description of the drawings]
FIG. 1 is a side sectional view showing each step of a method for manufacturing an SOI substrate according to the present invention.
FIG. 2 is a side sectional view of an SOI substrate manufactured by a conventional manufacturing method.
FIG. 3 is a side sectional view of an SOI substrate manufactured by a conventional manufacturing method.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1
Claims (2)
(1)支持基板となる半導体ウェハの両面を、両面研磨装置により同時に研磨する両面研磨工程。
(2)両面研磨された支持基板の上面に、活性基板となる半導体ウェハを貼り合わせて貼合ウェハを得る貼り合わせ工程。
(3)貼合ウェハの周縁部の未接着部分を取り除く未接着部除去工程。
(4)未接着部分を除去された貼合ウェハの活性基板の表面を、平面研削して厚みを減ずる平面研削工程。
(5)平面研削された活性基板の表面を、スピンエッチングによりエッチングするスピンエッチング工程。
(6)スピンエッチングされた活性基板を、PACE加工により薄膜化するPACE加工工程。A method for manufacturing an SOI substrate, comprising the following steps.
(1) A double-side polishing step of simultaneously polishing both surfaces of a semiconductor wafer as a support substrate by a double-side polishing apparatus.
(2) A bonding step in which a semiconductor wafer serving as an active substrate is bonded to the upper surface of the support substrate polished on both sides to obtain a bonded wafer.
(3) An unbonded portion removing step of removing an unbonded portion at a peripheral portion of the bonded wafer.
(4) A surface grinding step of reducing the thickness by surface grinding the surface of the active substrate of the bonded wafer from which the unbonded portion has been removed.
(5) A spin etching step of etching the surface of the active substrate that has been ground by spin etching.
(6) A PACE processing step of thinning the spin-etched active substrate by PACE processing.
(1)支持基板となる半導体ウェハの両面を、両面研磨装置により同時に研磨する両面研磨工程。
(2)両面研磨された支持基板の上面に、活性基板となる半導体ウェハを貼り合わせて貼合ウェハを得る貼り合わせ工程。
(3)貼合ウェハの周縁部の未接着部分を取り除く未接着部除去工程。
(4)未接着部分を除去された貼合ウェハの活性基板の表面を、平面研削して厚みを減ずる平面研削工程。
(5)平面研削された貼合ウェハを一枚ずつトップリングにより保持して、活性基板を研磨する枚葉研磨工程。
(6)枚葉研磨された活性基板を、PACE加工により薄膜化するPACE加工工程。A method for manufacturing an SOI substrate, comprising the following steps.
(1) A double-side polishing step of simultaneously polishing both surfaces of a semiconductor wafer as a support substrate by a double-side polishing apparatus.
(2) A bonding step in which a semiconductor wafer serving as an active substrate is bonded to the upper surface of the support substrate polished on both sides to obtain a bonded wafer.
(3) An unbonded portion removing step of removing an unbonded portion at a peripheral portion of the bonded wafer.
(4) A surface grinding step of reducing the thickness by surface grinding the surface of the active substrate of the bonded wafer from which the unbonded portion has been removed.
(5) A single wafer polishing step of holding the surface-ground bonded wafers one by one by a top ring and polishing the active substrate.
(6) A PACE processing step of thinning the active substrate polished by a single wafer by PACE processing.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10990895A JP3553196B2 (en) | 1995-03-29 | 1995-03-29 | Method for manufacturing SOI substrate |
| TW85103834A TW300318B (en) | 1995-03-29 | 1996-04-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10990895A JP3553196B2 (en) | 1995-03-29 | 1995-03-29 | Method for manufacturing SOI substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08274286A JPH08274286A (en) | 1996-10-18 |
| JP3553196B2 true JP3553196B2 (en) | 2004-08-11 |
Family
ID=14522207
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10990895A Expired - Lifetime JP3553196B2 (en) | 1995-03-29 | 1995-03-29 | Method for manufacturing SOI substrate |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP3553196B2 (en) |
| TW (1) | TW300318B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0964321A (en) * | 1995-08-24 | 1997-03-07 | Komatsu Electron Metals Co Ltd | Method for manufacturing SOI substrate |
| US6090688A (en) * | 1996-11-15 | 2000-07-18 | Komatsu Electronic Metals Co., Ltd. | Method for fabricating an SOI substrate |
| JP3672436B2 (en) | 1998-05-19 | 2005-07-20 | シャープ株式会社 | Method for manufacturing solar battery cell |
| JP3944087B2 (en) | 2003-01-21 | 2007-07-11 | 株式会社東芝 | Method for manufacturing element forming substrate |
| KR20110099108A (en) | 2008-11-19 | 2011-09-06 | 엠이엠씨 일렉트로닉 머티리얼즈, 인크. | Methods and Systems for Stripping Edges of Semiconductor Wafers |
| US8035962B2 (en) | 2010-03-03 | 2011-10-11 | Antec, Inc. | Computer hot-plug structure |
| JP7187115B2 (en) * | 2018-12-04 | 2022-12-12 | 株式会社ディスコ | Wafer processing method |
-
1995
- 1995-03-29 JP JP10990895A patent/JP3553196B2/en not_active Expired - Lifetime
-
1996
- 1996-04-02 TW TW85103834A patent/TW300318B/zh active
Also Published As
| Publication number | Publication date |
|---|---|
| TW300318B (en) | 1997-03-11 |
| JPH08274286A (en) | 1996-10-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3352896B2 (en) | Manufacturing method of bonded substrate | |
| EP0935280A1 (en) | SOI substrate and method of manufacturing the same | |
| US6090688A (en) | Method for fabricating an SOI substrate | |
| JPH0964321A (en) | Method for manufacturing SOI substrate | |
| JPH0636414B2 (en) | Manufacturing method of semiconductor element forming substrate | |
| JP2001326206A (en) | Method for thinning semiconductor wafer and thin semiconductor wafer | |
| JPH11219873A (en) | Improvement of mechanical resistance of single crystal silicon wafer | |
| JPH10223497A (en) | Method of manufacturing bonded substrate | |
| JP3553196B2 (en) | Method for manufacturing SOI substrate | |
| JP2662495B2 (en) | Method for manufacturing bonded semiconductor substrate | |
| JP3496925B2 (en) | Semiconductor substrate and manufacturing method thereof | |
| JPH0917984A (en) | Method for manufacturing bonded SOI substrate | |
| JPH08274285A (en) | SOI substrate and manufacturing method thereof | |
| JPH08107092A (en) | Manufacture of soi substrate | |
| JPH0897111A (en) | Method for manufacturing soi substrate | |
| JP2003151939A (en) | Method of manufacturing soi substrate | |
| JP3422225B2 (en) | Laminated semiconductor substrate and method of manufacturing the same | |
| CN110429022A (en) | Crystal back thinning method | |
| JP2001085453A (en) | Method of manufacturing semiconductor device | |
| JPH01302837A (en) | Manufacture of semiconductor substrate | |
| JP3798760B2 (en) | Method for forming semiconductor wafer | |
| JP3996557B2 (en) | Manufacturing method of semiconductor junction wafer | |
| JPH1187203A (en) | Substrate bonding method | |
| JPS62264864A (en) | Lapping method for substrate | |
| CN110429023A (en) | Crystal back thinning method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20040413 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20040428 |
|
| R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090514 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090514 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100514 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110514 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110514 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120514 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130514 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140514 Year of fee payment: 10 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| EXPY | Cancellation because of completion of term |