JP3553793B2 - Single event upset countermeasure data processing device and single event upset countermeasure processing method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a computer technology used in a field in which a single event upset (SEU) occurs in a data holding circuit due to radiation or the like, and is particularly used in a data processing device mounted on a satellite or in a nuclear reactor. The present invention relates to a single-event upset countermeasure data processing device and a single-event upset countermeasure processing method suitable for a data processing device to perform.
[0002]
[Prior art]
First, a single event upset (SEU) will be described. When radiation such as heavy particles existing in the space environment enters an LSI such as a CMOS or the like, inversion of data in a data holding circuit (memory, register, etc.), for example, in binary logic, “1 → 0” or “0 → 1” It is known to cause such an information inversion phenomenon. This inversion phenomenon is considered to be a transient soft error phenomenon because data is recovered by rewriting, and is called a single event upset (SEU).
[0003]
FIG. 4 is a diagram illustrating an example of a single event upset (SEU).
When heavy particles enter a cache memory (cache memory) 11 built in the CPU 1, the energy of radiation is charged, and the charge becomes a certain amount, thereby inverting information. In FIG. 4, se1 indicates an SEU error due to heavy particles. Although se1 is only in the cache memory 11 and is not reflected in the main memory (MEM: main memory) 2, when the cache memory 11 is of the store-through type, se2, which is an operation result calculated using se1, is This is reflected in the main memory 2.
[0004]
Conventionally, high speed was not required for a data processor mounted on a satellite, so a space CPU (low performance) was used, and a hardware circuit was added as necessary, so that space equipment could be used. The development was done. A CPU having a built-in cache memory in which a single event upset is likely to occur has not been used.
[0005]
However, recent satellites, especially scientific satellites, have been forced to deal with high-performance CPUs as mission demands for higher functionality and higher performance have increased. At present, there is no high-performance space CPU developed for space that has more than several tens of MIPS. In general, developing a space device requires enormous development costs, but developing a high-performance space CPU also requires enormous development costs. However, even if a high-performance space CPU is developed, there is a problem that the demand is small and enormous cost is required to maintain the production line.
[0006]
In view of such a conventional technical background, it is necessary to mount a data processing device having a high-performance CPU for consumer use on a satellite.
[0007]
[Problems to be solved by the invention]
A general consumer high-performance CPU has a built-in cache memory in a computer system to absorb a performance difference between the CPU and the main memory. On the other hand, a conventional data processor mounted on a satellite does not require a high speed, so that a CPU with a built-in cache is not used. When a CPU with a built-in cache memory is used in a data processing device mounted on a satellite for high performance, it is necessary to consider SEU measures for the cache memory and the main memory.
[0008]
Here, the main memory is usually provided with an EDAC (Error Detection And Correction: 1-bit error correction / 2-bit error detection mechanism), thereby implementing SEU measures. When an SEU occurs in the main memory by the EDAC, a one-bit error is corrected and a two-bit error is detected, so that no problem occurs. As a result, the main memory is not expected to be critical.
[0009]
On the other hand, the cache memory built in the CPU also has a relation of physical quantity and the like, and usually does not have an error correction / detection mechanism such as EDAC. For this reason, when used in a space radiation environment, the arithmetic processing may proceed without surface even if SEU occurs. This can lead to extremely critical situations, such as producing incorrect results.
[0010]
An object of the present invention is to realize a data processing device and an SEU measure method capable of dealing with SEU generated in a cache memory in a CPU. The invention allows the use of high performance consumer CPUs in space radiation environments.
[0011]
[Means for Solving the Problems]
FIG. 1 shows a configuration example of a data processing device of the present invention.
The data processing device 1 includes a CPU 10 having a built-in cache memory 11 and has a sequence control unit 12, a result storage unit 13, and a cache reset unit 15 as an instruction execution function of the CPU 10. Further, it has a result storage area 14 for storing a plurality of processing results in a main memory (not shown).
[0012]
The result storage unit 13 is a unit that stores the result of each execution of the program calculated by the CPU 10 in the result storage area 14 of the main memory. The sequence control unit 12 compares a plurality of execution results in the result storage area 14, and executes the next program if the execution results are equal, and executes the same program again if the execution results are not equal. Therefore, it is a means for controlling the program address to be executed. The cache reset unit 15 is a unit that resets the cache memory 11 before repeatedly executing the same program.
[0013]
The basic concept of the present invention is a two-time calculation method of a program. In other words, basically, the same program is executed twice, and when the execution results are equal, a method of proceeding to the execution of the next program is adopted. The process proceeds after the cache memory 11 at the start of the first calculation and at the start of the second calculation is initialized to the program to be executed. For this purpose, the cache memory 11 is reset at the start of each calculation after the second time.
[0014]
As a feature of the cache memory, if a program or the like to be executed exists in the cache memory, the cache memory is used to execute the program or the like. That is, by using the cache memory, the program and the like are not newly loaded from the main memory, thereby improving efficiency. However, when such a feature of the cache memory is used, in a method in which the program is calculated twice in the space radiation environment, the SEU generated in the cache memory at the time of the first calculation remains even at the time of the second calculation. , May affect the result of the second calculation. Therefore, by resetting (purging) the cache memory at the start of the second and subsequent calculations, it is possible to avoid such an influence of the SEU generated in the previous calculation.
[0015]
Further, the processing time of the program is sufficiently shorter than the frequency of occurrence of SEU in the cache memory. Therefore, when the program is calculated twice, the probability that an SEU will occur twice is very small.
[0016]
Therefore, when a program is calculated twice, the execution results are compared, and whether or not the calculation results are different is checked, it is possible to detect the occurrence of SEU in the cache. Further, since the process proceeds to the next process only when the calculation results are equal, a malfunction due to the occurrence of SEU can be avoided.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described.
FIG. 2 is a diagram for explaining processing and transition of the cache memory according to the embodiment of the present invention.
[0018]
In order to realize the present invention, the following processing is performed in a conventional program processing in which programs A, B, C,... Are sequentially processed.
First, the CPU 10 performs the first calculation of the program. At this time, the sequence control means 12 sets the address “ep-i” of the program A to be executed by the CPU 10. The program A is loaded from the main memory 2 to the cache memory 11 with the instruction fetch of the program A by the CPU 10. (1) and executed by the CPU 10. The calculation result (ans-A) is stored in the result storage area 14 of the main memory 2 by the result storage means 13.
[0019]
Here, it is assumed that an SEU has occurred in the cache memory 11 ((2)).
Next, the second calculation is performed for the program A, but before that, the cache memory 11 is reset once by the cache reset means 15 to bring it into the initial state ([3]). When the second calculation is started, the program A to be executed in the same manner as the first calculation does not exist in the cache memory 11, so that the program A is loaded from the main memory 2 to the cache memory 11 again ((4)), and the second calculation is performed. The calculation is performed, and the calculation result (ans-B) is stored in the result storage area 14.
[0020]
The sequence control means 12 compares the first calculation result (ans-A) and the second calculation result (ans-B) stored in the result storage area 14 ([5]). If the calculation results are equal, the address "ep-i + 1" of the program B is set to proceed to the next processing (program B). If the calculation results (ans-A, ans-B) are not equal, the cache memory 11 is reset to the initial state, and the address “ep-i” of the program A is reset. The third calculation is performed. If the third calculation result is equal to the first (ans-A) or second (ans-B) calculation result, the process proceeds to the next process (program B). ep-i + 1 "is set. If the calculation results are not equal, the same method is repeated several times, and if the calculation results are not equal even after repeating the predetermined number of times, it is processed as a CPU error.
[0021]
As described above, since the cache memory 11 is reset and returned to the initial state at the start of execution of the second calculation, even if SEU occurs in the cache memory 11, the second calculation is not affected by the SEU. .
[0022]
A program for implementing the sequence control means 12, the result storage means 13, and the cache reset means 15 in the present invention can be provided as a library program that can be combined with, for example, an application program. These means can be provided as a function of the operating system.
[0023]
FIG. 3 is a flowchart of a process according to the embodiment of the present invention.
First, the address of the program to be processed is set (S1), the program is executed (S2), and the execution result is stored in a predetermined result storage area 14 (S3). It is determined whether or not the execution is the first time (S4). If the execution is the first time, the cache memory 11 is reset (S7), the address of the currently executed program is reset (S8), and the process returns to the step S2. Advance.
[0024]
If the execution in step S4 is not the first execution, the new execution result stored in the result storage area 14 is compared with the previous execution result (S5). If the result is the same, no SEU has occurred, and the program moves to the next program execution. If the results are not the same, it is further determined whether or not the execution has been performed n times (n is a predetermined number of retries) (S6). If the execution has not been performed n times, the cache memory 11 is reset (S7) and the address is re-executed. It is set (S8), and the process returns to step S2 to proceed. If the execution result is not the same even after executing the predetermined number of retries n times, the error is considered to be an error other than SEU, and the process proceeds to error processing (S9).
[0025]
In order to evaluate the performance of the system using the present invention, the evaluation software is executed in a certain test system, and execution is performed when a cache memory is used (cache enable) and when the cache memory is not used (cache disable). Time comparisons were made.
[0026]
When the SRAM was used as the memory, the execution time ratio was 1 when the cache memory was used and 1 when the cache memory was not used. The execution time ratio between when the cache memory was used and when the cache memory was not used when the DRAM was used was 1: 7.
[0027]
In other words, the execution time in the cache disable state requires five times and seven times the execution time in the cache enable state when the memory is the SRAM and the DRAM, respectively. This indicates that even if the same program is executed twice or more, the use of the cache memory can be executed at a higher speed than the case where the cache memory is not used. Therefore, by taking measures against a single event upset using the present invention, it becomes possible to use a consumer high-performance CPU having a built-in cache memory, thereby improving the performance.
[0028]
In the case of a satellite device, an SRAM is used as a normal memory. This is because SRAM is generally superior in radiation resistance to DRAM.
[0029]
【The invention's effect】
As described above, according to the present invention, the SEU in the internal cache of the high-performance CPU can be avoided, and in the space radiation environment, a high-performance CPU for a consumer that is critical can be used in the space radiation environment. It can respond to demands for high performance and high functionality, and can avoid the cost burden associated with the development and maintenance of expensive space CPUs.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration example of a data processing device of the present invention.
FIG. 2 is a diagram showing a transition of processing and cache memory according to the embodiment of the present invention.
FIG. 3 is a flowchart of a process according to the embodiment of the present invention.
FIG. 4 is a diagram illustrating an example of a single event upset (SEU).
[Explanation of symbols]
1 data processing device 2 main memory (MEM)
10 CPU
11 cache memory 12 sequence control means 13 result storage means 14 result storage area 15 cache reset means

Claims (2)

In a data processing device having a CPU with a built-in cache memory,
Means for storing each execution result in a result storage area for storing a program execution result;
Executes the same program multiple times, compares multiple execution results in the result storage area, executes the next program if the execution results are equal, and executes the same program again if the execution results are not equal Sequence control means for controlling a program address to be executed,
Means for resetting the cache memory before repeatedly executing the same program. A single event upset countermeasure processing method for a cache memory in a data processing device having a CPU with a built-in cache memory,
The process of setting the address of the program that performs the desired processing and executing the program;
Storing a program execution result in a first result storage area;
Resetting the cache memory before repeatedly executing the same program;
Resetting the program address and executing the program;
Storing a program execution result in a second result storage area;
A plurality of execution results in the first and second result storage areas are compared, and if the execution results are equal, the process proceeds to the next program process; if the execution results are not equal, the same program execution process or Shifting to error processing.

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