JP3554763B2 - Chip package and manufacturing method thereof - Google Patents

Description

ボールパッド及びスルーホール部分には図５に示した Ｎｉ／Ａｕ層９が形成されていた。
【００４２】
Ｎｉ／Ａｕ層９の剥離試験：市販セロテープ（Ｒ）によるピールテストにて剥れなきと良好な値を得ることができた。
【図面の簡単な説明】
【図１】（ａ）〜（ｄ）は本発明の実施の形態（３）に係るフリップチップパッケージ
の製造工程の一部を示す断面図である。
【図２】（ａ）〜（ｄ）は本発明の実施の形態（３）に係るフリップチップパッケージ
の製造工程の一部を示す断面図である。
【図３】（ａ）〜（ｄ）は本発明の実施の形態（３）に係るフリップチップパッケージ
の製造工程の一部を示す断面図である。
【図４】（ａ）〜（ｄ）は本発明の実施の形態（３）に係るフリップチップパッケージ
の製造工程の一部を示す断面図である。
【図５】実施例に係る接合パッドに形成されたＮｉ／Ａｕ層を示す拡大断面図である。
【図６】従来のＰＢＧＡの一例を示す断面図である。
【図７】（ａ）は従来のめっき用引き出し線が形成されたＢＴ基板を示す平面図、（ｂ
）は断面図である。
【図８】従来の２層形放熱板付ＢＧＡの一例を示す断面図である。
【図９】ボールパッド近傍を拡大して示した断面図である。
【図１０】従来のフリップチップパッケージの一例を示す断面図である。
【図１１】ボールパッド近傍を拡大して示した断面図である。
【符号の説明】
１、１ａ 銅張積層板
２ 樹脂基板
３、３ａ 銅箔
４ スルーホール
６ Ｃｕ層
７ Ｃｕ板
７ａ 接着シート
８ ＤＦＲ
９ Ｎｉ／Ａｕ層
１０ 配線パターン（パッド含む）
４３ ソルダマスク[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a chip package and a method of manufacturing the same. More specifically, the present invention includes a package called a BGA package or a flip chip package, and is mainly used as a chip mounting package such as an LSI chip. The present invention relates to a type of chip package having a wiring pattern and a ball pad formed by etching a metal layer on both surfaces, and a method of manufacturing the same.
[0002]
[Prior art]
In response to demands for higher density and higher speed in semiconductor devices, BGAs (Ball Grid Arrays), flip chip packages, and the like, which can have multiple terminals, have recently attracted attention. The BGA is most suitable for mounting an IC such as a microprocessor or an ASIC that requires a large number of terminals, and has the following features.
[0003]
(A) Since the balls are arranged two-dimensionally, the number of terminals can be significantly increased compared to a mounting technology using a lead frame such as a QFP (Quad Flat Package), and the number of terminals is further increased compared to a PGA (Pin Grid Array). Multiple terminals are possible.
[0004]
(B) The lead pitch is larger than the QFP, so that the accuracy of the mounter or the like may be low, and the mounting yield is improved.
[0005]
(C) The cost is relatively low.
[0006]
(D) Excellent heat dissipation and low impedance.
[0007]
Until recently, ceramic BGAs have attracted attention from the viewpoint of reliability among BGAs, but the focus has shifted to plastic array packages from the viewpoint of cost reduction. If this kind of plastic array package is widely interpreted, there are PBGA (Plastic BGA), TBGA (Tape BGA), μ-BGA, CSP (Chip Size Package, Chip Scale Package) and the like.
[0008]
FIG. 6 shows an example of the PBGA. A wiring pattern 13 is formed on the surface of the resin substrate 12 on which the IC chip 11 is mounted, and a large number of ball pads 14 are formed on the other surface. These ball pads 14 and the wiring pattern 13 are connected via through holes 16 for wiring. The lower surface of the IC chip 11 is connected to ball pads 14 via through holes 17 for heat radiation, and solder balls 15 are welded onto the ball pads 14. The wiring pattern 13 is connected to a pad (not shown) formed on the IC chip 11 via a bonding pad 13a and a wire bonder 18. Then, a portion including the IC chip 11, the wire bonder 18, and most of the wiring pattern 13 is covered with a mold resin 19.
[0009]
The bonding pad 13a and the ball pad 14 are usually subjected to Ni / Au plating (not shown) in order to improve the bonding property and the welding property of the solder ball 15, and a wiring for electrolytic plating for this purpose is provided, for example. It is formed as shown in FIG. Each bonding pad 13a and ball pad 14 (FIG. 6 ) are connected to a tie bar 21 via a lead wire 20 for plating, and after plating, are cut at a cut line 22 to constitute each device. Portions that do not require plating are covered with a solder mask 23 before plating.
[0010]
8 and 9 show an example of a BGA with a heat sink. BT (Bismaleimide Triazine) is used for forming the thin tape-shaped resin substrate 32. BT resin is widely used in LSI packages because it has a heat distortion temperature (300 ° C.) substantially equal to that of polyimide resin, and has better adhesiveness to copper foil and processability than polyimide resin. A wiring pattern (not shown) formed by etching a copper foil and a ball pad 34 are formed on the lower surface of the resin substrate 32, and the solder balls 15 are welded to the ball pad 34. A copper ring 33 having a cavity 35 for accommodating the IC chip 11 is attached to the upper surface of the resin substrate 32, and a copper heat spreader 38 is attached to the upper surface of the copper ring 33 via an adhesive sheet 38a. I have. A dam 36 is formed at the center of the resin substrate 32 so as to surround the cavity 35. After the wire bonder 18 is connected, a casting resin 39 is injected into the cavity 35 and solidified. The ball pad 34 and the bonding pad (not shown) are composed of a copper layer 34a and a Ni / Au layer 34b as shown in FIG. 9 , and a solder mask 43 is formed around the Ni / Au layer 34b.
[0011]
In the case of the BGA with a heat sink of the type shown in FIG. 8, it is difficult to arrange the lead wires 20 for plating as shown in FIG. 7 from the viewpoint of space. Therefore, the Ni / Au layer 34b is formed by an electroless plating method. The plating lead wire 20 and the tie bar 21 as shown in FIG. 7 are not formed during the manufacturing process.
[0012]
FIGS. 10 and 11 show an example of a conventional flip chip package in which a semiconductor element is mounted by flip chip bonding. A wiring pattern 13 and ball pads 14a are formed on the mounting surface of the chip 11 of the resin substrate 12, and a large number of ball pads 14b are formed on the other surface. These ball pads 14b and wiring patterns 13 are used for wiring. The ball pad 14a on the lower surface of the chip 11 is connected to a ball pad 14b through a heat dissipation through hole 17, and a solder ball 15 is placed on the ball pad 14b. Welded. The wiring pattern 13 is connected to the chip 11 via a solder ball 15 welded on the ball pad 14a. A space between the chip 11 and the resin substrate 12 is filled with a mold resin 19. Matabo - Le Pad 14a, solder mask 23 is formed in a portion of the wiring patterns 13 excluding 14b, ball - Le Pad 14a, 14b is copper layer 34a as shown in FIG. 11, taken from the Ni / Au layer 34b The solder mask 23 is formed around the Ni / Au layer 34b.
[0013]
The formation of the Ni / Au layer 34b of the flip chip package as shown in FIGS. 10 and 11 is performed not by electrolytic plating but by electroless plating. This is because flip-chip packages often have high-density wiring, and it is difficult to form lead wires for electrolytic plating between the high-density wiring.
[0014]
[Problems to be solved by the invention]
In the case of a PBGA of the type shown in FIGS. 6 and 7 , many plating lead wires 20 and tie bars 21 connected to each bonding pad 13a and ball pad 14 must be formed in order to perform electrolytic plating. And the wiring patterns 13 and the ball pads 14 are hindered from increasing in density. Also, after plating, the plating lead 20 inside the cut line 22 remains, and these may become sources of reflection noise and adversely affect the electrical characteristics.
[0015]
On the other hand, in the case of the BGA with a heat sink of the type shown in FIGS. 8 and 9 , since the electroless plating method is used, the formation of the lead wire 20 for the plating and the tie bar 21 is unnecessary, and the above-described problems related to the increase in the density of the wiring and the like. However, there was a problem that the bonding strength of the solder ball 15 to the ball pad 34 was low, and the solder ball 15 was likely to be unstable.
[0016]
Also in the case of the type of flip-chip package shown in FIGS. 10 and 11, as in the case of the type of radiating fitted with BGA shown in FIGS. 8 and 9, since by electroless plating, for plating lead wire 20 and the tie bar The formation of 21 is unnecessary, and the above-mentioned problems related to the increase in the wiring density and the like have been eliminated, but there has been a problem that the bonding strength of the solder balls 15 to the ball pads 14a and 14b is low and the solder balls 15 tend to be unstable.
[0017]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and achieves high density by performing plating by an electrolytic plating method to secure the bonding strength of a solder ball to a pad and eliminate the need for forming a lead wire for plating. It is another object of the present invention to provide a chip package capable of improving electrical characteristics and a method of manufacturing the same.
[0018]
Means for Solving the Problems and Their Effects
In order to achieve the above object, a method (1) for manufacturing a chip package according to the present invention uses a resin substrate having copper foil bonded to one or both surfaces thereof, and forms a wiring pattern on one or both surfaces of the resin substrate. In a method of manufacturing a chip package for forming a terminal connection pad and a semiconductor element connection pad,
A step of etching and removing the copper foil formed on the surface of the resin substrate,
Forming an electroless copper plating film on the surface of the resin substrate,
Forming a plating resist pattern opposite to the wiring pattern on the surface of the electroless copper plating film,
Energizing the electroless copper plating film and forming an electrolytic copper plating film on the surface of the electroless copper plating film that is not covered with a plating resist pattern opposite to the wiring pattern,
An electric current is applied to the electroless copper plating film serving as the wiring pattern, and a Ni and Au plating film is formed by electrolytic plating on the surface of the electrolytic copper plating film that is not covered with the plating resist pattern opposite to the wiring pattern. Forming the external terminal connection pad and the semiconductor element connection pad by:
Removing the plating resist pattern opposite to the wiring pattern, and etching and removing the Ni and Au plating films and the electroless copper plating film not covered with the electrolytic copper plating film.
It is characterized by containing .
[0019]
According to the chip package manufacturing method (1), the metal layer for the wiring pattern and the ball pad and the metal layer for the through hole portion are formed by forming the electroless copper plating layer. Since they can be formed simultaneously, the manufacturing process of the chip package can be simplified. Further, the electroless copper plating layer can be formed as thin as about 1 micron, and the subsequent etching of the electroless copper plating layer as a metal layer is easy. It is possible to easily achieve a high-density wiring pattern by minimizing the amount of overhang at the time of etching the layer.
[0020]
Further, in the method ( 2 ) for manufacturing a chip package according to the present invention, in the method ( 1 ) for manufacturing a chip package described above, after forming a through hole in the resin substrate, an electroless copper plating process is performed on a side wall surface of the through hole. And a step of performing an electrolytic plating process.
[0021]
According to the chip package manufacturing method (2), the copper plating film, which is a good conductor, is formed on the side wall surface of the through hole before the Ni / Au plating process by the electrolytic plating method. A Ni / Au plating film can also be formed on the wall surface by electrolytic plating. Therefore, the reliability of the chip package can be improved.
[0022]
Also, in the chip package manufacturing method (3) according to the present invention, in the chip package manufacturing method (1), before forming the plating resist pattern opposite to the wiring pattern, the surface of the electroless copper plating film is adjusted. It is characterized in that surface treatment is performed.
[0023]
By performing the surface conditioning treatment, the adhesion of the plating resist pattern to the metal layer surface is improved, and the plating solution is prevented from penetrating into the lower surface of the plating resist pattern even during electrolytic plating. In addition, the occurrence of a short circuit pattern can be suppressed.
[0024]
Further, the method (4) for manufacturing a chip package according to the present invention is the method according to any one of the methods (1) to (3) for manufacturing a chip package, wherein the copper foil formed on the surface of the resin substrate is removed by etching. The surface of the resin substrate after the roughening is subjected to a roughening treatment .
[0025]
According to the chip package manufacturing method (4), the adhesion of the electroless copper during the electroless copper plating treatment can be improved.
[0026]
The chip package manufacturing method (5) according to the present invention is the chip package manufacturing method according to any one of (1) to (4), wherein a copper ammine complex or a tetraammine chloride is used as an etchant for the electroless copper plating film. It is characterized in that an alkaline liquid containing copper (II) as a main component is used.
[0027]
The above-mentioned alkali liquid containing copper ammine complex or tetraammine copper (II) chloride as a main component can efficiently etch only the copper layer without dissolving the Ni and Au coatings. Therefore, the copper layer can be efficiently etched using the Ni / Au electrolytic plating film as an etching mask.
[0028]
Further, the method (6) for manufacturing a chip package according to the present invention is the method for manufacturing a chip package according to any one of the above-described methods (1) to (5), wherein sodium persulfate or peroxide is used as an etchant for the electroless copper plating film. It is characterized in that a soft etching solution containing a mixture of hydrogen and sulfuric acid as a main component is used.
[0029]
The above-described soft etching solution containing soda persulfate or a mixture of hydrogen peroxide and sulfuric acid as a main component can efficiently form a copper layer without dissolving an Au film by using the copper ammine complex or tetraammine copper chloride. Etching can be performed more mildly than an alkaline solution containing (II) as a main component. Therefore, the electroless copper plating layer can be accurately and efficiently etched using the Ni / Au electrolytic plating film as an etching mask, with almost no overhang on the electroless copper plating layer.
[0030]
Further, the chip package according to the present invention is characterized in that the lead wire for electroplating obtained by using any one of the above-described chip package manufacturing methods (1) to (6) is not formed. And
[0031]
According to the above-mentioned chip package, since the energization at the time of electrolytic plating is performed on the electroless copper plating film, lead wires for electrolytic plating, which are normally required, are not required, and high density hindrance due to the presence of these lead wires, Deterioration of electrical characteristics can be prevented. Further, since the plating for forming the Ni film and the Au film is performed by the electrolytic plating method, a sufficient value of the adhesive strength of the solder ball can be obtained.
[0032]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a chip package and a method of manufacturing the same according to the present invention will be described with reference to the drawings.
1 to 4 are schematic cross-sectional views showing a part of a manufacturing process of the flip chip package according to the embodiment ( 1 ), wherein 1 shows a copper-clad laminate. Copper-clad laminate 1 is composed is adhered copper foil 3 on both main surfaces of the resin substrate 2 (FIG. 1 (a), FIG. 3 (a)), the through-hole 4 in the copper clad laminate 1 subjected to a boring (Figure 3 (a)). Next, an etching process using a FeCl ₃ solution is performed to peel and remove the copper foil 3. Further, in order to improve the adhesion of the electroless copper during the subsequent electroless copper plating treatment, the surface of the resin substrate 2 from which the copper foil 3 has been removed is roughened using a permanganic acid solution for surface roughening. previously subjected to a treatment (FIG. 1 (b), the Figure 3 (b)).
[0033]
Next, the entire surface of both main surfaces of the resin substrate 2 including the side wall surface of the through hole 4 is subjected to panel plating by electroless copper plating, so that the electroless copper plating has a thickness of about 1/10 of the thickness of the copper foil 3. forming a layer 6a, an electroless copper plating layer 6a formed on the upper surface and the lower surface of the resin substrate 2 through a through-hole 4 keep electrically connected ((FIG. 1 (c), the FIG. 3 (c )).
[0034]
Next, the surface of the electroless copper plating layer 6a is subjected to surface smoothing. The surface conditioning treatment is a treatment performed to enhance the adhesion of the DFR 8 to be adhered later, and more specifically, a jet scrub (mechanical polishing by buffing), pickling with sulfuric acid, a jet scrub treatment, or the like. A DFR (dry film resist) 8 containing an acrylic resin as a main component is adhered on the electroless copper plating layer 6a that has been subjected to the above-mentioned surface conditioning. Next, the DFR 8 is subjected to an exposure process for developing a pattern reverse to the wiring pattern, and then a PEB (Post Exposure Bake) process is performed before the development in order to promote a photocuring reaction due to the exposure and improve the adhesion. Next, DFR8 is developed to leave the DFR8 of the reverse pattern, and then post-baked for the purpose of promoting the thermosetting reaction and improving the adhesion (FIG. 1 (d), FIG. 3 ). (D)).
[0035]
Next, in order to form the electrolytic copper plating layer 6b on the surface portion of the electroless copper plating layer 6a not covered with the DFR 8, the resin substrate 2 is immersed in a plating solution, energized, and subjected to electrolytic plating treatment (FIG. 2 (a), FIG. 4 (a)). Subsequently, in order to form the Ni / Au layer 9 on the surface portion of the electrolytic copper plating layer 6b not covered with the DFR 8, the resin substrate 2 is immersed in a plating solution and energized to perform an electrolytic plating process (FIG. 2 ). (B), FIG. 4 (b)). After the plating solution is thoroughly washed with water, it is immersed in a 3% NaOH aqueous solution at 50 ° C. to peel off and remove DFR8. After removal completion of DFR8 (FIG. 2 (c), the FIG. 4 (c)), to etch the electroless copper plating layer 6a of the Ni / Au layer 9 formed as a mask. As the etchant, it is preferable to etch only the electroless copper plating layer 6a without etching the Ni / Au layer 9, but since the electroless copper plating layer 6a can be made thinner by about one digit as compared with the copper foil 3, Etching can be performed without using an alkaline solution containing copper ammine complex or tetraammine copper (II) chloride as a main component. For example, soft etching of soda persulfate or a mixed solution of hydrogen peroxide and sulfuric acid can be used. A liquid can be used as an etchant. By this etching process, a wiring pattern 30 including a pad portion in which the electrolytic plating film of the Ni / Au layer 9 is formed on the Cu wiring composed of the electroless copper plating layer 6a and the electrolytic copper plating layer 6b is formed (FIG. 2 ). (D), FIG. 4 (d)).
[0036]
According to the method of manufacturing the flip chip package according to the present embodiment ( 1 ), the electroless copper plating layer 6a itself serves as the conventional lead wire 20 for plating (FIG. 6 ). Without formation, the Ni / Au layer 9 can be formed on the wiring pattern 30 by the electrolytic plating method. Moreover, since the electroless copper plating layer 6a can be made thinner by about one digit as compared with the copper foil 3, the etching of the electroless copper plating layer 6a for forming a pattern becomes very easy, and the overhang occurs. The amount can be almost eliminated (about 1/10 of the case where the copper foil 3 is used), and it is easy to increase the density of the wiring pattern 30. In addition, there is no reflection due to the plating lead wire 20 which remains partially, and the electrical characteristics can be improved. In addition, since the Ni / Au layer 9 is formed by the electrolytic plating method, a sufficiently large value of the wire bonding and the bonding strength of the solder ball 15 (FIG. 7 ) can be secured.
[0037]
Further, since the Ni / Au layer 9 is formed also on the side wall surface of the through hole 4 by the electrolytic plating method, the reliability can be improved.
[0038]
The DFR 8 containing an acrylic resin as a main component has a high resistance to a plating solution used when the Ni / Au layer 9 is formed by the electrolytic plating method, and has good releasability with a stripping solution such as an aqueous NaOH solution. Peeling residue hardly occurs. Therefore, it is easy to accurately form the wiring pattern 30, and a short circuit between wirings is less likely to occur. Further, the adhesion of the DFR 8 to the electroless copper plating layer 6a can be increased by the surface conditioning treatment and the baking treatment, and the intrusion of the plating solution into the lower surface of the DFR 8 can be more reliably prevented.
[0039]
Further, since an etchant of the electroless copper plating layer 6a is made of soda persulfate or a soft etching solution containing a mixture of hydrogen peroxide and sulfuric acid as a main component, the Au layer 9 formed by electrolytic plating is dissolved. Without overheating, the amount of overhang of the electroless copper plating layer 6a can be suppressed and the electroless copper plating layer 6a can be efficiently etched, and the handling is easy, and the waste liquid treatment is easy. .
[0040]
In the above embodiment ( 1 ), the manufacturing method of the flip chip package has been described as an example. However, the manufacturing method according to the present invention is not limited to the manufacturing method of the flip chip package, and the manufacturing method according to the present invention. Since the Ni / Au layer 9 is formed by the electrolytic plating method, the thickness of the Ni / Au layer 9 can be easily adjusted unlike the case of the electroless plating method. By increasing the thickness, the present invention can be similarly applied to a method of manufacturing a BGA package of a wire bonding type. Further, in the above embodiment ( 1 ), the resin substrate 2 obtained by peeling and removing the copper foil 3 from the copper-clad laminate 1 was used, but in another embodiment, it is not necessary to use the copper-clad laminate 1 at all. The resin substrate 2 may be used as a starting material to form a through hole 4 or the like. In the first embodiment, DFR8 is used as a plating mask. However, the plating mask is not limited to DFR8. In another embodiment, a resist pattern is formed using a liquid resist. No problem.
[0041]
【Example】
Hereinafter, embodiments of a chip package and a method of manufacturing the chip package according to the present invention will be described.
Example 1
To prepare a flip chip package by the method shown in FIGS. Specific production conditions are shown below.

The Ni / Au layer 9 shown in FIG. 5 was formed on the ball pad and the through hole.
[0042]
Peeling test of Ni / Au layer 9: A good value could be obtained without peeling in a peel test using a commercial cellotape (R).
[Brief description of the drawings]
[1] (a) ~ (d) are sectional views showing a part of the manufacturing process of a flip-chip package according to an embodiment of the present invention (3).
[2] (a) ~ (d) are sectional views showing a part of the manufacturing process of a flip-chip package according to an embodiment of the present invention (3).
3 (a) to 3 (d) are cross-sectional views showing a part of a manufacturing process of a flip chip package according to Embodiment (3) of the present invention.
[4] (a) ~ (d) are sectional views showing a part of the manufacturing process of a flip-chip package according to an embodiment of the present invention (3).
FIG. 5 is an enlarged cross-sectional view showing a Ni / Au layer formed on a bonding pad according to an example.
FIG. 6 is a sectional view showing an example of a conventional PBGA.
7 (a) is a plan view showing a BT substrate conventional plating lead wire is formed, (b
() Is a sectional view.
FIG. 8 is a cross-sectional view showing an example of a conventional BGA with a two-layer heat sink.
FIG. 9 is an enlarged sectional view showing the vicinity of a ball pad.
FIG. 10 is a sectional view showing an example of a conventional flip chip package.
FIG. 11 is an enlarged sectional view showing the vicinity of a ball pad.
[Explanation of symbols]
1, 1a Copper clad laminate 2 Resin substrate 3, 3a Copper foil 4 Through hole 6 Cu layer 7 Cu plate 7a Adhesive sheet 8 DFR
9 Ni / Au layer 10 Wiring pattern (including pad)
43 Solder Mask

Claims (7)

Using a resin substrate having a copper foil bonded to one or both sides thereof, a wiring pattern on one or both sides of the resin substrate, an external terminal connection pad, and a method of manufacturing a chip package for forming a semiconductor element connection pad,
A step of etching and removing the copper foil formed on the surface of the resin substrate,
Forming an electroless copper plating film on the surface of the resin substrate,
Forming a plating resist pattern opposite to the wiring pattern on the surface of the electroless copper plating film,
Energizing the electroless copper plating film and forming an electrolytic copper plating film on the surface of the electroless copper plating film that is not covered with a plating resist pattern opposite to the wiring pattern,
An electric current is applied to the electroless copper plating film serving as the wiring pattern, and a Ni and Au plating film is formed by electrolytic plating on the surface of the electrolytic copper plating film that is not covered with the plating resist pattern opposite to the wiring pattern. Forming the external terminal connection pad and the semiconductor element connection pad by:
Removing the plating resist pattern opposite to the wiring pattern, and etching and removing the Ni and Au plating films and the electroless copper plating film not covered with the electrolytic copper plating film.
A method for manufacturing a chip package, comprising: After forming a through hole in the resin substrate, a manufacturing method of claim 1, wherein the chip package, characterized in that it includes the step of electroless plating process and the electrolytic plating copper on the side wall surface of the through hole . 3. The method for manufacturing a chip package according to claim 1, wherein the surface of the electroless copper plating film is subjected to a surface treatment before forming a plating resist pattern opposite to the wiring pattern . The surface according to any one of claims 1 to 3, wherein the surface of the resin substrate after the copper foil formed on the surface of the resin substrate is removed by etching. The manufacturing method of the chip package described in the above. The chip package according to any one of claims 1 to 4, wherein a copper ammine complex or an alkaline solution containing copper (II) tetraammine chloride as a main component is used as an etchant of the electroless copper plating film . Production method. According to any one of claims 1 to 4, characterized by using a soft etching solution mainly composed of a mixed solution of sodium persulfate or hydrogen peroxide and sulfuric acid, as an etchant of the electroless copper plating film Manufacturing method of chip package. A chip package, wherein a lead wire for electroplating obtained by using the manufacturing method according to any one of claims 1 to 6 is not formed.

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