JP3555740B2 - Information compression device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an information compression device, and more particularly, to an information compression device that compresses and codes an input image signal and an audio signal.
[0002]
[Prior art]
In various fields such as communication, broadcasting, and storage media, technology for compressing information signals is extremely important in transmitting information signals with as much information as possible through transmission paths with a limited transmission band. Various information compression techniques have been proposed. Among them, a typical information compression technique is an information compression technique based on MPEG (Moving Picture Experts Group), which is an international video coding standard for performing high-efficiency compression coding on image signals and audio signals.
[0003]
In such an information compression apparatus of the MPEG system, the compression operation is performed in units of a plurality of frames, and the control of the code amount is also performed in units of a plurality of frames called a so-called GOP (group of pictures). It is a unit. FIG. 2 shows an example of this GOP configuration. In the figure, I indicates an I picture, B indicates a B picture, P indicates a P picture, a subscript indicates an order in a GOP, and an arrow indicates a prediction direction.
[0004]
As is well known, an I-picture is an intra-coded image (intra-frame coded image) obtained by compressing and encoding image information of one screen in the same order as an original image, and a P-picture represents image information between frames as an original image. It is an inter-frame forward prediction coded image compressed in the same order. A B-picture is a bidirectionally predictive coded image inserted between the I-picture and the P-picture after they are processed first. One GOP is composed of one I picture and one or more P pictures and B pictures.
[0005]
[Problems to be solved by the invention]
In the above-mentioned conventional information compression apparatus, if the number of frames (the number of pictures) constituting a GOP is large, the image quality of the same code amount is improved, but the processing unit becomes large and the unit that can be edited becomes large. When applied, it becomes difficult to perform recording pause at an arbitrary position on the recording medium. On the other hand, when the number of frames (the number of pictures) constituting the GOP is reduced (for example, one frame), the editing unit becomes small, and the recording pause becomes possible on all screens, but the image quality with the same code amount deteriorates.
[0006]
Further, the image signal encoded into the compression-encoded data of the MPEG system needs to be a signal edited before encoding or a signal in which an editing point is specified, and thus the workability is poor. For example, if the image is interrupted at the picture P ₀₁ in the GOP of FIG. 2, because the next encoding also must Namere start from the I picture. Further, the conventional apparatus has a problem that a large-capacity memory is required for editing before encoding or for specifying an editing point.
[0007]
The present invention has been made in view of the above points, and an object of the present invention is to provide an information compression apparatus that can continuously perform information compression without editing before encoding or designating an editing point.
[0008]
Another object of the present invention is to provide an information compression device capable of improving workability.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a memory for writing at least an information signal including an image signal, an address generation circuit for generating an address of the memory, and detecting a head of a frame of the information signal. a compression processing circuit for outputting encoded data start address storage means, and compresses and encodes the information signal read from the memory in a plurality of frames for storing the memory address when it is written in the memory, the information signal in A synchronizing signal separating the synchronizing signal, a phase locked loop circuit to which a synchronizing signal output from the synchronizing signal is supplied, a synchronizing signal output from the synchronizing signal, and a synchronizing pulse generated by the phase locked loop circuit And that the synchronization signal and the synchronization pulse are out of synchronization by the comparison circuit. In, when the pause each compression process operation of the address increment the compression processing circuit of the address generation circuit, synchronized re agreement between the synchronizing signal and the synchronizing pulse is detected by said comparator circuit, said address generating circuit Control means for restarting the address increment from the memory address stored by the head address storage means, starting writing of a new information signal into the memory from the head of the frame, and restarting the compression processing operation of the compression processing circuit. And a configuration having:
[0010]
According to the present invention, when it is detected that the synchronization signal output from the synchronization separation circuit is out of synchronization with the synchronization pulse generated by the phase locked loop circuit , an address signal is supplied to a memory for storing an information signal. The stepping of the address generation circuit and the compression processing operation of the compression processing circuit for compressing and encoding the information signal read from the memory by a predetermined method and outputting encoded data are stopped, and the synchronization signal and the synchronization pulse are stopped. If a synchronization re-match is detected , the address advance of the address generation circuit is returned to the head memory address of the frame of the information signal and started there, and the writing of the information signal to the memory from the head of the frame is started. The information that was discontinued in the middle of the frame and stored in the memory because the compression processing operation of the compression processing circuit was started at the same time Thereafter, the signal is rewritten from the beginning of the frame of the information signal that has returned to normal, and is read from the beginning of the frame of the information signal that has returned to normal and input to the compression processing circuit. Compression encoding can be performed while maintaining the same frame sequence.
[0011]
Further, the present invention provides a memory for writing an information signal including at least an image signal, an address generation circuit for generating an address of the memory, and detecting a head of a frame of the information signal so that the head of the frame is stored in the memory. A head address storage means for storing a memory address at the time of writing, a compression processing circuit for compressing and encoding an information signal read from the memory in a plurality of frame units and outputting encoded data, an encode pause button, When the ON of the encode pause button is detected, the address increment of the address generation circuit and the compression processing operation of the compression processing circuit are temporarily stopped, and when the release of the encode pause button is detected, The address increment of the address generation circuit is stored in the memory address stored by the head address storage means. Together to start writing from the beginning of the frame of a new information signal is resumed to the memory from, and having a control means for resuming the compression operation of the compression circuit.
[0012]
According to the present invention, the encoding can be temporarily stopped by turning on the encode pause button, and then turned off (canceled) by turning off (cancel) the encode pause button, so that the start position of the first frame of the input image signal after the cancellation is detected. Returning to the frame start address, the writing to the memory is resumed, and the compression processing on the image data read from the memory can be resumed in the original sequence immediately after the compression operation is stopped. The edited signal or the editing point need not be the designated signal.
[0013]
Further, the compression processing circuit according to the present invention performs the MPEG compression coding having a predetermined GOP sequence on the information signal read from the memory, and performs the compression processing from the temporary stop to the restart of the compression processing operation. The GOP sequence in the encoded data is maintained.

[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an information compression apparatus according to the present invention. In FIG. 1, an image signal input via an input terminal 10 is input to a sync separation circuit 11 where a horizontal sync signal (H.SYNC) and a vertical sync signal (V.SYNC) are separated, while a low-frequency signal is output. The signal is input to a filter (LPF) 12 to remove high frequency components and is supplied to an A / D converter 13, where it is converted into a digital signal.
[0015]
The horizontal synchronization signal and the vertical synchronization signal separated by the synchronization separation circuit 11 are respectively supplied to a PLL (Phase Locked Loop) circuit 14 and are at least twice as high as the highest frequency of the input video signal at the input terminal 10. Is generated as a sampling clock fs at a high frequency and phase-synchronized with the synchronization signal. The H-pulse at the horizontal scanning frequency is phase-synchronized with the horizontal synchronization signal. Generated on V pulse.
[0016]
At least one of the horizontal synchronization signal and the vertical synchronization signal output from the synchronization separation circuit 11 becomes discontinuous when the discontinuity of the input image signal occurs, whereas the H pulse and the V pulse extracted from the PLL circuit 14 are Even if the discontinuity of the input image signal occurs, if the discontinuity period is short, the phase is locked to the horizontal synchronization signal and the vertical synchronization signal of the input image signal before the discontinuity occurs, and is taken out. The H pulse and the V pulse are supplied to the discontinuity detecting / controlling circuit 15 together with the horizontal synchronizing signal and the vertical synchronizing signal output from the synchronizing separation circuit 11, respectively.
[0017]
Thus, the discontinuity detection / control circuit 15 can monitor whether the input image signal is discontinuous by comparing the horizontal synchronization signal with the H pulse and the vertical synchronization signal with the V pulse. The discontinuity detection / control circuit 15 generates an effective area of the image based on the H pulse and the V pulse, generates an enable signal for increasing a memory address, and supplies the enable signal to the address generation circuit 17. At the same time, a load signal is generated by detecting the head position of the frame of the input image signal, and the load signal is supplied to the address latch 16 to latch the address of the head position of the frame from the address generation circuit 17. .
[0018]
Thus, when the input image signal is not discontinuous, the sampling clock from the PLL circuit 14 is supplied to the A / D converter 13, input to the address latch 16 as a shift clock, and supplied to the address generation circuit 17. To advance the memory address.
[0019]
The image data extracted from the A / D converter 13 that performs analog-to-digital conversion in synchronization with the sampling clock from the PLL circuit 14 is supplied to the memory 18 and converted to an address according to the memory address from the address generation circuit 17. After being stored, the data is supplied to the compression processing circuit 19, and is subjected to the known compression encoding according to the above-mentioned MPEG method. The compression-encoded coded image data is extracted from the compression processing circuit 19, supplied to the memory 20, and accumulated. The memory 20 is, for example, a storage medium such as a hard disk or an optical disk, and reads out at a constant speed after storing coded image data for one program, for example.
[0020]
Here, assuming that a discontinuity occurs due to switching of the input channel in the input image signal, the discontinuity detection / control circuit 15 compares the horizontal synchronization signal with the H pulse and the vertical synchronization signal with the V pulse, respectively. , A discontinuity of the input image signal is detected, and a disable signal is supplied to stop the address generation operation of the address generation circuit 17, thereby stopping the write operation of the memory 18 and sending the HALT signal to the compression processing unit 19. To temporarily stop the compression operation.
[0021]
During that time, the discontinuity detection / control circuit 15 monitors whether the input image signal has become normal by comparing the horizontal synchronization signal with the H pulse and the vertical synchronization signal with the V pulse, respectively. If the H pulse and the vertical synchronizing signal are synchronized with the V pulse, it is considered that the input image signal has become normal, and the frame start address at the time of writing, which is latched in the address latch 16, is loaded into the address generating circuit 17, and When the head position of the first frame of the input image signal after the detection of the restoration is detected, returning to the above-mentioned frame head address, restarting the writing to the memory 18 and releasing the HALT signal to the compression processing circuit 19, The compression processing for the image data read from the memory 18 is restarted in the original sequence immediately after the compression operation is stopped.
[0022]
As a result, the image data that has become discontinuous in the middle of the frame stored in the memory 18 is rewritten from the beginning of the frame of the image data that has returned to the normal state, and the frame of the image data that has returned to the normal state. Are read from the beginning and input to the compression processing circuit 19, and compression encoding is performed with the same picture as when the compression operation was stopped and with the GOP frame sequence maintained. Thus, with a GOP configuration having an appropriate number of frames, recording pause can be applied to all screens, and information compression that does not cause deterioration in image quality can be realized.
[0023]
The present invention is not limited to the above embodiment. For example, the present invention is applied to a recording device that records the output compressed image data of the memory 20 on a recording medium, and a user turns on an encode pause button at an arbitrary timing. When the encoding pause button is detected by the user at an arbitrary timing, the writing operation of the memory 18 is stopped, and the compression operation of the compression processing unit 19 is temporarily stopped. May be detected as normal recovery, and the writing to the memory 18 may be restarted from the image data at the frame start position immediately after that, and the compression operation of the compression processing circuit 19 may be restarted.
[0024]
In this case, it is possible to freely assemble and edit the input image signal at the time of encoding, thereby improving workability and eliminating the need for a storage device for previously edited material. Further, by turning on the encoding end button, the encoding is ended at the break of the GOP. Further, in the above-described embodiment, the description has been made such that the image signal is compression-coded. However, the present invention can be similarly applied to an audio signal.
[0025]
【The invention's effect】
As described above, according to the present invention, an information signal that is stored in a memory and becomes discontinuous in the middle of a frame is rewritten with a new information signal, and this information signal is read from the memory. Since compression encoding can be performed while being input to the compression processing circuit and maintaining the same frame sequence as when the compression operation is temporarily stopped, even if the information signal becomes discontinuous so that the input channel can be switched, the compression encoding can be performed. without changing the frame sequence of data, off subsequent information signal compression encoding.
[0026]
Further, according to the present invention, by turning on the encoding pause button, encoding can pause, then the encoding pause button By off (released), it is possible to resume the encoding, encoded information signal encoded The previously edited signal or the editing point does not have to be the designated signal, so that the workability can be improved, and a device for storing the pre-edited material is not required, and the device can be configured at low cost. it can.
[Brief description of the drawings]
FIG. 1 is a block diagram of one embodiment of the present invention.
FIG. 2 is an explanatory diagram of the structure of a GOP.
[Explanation of symbols]
10 Image signal input terminal 11 Sync separation circuit (detection means)
13 A / D converter 14 PLL circuit (detection means)
15 Discontinuity detection / control circuit (detection means, control means, comparison means)
16. Address latch circuit (head address storage means)
17 Address generation circuit 18 Memory 19 Compression processing circuit 20 Memory

Claims (3)

A memory for writing an information signal including at least an image signal;
An address generation circuit that generates an address of the memory;
Head address storage means for detecting a head of a frame of the information signal and storing a memory address when the head of the frame is written to the memory;
A compression processing circuit that compresses and encodes the information signal read from the memory in units of a plurality of frames and outputs encoded data;
A synchronization separation circuit that separates a synchronization signal in the information signal, a phase locked loop circuit to which a synchronization signal output from the synchronization separation circuit is supplied, a synchronization signal output from the synchronization separation circuit, and the phase locked loop circuit. A comparison circuit that compares the generated synchronization pulse with
Wherein the the comparator circuit when the synchronization with the synchronizing signal and the synchronizing pulse is detected to have deviated, the compression operation of the address increment to the compression processing circuit of the address generation circuit to pause, respectively, the comparison When a synchronization re-coincidence between the synchronization signal and the synchronization pulse is detected by the circuit, the address increment of the address generation circuit is restarted from the memory address stored by the head address storage means, and a new information signal is generated. Control means for starting writing to the memory from the beginning of a frame and restarting the compression processing operation of the compression processing circuit. A memory for writing an information signal including at least an image signal;
An address generation circuit that generates an address of the memory;
Head address storage means for detecting a head of a frame of the information signal and storing a memory address when the head of the frame is written to the memory;
A compression processing circuit that compresses and encodes the information signal read from the memory in units of a plurality of frames and outputs encoded data;
An encode pause button,
When the ON of the encode pause button is detected , the address increment of the address generation circuit and the compression processing operation of the compression processing circuit are temporarily stopped, and when the release of the encode pause button is detected , The address increment of the address generation circuit is restarted from the memory address stored by the head address storage means to start writing a new information signal to the memory from the head of the frame, and the compression processing operation of the compression processing circuit Control means for restarting the information compression. The compression processing circuit performs an MPEG compression coding having a predetermined GOP sequence on the information signal read from the memory, and performs the compression coding from the temporary stop to the restart of the compression processing operation. information compression apparatus according to claim 1 or 2, wherein the GOP sequence in the coding data is maintained.

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