JP3556293B2 - Multimedia data recording device - Google Patents

Description

とするサイズであることから、入力時のデータエリアの容量を１物理ブロックエリア内に包容することができる。また、余剰エリアは無効データとして配列するようにしても良いが、信頼性向上用のオプションとして物理ブロック単位でＥＣＣを追加して付けるシステムとして構成するようにしても良い。
【００７０】
これにより、民生用ディジタルＶＴＲにおけるビデオデータ領域は、１トラック１３５ＳＹＮＣであることから、図３に示すように１５ＳＹＮＣ１ブロックで構成する物理ブロックを９ブロック記録することが可能となる。尚、誤り訂正外符号器６１による誤り訂正符号は、記録する１トラックのビデオデータエリア分の９ブロック（＋ＶＡＵＸの３ＳＹＮＣ）におけるデータに対して付加するようになっている。
【００７１】
また、再生時においては、記録時における処理とは逆の処理が行われる。即ち、誤り訂正外復号器６４で１トラック分（１３５ＳＹＮＣ＋ＶＡＵＸ３ＳＹＮＣ）の再生データを誤り訂正した後、１５ＳＹＮＣ分のデータずつバッファメモリ３に伝送する。その後、ヘッダー２４バイトをデコードすると共に、各シンクのヘッダー１バイトによりパケットの識別とシンクシリーズＮｏとをデコードした後、バッファメモリ３に各シンクの有効データ７６バイトずつ１５ＳＹＮＣ、順に書き込む。このようにして１０２４バイトの有効データをバッファメモリ３に書き込むようにする。また、同様に次のブロックからも有効データ１０２４バイトをバッファメモリ３に書き込み、１トラック９ブロックのデータから、（１０２４×９バイト）のデータをバッファメモリ３に書き込む。この場合のバッファメモリメモリ３に対する書き込み制御は、記録時と同様にバッファコントロール部４により行われることになる。また、誤り訂正外復号器６４からバッファメモリ３へのデータ転送速度は、記録時と同様の転送速度３．１Ｍバイト／ｓｅｃで転送するようになっている。
【００７２】
したがって、本実施例によれば、コンピュータ等から、ＳＣＳＩを介して伝送されたデータにおいて、１５ＳＹＮＣ×９ブロックの物理フォーマットに変換することにより、元のパケット構成を壊すことなく記録し且つ再生を行うことができるという効果を有する。
【００７３】
尚、本実施例におけるデータストリーマでは、コンピュータからのコンピュータデータを入出力するたの伝送方式としてＳＣＳＩケーブルについて説明したが、これに限定されることなく別の種類のケーブルを用いて伝送しても良い。例えば高速転送が可能なＰ１３９４等のシリアルＳＣＳＩ方式を用いて伝送するようにしても良い。
次に、本発明に係るマルチメディアデータ記録・再生装置の第２実施例を図１及び図７を参照して説明する。
【００７４】
本実施例においては、異なる種類の伝送経路によるパケット単位の入力データに対しても、１５ＳＹＮＣ×９ブロックの物理フォーマットで元のパケット構成を壊すことなく記録及び再生することができるという本発明の目的を達成するめたに、前記実施例とは別の伝送形態による入力データが供給された場合について説明する。例えば、データストリーマとしてのマルチメディアデータ記録・再生装置のディジタルインターフェースに、図１に示すＡＴＶデコーダ１１と接続し、且つＭＰＥＧ２方式の伝送形態でデータの入出力を行う。即ち、ＭＰＥＧ２のトランスポートストリームを本発明の伝送パケットに変換して、誤り訂正外符号復号器に伝送し、前記実施例と同様の物理ブロックによるフォーマットで記録しまたは再生して出力する場合である。
【００７５】
図７はＭＰＥＧ２方式による伝送形態の場合における本発明のパケット変換処理を説明するための説明図である。
【００７６】
いま、図１に示すＡＴＶデコーダ１１から、ＭＰＥＧ２方式により伝送されたデータが切換スイッチ６に供給されたものとする。すると、本実施例では、ＭＰＥＧ２による伝送形態に基づくデータが供給されるものとしていることから、切換スイッチ６は各種伝送形態の内、ＭＰＥＧ２により伝送されたデータを選択して、ディジタルインターフェース２に供給する。このとき、ディジタルインターフェース２に供給されるデータは、ＭＰＥＧ２のトランスポートストリームパケットでＡＴＶデコーダ１１等から伝送されることになる。ＭＰＥＧ２のトランスポートストリームのパケットサイズは、図７に示すように１パケット１８８バイトである。つまり、本例の場合では、パケットに区切って伝送するため、誤り伝播が小さく、且つハードウェア処理がし易くなる。言い替えればパケットを壊さないで伝送することが肝要である。
【００７７】
よって、この２パケット（１８８×２＝３７６バイト）が、丁度ディジタルＶＴＲの５ＳＹＮＣサイズ（３８５バイト）に変換すると都合がよいことは既に、ディジタルＶＴＲの協議会で現在検討されている。したがって、図７に示すように、各シンクの頭にはヘッダーを付加する。この場合ヘッダーは、ＭＰＥＧ２パケットの識別４ビットと、シンクシリーズＮｏの４ビットとで構成し、即ち１バイトヘッダーとなる。また、２パケットの繋ぎめに１バイトのマークを付加し、５ＳＹＮＣ目の最後の３バイトを無効データとするように配列する。
【００７８】
この場合も、図１で、ＡＴＶデコーダからのデータ入力に対しバッファメモリ３でＭＰＥＧ２パケットを５ＳＹＮＣ単位に変換し、バッファメモリ３からは、５ＳＹＮＣを３つに配列し且つ１５ＳＹＮＣ単位で読み出すことで、前述したように、誤り訂正外符号器６１のディジタルインターフェースのビデオデータエリアタイミングである１５ＳＹＮＣ毎のタイミングに合わせることができる。以下、前記実施例におけるデータストリーマの場合と同様に、図３に示す記録フォーマットに１５ＳＹＮＣ×９ブロックの形で記録することが可能となる。つまり１ブロックあたりのＭＰＥＧ２トランスポートストリームは６パケット、即ち１トラックあたり５４パケットとして記録することができる。
【００７９】
一方、再生時においても、前記第１実施例と同様に再生処理が行われる。即ち、誤り訂正外復号器６４から１５ＳＹＮＣ単位に読み出し、有効データ部のみバッファメモリ３に書き込み、バッファメモリ３から５ＳＹＮＣ分のデータずつ、ＭＰＥＧ２の２パケットデータ分ずつ読み出す。これにより、ディジタルＶＴＲから、ＭＰＥＧ２のビットストリームであるＡＴＶのパケットで、ＡＴＶデコーダ１１に出力することができる。
【００８０】
したがって、本実施例においても、前記第１実施例と同様に本発明によるパケット変換を行うことにより、ＡＴＶデコーダからのＭＰＥＧ２方式で伝送したデータの記録及び再生を行うことができるという効果を有する。
【００８１】
次に、本発明に係るマルチメディアデータ記録・再生装置の第３実施例を図１及び図８を参照して説明する。
【００８２】
本実施例においては、データストリーマとしてのマルチメディアデータ記録・再生装置のディジタルインターフェースに、図１に示すＡＴＶ変換器１２を接続し、且つＭＰＥＧ２方式のトランスポートストリームをＩＳＤＮや高速ＬＡＮといった、ＡＴＭ網（以下、ＡＴＭセルと記載）１２ａを使用してデータの入出力を行う。即ち、ＭＰＥＧ２のトランスポートストリームをＡＴＭセル１２ａで伝送するパケット形態を、本発明の伝送パケットに変換して、誤り訂正外符号復号器に伝送し、前記実施例と同様の物理ブロックによるフォーマットで記録しまたは再生して出力する。
【００８３】
図８はＭＰＥＧ２方式のトランスポートストリームをＡＴＭセルを用いて伝送した場合の本発明のパケット変換処理を説明するための説明図である。
【００８４】
いま、図１に示すＡＴＭ変換器１２から、ＭＰＥＧ２方式のトランスポートストリームがＡＴＭセル１２ａによる伝送形態で伝送されたデータが、切換スイッチ６に供給されたものとする。すると、本実施例では、ＡＴＭセル１２ａによる伝送形態に基づくデータが供給されるものとしていることから、切換スイッチ６は各種伝送形態の内、ＡＴＭセル１２ａにより伝送されたデータを選択して、ディジタルインターフェース２に供給する。このとき、ディジタルインターフェース２に供給されるデータは、ＭＰＥＧ２のトランスポートストリームがＡＴＭセルの伝送方式でＡＴＶ変換器１２から伝送されることになる。
【００８５】
例えば、ＡＴＭセル１２ａをデータ通信用のＡＡＬ５の場合に設定したものとする。すると、この場合１セルは、図８に示すように４８バイトである。このため、ＭＰＥＧ２のトランスポートストリームパケットは、前記実施例で説明したように１パケット１８８バイトであることから、ＭＰＥＧ２のトランスポートストリームパケットは４個のＡＴＭセルで伝送することができることになる。
【００８６】
したがって、前記第２実施例で述べたように、ディジタルＶＴＲのＳＹＮＣ単位へのパケット変換を行うようにして、ＭＰＥＧ２のトランスポートストリームパケットの２パケットを、８個のＡＴＭセルで伝送する。このとき、３７６バイトのトランスポートストリームの最後部には、図８に示すように８バイトのＡＴＭ伝送用オーバーヘッド（CONVERGENCE SUBLAYER ）を付加する。つまり、ＡＴＶセル１２ａでは３８４バイトで伝送することになるが、この８バイトのＡＴＭ伝送用オーバーヘッドは伝送時のみのデータであるため、図１に示すバッファメモリ３に書く込む際には３７６バイトのデータを書き込むことになる。
【００８７】
その後、バッファメモリ３からは、図５に示すメモリコントロール／パケット変換制御回路４ａにより３７６バイトデータを５ＳＹＮＣ単位にパケット変換して読み出す。その後の処理は、前記第２実施例と同様に各シンクの先頭部に１バイトのヘッダーを付加する。この場合のヘッダはＡＴＭのパケットの識別４ビットと、シンクシリーズＮｏの４ビットとで構成して、１バイトヘッダーとなる。
【００８８】
この場合も、図１に示すＢ−ＩＳＤＮ等のＡＴＭ変換器１２からのデータ入力に対しバッファメモリ３で５ＳＹＮＣ単位に変換し、バッファメモリ３からは、５ＳＹＮＣを３つ配列し且つ１５ＳＹＮＣ単位で読み出すことで、誤り訂正外符号器６１のディジタルインターフェースのビデオデータエリアタイミングである１５ＳＹＮＣ毎のタイミングに合わせることができる。以下、前記第１実施例におけるＳＣＳＩ伝送のデータストリーマの場合と同様に、図３に示す記録フォーマットの１５ＳＹＮＣ×９ブロックのフォーマットで記録することが可能となる。つまり、１ブロックあたりのＡＴＭセルは２４個であり、即ち１トラックあたり２１６セルとして記録することができる。
【００８９】
一方、再生時においても第１実施例と同様に再生処理が行われる。即ち、誤り訂正外復号器６４から１５ＳＹＮＣ単位に読み出し、有効データ部のみバッファメモリ３に書き込み、バッファメモリ３から５ＳＹＮＣ分のデータを、ＡＴＭセルの４８バイト単位で８個読み出す。これにより、ＭＰＥＧ２の２パケットデータ分ずつディジタルＶＴＲから、ＡＴＭセル１２ａによる伝送形態でＡＴＭ変換器１２に出力することができる。
【００９０】
したがって、本実施例においても、前記第１実施例と同様に本発明によるパケット変換を行うことにより、ＡＴＶ変換器１２からＭＰＥＧ２のトランスポートストリームをＡＴＭセルによる伝送形態で伝送したデータの記録及び再生を行うことができるという効果を有する。
【００９１】
尚、本発明における第１乃至第３実施例においては、異なる複数の伝送形態により伝送される入力データを入力時に任意に選択して切り替えるために、切換スイッチを設けたことについてついて説明したが、この切換スイッチはディジタルＶＴＲの再生等の出力時に、再生データの先頭部に記録されている伝送形態種類のコードを判別し、且つこの判別結果に基づいて切り替えるようにしても良い。これにより、複数の異なる伝送形態の入出力データにおいても対応可能なマルチメディアデータ記録・再生装置として機能を発揮することができることは明かである。
【００９２】
【発明の効果】
以上説明したように、本発明によれば、複数の異なる伝送形態の入出力データにおいても、入力データの伝送方法及び記録フォーマットをそのままの形で壊すことなく論理ブロックを、ディジタルＶＴＲに適したパケットに変換することができることにより、記録及び再生することができる。よって、コンピュータ専用のデータストリーマだけでなく、他のディジタル機器から各々異なる伝送形態で伝送されるデータに関しても、記録及び再生が可能となるという効果を有する。
【図面の簡単な説明】
【図１】本発明に係るマルチメディアデータ記録・再生装置の一例を示すブロック図。
【図２】本発明のパケット変換処理を説明するための説明図。
【図３】本発明の１トラック分の物理フォーマットを示す図。
【図４】本発明のパケット化した論理ブロックを示す図。
【図５】図１中のバッファコントロール部の構成を示す構成図。
【図６】図５中のバッファコントロール部の動作を説明するための説明図。
【図７】本発明に係るマルチメディアデータ記録・再生装置の第２実施例を説明するための説明図。
【図８】本発明に係るマルチメディアデータ記録・再生装置の第３実施例を説明するための説明図。
【図９】従来におけるディジタルデータ記録再生装置の規格フォーマットを示す構成図。
【図１０】従来におけるディジタルデータ記録再生装置を示すブロック図。
【図１１】従来例を動作を説明するための説明図。
【図１２】ディジタルデータ記録再生装置の記録フォーマットを示す図。
【図１３】従来における８ｍｍＶＴＲの１ブロック論理ブロックを示すフォーマット。
【図１４】図１３中の誤り訂正符号領域部の構成を示す構成図。
【図１５】従来における８ｍｍＶＴＲの動作を説明するための説明図。
【符号の説明】
１…ディジタルインターフェースブロック、２…ディジタルインターフェース、
３…バッファメモリ、４…バッファコントロール部、５…μ−ＣＯＭ、
１０…コンピュータ、１０ａ…ＳＣＳＩ、１１…ＡＴＶデコーダ、
１１ａ…ＭＰＥＧ２、１２…ＡＴＭ変換器、１２ａ…ＡＴＭセル（高速ＬＡＮ）、[0001]
[Industrial applications]
The present invention provides a multimedia data recording system capable of recording and reproducing even input signals having different transmission packet formats by performing packet conversion suitable for a digital video cassette tape recorder (hereinafter referred to as a digital VTR). -It relates to a playback device.
[0002]
[Prior art]
In general, as a recording / reproducing apparatus for digitally recording information on a magnetic tape, there are a DAT (digital audio tape) for recording audio, a broadcast D1, D2, D3VTR for recording video and audio, and the like.
[0003]
In recent years, a conference for consumer digital recording VTRs has started, and standards for recording SD (STANDARD DEFINITION) signals such as NTSC and PAL and HD (HIGH DEFINITION) baseband signals on a 6 mm wide magnetic tape have been established. , Approved in 1994.
[0004]
FIG. 10 is a block diagram showing a consumer digital VTR conforming to such a standard, and FIG. 9 is an explanatory diagram showing a recording format of one track of a magnetic tape in this standard. The number of bits described in the standard track format shown in FIG. 9 indicates the number of bits of digital data before recording, and the number of bits shown on the right side of FIG. 9 indicates the number of bits during recording, that is, the number of bits after modulation. ing.
[0005]
In FIG. 10, a consumer digital VTR includes an input / output unit 40 for inputting and outputting a video signal and an audio signal or data to and from an external device, a compression / expansion unit 50 for encoding the video signal and the audio signal, and a codec. Error correcting unit 60 for performing error correction in the case of multiplexing or compounding, a recording / reproducing unit 70 for recording and reproducing on a magnetic tape, and a digital interface for optimally transmitting and supplying information recorded or reproduced to an external device And a unit 80.
[0006]
The video signal is supplied to a video processing circuit 43 via a video signal input terminal 41. The video processing circuit 43 performs A / D conversion, converts the video signal into a digital signal, and forms a frame. The shuffling circuit 51 performs a shuffling process on the framed image data in the frame and supplies the image data to a discrete cosine transform circuit (hereinafter, referred to as a DCT circuit) 52 in units of 8 pixels × 8 lines. The processing of the compression / decompression unit 50 is such that the luminance signal and the color difference signal are processed by different systems. The sampling frequency ratio between the luminance signal and the color difference signal is 4: 1, and four 8 × 8 luminance blocks and one 8 × 8 color difference block (CR, CB) have the same size. It is.
[0007]
The DCT circuit 52 converts an input signal into a frequency component by a two-dimensional DCT process. This makes it possible to reduce spatial correlation components. That is, the output (transform coefficient) of the DCT circuit 52 is supplied to the quantization circuit 53, and the quantization circuit 53 reduces the redundancy of the signal of one block by requantizing the transform coefficient with a predetermined quantization width. . In this case, the quantization circuit 53 sets a quantization width in which the low-frequency components are weighted in consideration of human visual characteristics, and performs quantization with a larger quantization coefficient for the higher-frequency components of the transform coefficients. Become Thus, signal redundancy is reduced.
[0008]
The quantized data from the quantization circuit 53 is supplied to a variable length coding circuit 54. The variable-length coding circuit 54 performs variable-length coding on the quantized output based on a predetermined variable-length code table, for example, a Huffman code table, and supplies the coded output to the outer error correcting encoder 61 of the error correcting unit 60. . As a result, short bits are assigned to data with a high appearance probability, and long bits are assigned to data with a low appearance probability, thereby further reducing the amount of transmission.
[0009]
The variable-length coded output is set to a fixed length in consideration of, for example, a case where the recorded image data is specially reproduced. In this fixed length, macroblocks composed of 4 blocks of luminance and 6 blocks of 1 block each of chrominance are collected from five discrete positions on the screen, and 5 macroblocks (hereinafter, referred to as large blocks) are used. The code amount is made constant. This makes the allocation of the code amount appropriate regardless of the pattern.
[0010]
On the other hand, the input audio signal is supplied from the audio signal input terminal 42 to the audio processing circuit 55. The audio processing circuit 55 A / D converts the input audio signal, synchronizes the input audio signal with the video signal, performs a mixing process, and supplies the mixed signal to the error correction unit 60. The error correction unit 60 encodes the compressed video data and audio data into a product code such as a Reed-Solomon code using the error correction outer encoder 61 and the error inner encoder 62, and outputs the encoded data. Thus, the compressed video data and audio data are error-correction-coded by the error-correcting outer encoder 61 and the error-correcting inner encoder 62.
[0011]
According to the standard of the consumer digital VTR, a synchronization signal (SYNC) and an ID are added to the image data that has been corrected, and data of a large block is packetized into five sync blocks and recorded. One sync block has a capacity of 90 bytes, and records data of one macroblock arranged in one sync block.
[0012]
FIG. 11 is an explanatory diagram showing this packetization.
[0013]
As described above, the macro block is composed of four luminance blocks and one color difference block each, and in the drawing, Y and C indicate recording areas of the luminance block and the color difference block, respectively. A sync signal SYNC is arranged at the head of one sync block, and an ID is arranged next. Next, a correction code (STA) and a Q number (QNO) are arranged. Here, QNO indicates a quantization value set for each macroblock, and DC is a DC value of each block in the macroblock after orthogonal transformation. Next, the data of the luminance block and the color difference block are arranged. Each recording area of the luminance block and the chrominance block is composed of 8 × m bits or 8 × n bits, and a 9-bit DC component is arranged at the head. At least, the data in the low-mid range of each block is arranged in the corresponding recording area. When excess or deficiency occurs in these recording areas, predetermined block data may be arranged in another recording area. The correction code STA indicates information in this case. Parity is added to the end of each sync block.
[0014]
Since five macroblocks are packetized into five sync blocks by the compression / decompression unit 50, the error correction encoding process in the error correction unit 60 becomes easy, which is very convenient in hardware processing. Note that the same error correction coding is performed on the audio data.
[0015]
In the standard of a consumer digital VTR, a data format to be recorded on one track is also determined. The data error-correction-coded by the error correction unit 60 is format-converted by a format conversion circuit (not shown) based on this standard. FIG. 9 shows the recording format of one track.
[0016]
The recording format of FIG. 9 has an ITI (INSERT AND TRACK INFORMATION) section, an audio section, a video section, and a synchronization section. A preamble PRE1, PRE2, PRE3, PRE4, a postamble POS1, POS2, POS3, POS4, a gap G1, G2, G3, and a margin are provided before and after these ITI, audio, video, and synchronization sections. The ITI section is arranged at the lower end of the recording area of one track, and is provided with PRE1, SSA / TIA and POS1. The audio section includes a 2-byte SYNC, a 3-byte ID code, a 5-byte auxiliary code (hereinafter, referred to as AUX), a recording area for audio data of 72 bytes (hereinafter, referred to as audio data area), and an 8-byte horizontal parity. C1 and a 77-byte vertical parity C2 are provided. The number of syncs for the AUX and the audio data area is nine, and the number of syncs for the vertical parity C2 is five.
[0017]
The video section is provided with a 2-byte SYNC, a 3-byte ID code, a 77-byte video data recording area (hereinafter, referred to as a video data area), an 8-byte horizontal parity C1, and a 77-byte vertical parity C2. An AUX consisting of 77 bytes and one sync is provided before and after the video data area. The synchronization unit has a 3-byte ID code, a 5-byte subcode, and a horizontal parity C1. With such a configuration, a recording format of one track according to the standard of the consumer digital VTR is obtained.
[0018]
In this recording format, the total number of syncs in the video section is 149 syncs as shown in FIG. 9, and the number of bytes is 90 bytes. The number of syncs in the video data area is 135, and the number of bytes is 77 bytes. That is, the bit number of the video data area before recording is 135 × 77 = 10395, excluding AUX. For example, if the data of the video portion is subjected to 24-25 modulation when recorded on a magnetic tape or the like, the data is modulated to 111750-bit data as shown on the right side of FIG.
[0019]
Therefore, the video data area of the recording format of the above-described standard satisfies the allowable area for recording the image data of the five sync blocks subjected to the packetization processing shown in FIG. The image data of the sync block can be recorded in packet units.
[0020]
Thereafter, the encoded output from the error correction unit 60 is supplied to the modulation circuit 71 of the recording / reproducing unit 70. The modulation circuit 71 modulates the input data by a modulation method suitable for high-density recording, for example, 24-25 modulation, and records the data on a magnetic tape 74 via a magnetic head 73.
[0021]
At the time of reproduction, the reproduction data from the magnetic tape 74 is supplied from the magnetic head 73 to the demodulation circuit 77 via the reproduction amplifier 75 and the equalizer 76. At this time, the equalizer 76 compensates for the amount of attenuation of the reproduced data to make the frequency characteristics uniform. The demodulation circuit 77 demodulates the reproduced data, and performs an error correction process on the demodulated data by the inner error correction decoder 63 and the outer error correction decoder 64. The video data from the non-error-correcting decoder 64 is supplied to a variable-length decoding circuit 56, and the audio data is supplied to an audio processing circuit 51a. The variable-length decoding circuit 56 performs variable-length decoding on the video data and supplies it to the inverse quantization circuit 57. The inverse quantization circuit 57 inversely quantizes the output of the variable-length decoded video data and supplies it to the inverse DCT circuit 58. The inverse DCT circuit 58 performs an inverse DCT process on the input data, thereby expanding the original coordinate axis data before the DCT process and supplying the data to the deshuffling circuit 59. For example, in the processing by the compression / expansion unit 50, processing is performed on video data by 5 SYNC block data in which 5 macro blocks, which are units of decoding, are packed. Thereafter, the variable length code is decoded in units of these five macroblocks, inverse quantization and inverse zigzag scanning are performed, and the inverse DCT circuit 58 expands the block into 8 pixels × 8 lines.
[0022]
The deshuffling circuit 59 performs deshuffling within the frame on the decompressed data to restore the original data array, and the video processing circuit 44 performs D / A conversion to obtain an analog output video signal.
[0023]
On the other hand, at the same time as the expansion of the video signal, the audio data from the decoder 64 outside the error correction is supplied to an audio data processing circuit, where the audio data is subjected to time alignment and correction processing with the video signal, and D / A converted. Obtain an analog output audio signal.
[0024]
As described above, the high-efficiency encoding technique encodes image data at a small bit rate in order to improve the efficiency of digital transmission, recording, and the like by employing orthogonal transformation, variable-length encoding, and the like. .
[0025]
In a consumer digital VTR, for example, when connecting to another digital device (external device), it is conceivable to transmit digital data to the other digital device. In this case, transmission of digital data does not cause signal degradation due to transmission in an analog state, which is extremely effective in maintaining high image quality. In particular, when dubbing between consumer digital VTRs, there is no data deterioration during dubbing and no data deterioration due to compression, resulting in a great advantage of the digital VTR.
[0026]
As described above, as an apparatus for transmitting compressed digital data without any data deterioration, there is an apparatus provided with a digital interface section 80 in front of the error correction section 60 as shown in FIG. For example, at the time of reproduction, the video data and the audio data from the error correction unit 60 are supplied to a digital interface packet processing circuit (hereinafter, referred to as a D-IF packet processing circuit) 81 of the digital interface unit 80. The D-IF packet processing circuit 81 performs a packet conversion process on video data and audio data using the buffer memory 82. Thereafter, the packetized data is supplied to an I / F unit 83, which is divided into blocks for transmitting digital data to an external digital device (not shown), and transmitted from a terminal 47 to a digital interface of another digital device. I do. At the time of recording, the input data is similarly processed into blocks and packets, and transmitted to the error correction unit 60. The μ-COM 84 connected to the I / F unit 83 is a control circuit that performs servo control on the deck side during recording or reproduction based on input data.
[0027]
As described above, a method of transmitting a packet from a consumer digital VTR to another digital device is specified in the consumer digital standard. This transmission packet structure is generally standardized, and the transmission of data recorded on one track is specified by the data structure shown in FIG. 12 to be input / output from the I / F section of the digital interface.
[0028]
FIG. 12 is an explanatory diagram for explaining a transmission packet structure in the digital interface. As shown in FIG. 12, in the packet structure, first, a header 1 SYNC, a subcode 2 SYNC, and a video auxiliary code (V-AUX) 3 SYNC are transmitted. After that, 1 SYNC of the audio data and 15 SYNC of the video data are transmitted, and 16 SYNC of the audio data and the video data are repeated nine times to transmit the recording data of one track. In other words, in order to input / output video data to / from an external device, if data of 1 SYNC, which is 3 bytes of ID data and 77 bytes of video data, is considered as one video packet of 15 SYNC, 9 data packets are recorded in one track period. Is transmitted.
[0029]
By the way, digital VTRs for consumer use are designed so that signals of digital broadcasts (ADVANCED TELEVISION, hereinafter referred to as ATVs), which are the next-generation broadcasts in the United States, can be recorded in the same recording format as SD signals as data compressed signals. A standard for a simple bit stream interface is currently under consideration by the Digital VTR Council. According to this standard, an ATV bit stream signal is converted into a packet through a digital interface, and is recorded in the same recording format as the SD signal.
[0030]
Further, as an application of digital tape recording / reproducing equipment, the use as a data streamer capable of recording a large amount of digital data is spreading from the point that the recording capacity of the tape is extremely advantageous as compared with other recording media. Such a data streamer includes, for example, a device using a 1/2 inch tape called QIC as a backup device for a workstation, a device using a DAT (4 mm), or a data of a computer or a hard disk using an 8 mm tape. There is a data streamer for backup.
[0031]
For example, as a technique for using an 8 mm tape deck as a data streamer, there is a technique that has already been proposed in the document of US Patent US Pat. No. 5,142,422 (Japanese Publication No. 5-500683, Invention Title: Dual Channel Spiral Scanning Recorder). .
[0032]
According to the technology according to this proposal, as shown in FIG. 13, a header portion for recording identification and length information of a logical data block is arranged at 14 bytes, and then a 1024 byte data area portion and 400 bytes of error correction are arranged. An ECC area and a 2-byte CRC area are arranged. That is, the format is such that eight physical blocks each consisting of a header part, a data area part, an error correction part and a CRC area part are recorded in one track of the tape. In this format, for example, if a logical block has a maximum of 1024 bytes, one physical block is constituted by one logical block when the logical block is 1024 bytes. In addition, when it is 512 bytes, it is composed of two logical blocks, and when it is 256 bytes, it is composed of four logical blocks. That is, the break of the logical block is a convenient number. The configuration of the error correction ECC area shown in FIG. 13 is such that, as shown in FIG. 14, in each of the header, data area, and CRC horizontal blocks (C1 direction), an error-coded 160-byte horizontal parity is arranged. In the vertical direction (C2 direction), a 240-byte vertical parity is arranged. However, the format according to this proposal has a disadvantage that it cannot be used for other purposes since it is a format devised exclusively for a data streamer using an analog 8 mm VTR tape.
[0033]
Normally, the data recording capacity of a consumer digital VTR is several to ten times that of a conventional DAT or 8 mm tape. Therefore, even if only the video area of the recording format is recorded, the recording capacity is about 55 GB (gigabyte), and the transfer rate is 3.1 MG (megabyte) / sec, which is significantly higher than the conventional one. Therefore, a consumer digital VTR is most suitable for a streamer of data such as video, and it is expected that demand will further increase in the future. However, if the recording format is determined exclusively for the data streamer as in the case of 8 mm as described above, the recording device will be a computer-only recording device.
[0034]
Considering the future use of data streamers, for example, image compression signals based on the MPEG2 (MOTION PICTURE GROUP PHASE 2) system, which is an international standard system for which application products are widely used as image compression systems for discs and digital broadcasts, are rapidly spreading. It records data or records data transmitted through ATM (ASYNCHRONOUS TRANSFER MODE), which has rapidly spread as multimedia data transmission technology such as video and audio for ISDN (Integrated Services Digital Network) and high-speed LAN. It is assumed that it is used as a multimedia data streamer. In this case, each packet is transmitted / exchanged by dividing it into fixed-length packets. That is, this is to facilitate hardware processing and increase the speed. However, in order to transmit and record to a recording device corresponding to a plurality of types of transmission forms, it is indispensable to record the original packet without destroying it. That is, if a format suitable for each transmission mode is separately set, the circuit configuration becomes complicated, and there arises a problem that a dedicated device corresponding to each application must be separately developed.
[0035]
Therefore, as a demand in the future, a device that supports various multimedia data, which is a format suitable for various transmission modes, is desirable. However, the recording format of a consumer digital VTR (6 mm tape), which is a current large-capacity recording device, does not support recording directly on each packet of different types of media. For example, one packet of MPEG2 has 188 bytes, one cell of ATM has 48 bytes, and 1024 bytes which is an example of a logical block from SCSI, the data area which can be recorded in 1SYNC of the digital VTR is shown in the video data area of FIG. Is 77 bytes. That is, if recording is performed as it is, the original packet will be cut off in the middle, the number of SYNCs for each packet will not match, and the size of the transmission unit will be different. As a result, there is a problem that recording and reproduction cannot be performed according to a plurality of types of transmission packet forms.
[0036]
[Problems to be solved by the invention]
As described above, the conventional data slitter cannot perform packet conversion according to the transmission packet form of the input signal, so that when input data having a different transmission packet form is supplied, normal recording or reproduction can be performed. There was a problem that it was not possible.
[0037]
Therefore, the present invention has been made in view of the above-described problems, and performs multimedia data that can be recorded and reproduced by performing packet conversion suitable for a digital VTR even when input data having different transmission packet formats is supplied. The purpose is to provide a recording / reproducing device.
[0038]
[Means for Solving the Problems]
A multimedia data recording apparatus according to claim 1, wherein the recording means is capable of recording data on a recording medium of a format having a fixed data length and a fixed number of sync blocks as a recording unit; Switch means for selecting and outputting predetermined input data from among one or more different input data; buffer memory for storing the input data selected by the switch means in the format thereof; Control means for reading and outputting the input data stored in the buffer memory, with the data length being the data length based on the packet capacity of the input data as a read unit, and read by the control means. Type of the format of the input data for each read unit in the input data. And adding means for outputting by adding to the header, supplied to the data the recording means by packetizing the read unit from the adding means, der those equipped with packetization means for recording, theYou.
[0039]
[Action]
In the first aspect of the present invention, one of a plurality of input data having different formats is selectively input by the switch means. The buffer memory stores the selected input data, and reads data from the buffer memory in units of a predetermined number of sync blocks by the control means. At this time, the adding unit adds a header indicating the format type of the input data for each read unit and outputs the data. The packetizing unit sequentially records the physical blocks in a predetermined recording unit of the recording medium, with the data of the read unit from the adding unit as one physical block unit.
[0041]
【Example】
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0042]
FIG. 1 is a block diagram showing a first embodiment of a multimedia data recording / reproducing apparatus according to the present invention. This apparatus shows a consumer digital VTR which performs recording / reproducing using, for example, a 6 mm magnetic tape. . 1, the same components as those in FIG. 9 are denoted by the same reference numerals.
[0043]
In this embodiment, data from another digital device is input / output via the digital interface block 1. Data supplied from a digital device includes, for example, data supplied from a computer or the like via an interface such as a serial SCSI (SMALL COMPUTER SYSTEM INTERFASE), data transmitted from an ATV decoder through packet compression by MPEG2, and an ATM converter. There are data and the like transmitted using ATM such as ISDN and high-speed LAN. Therefore, in this embodiment, a case will be described in which data is transmitted using a computer and a SCSI cable or a serial SCSI cable which is currently being studied for high-speed transfer, and is supplied to the digital VTR shown in FIG.
[0044]
In the case of a consumer digital recording VTR using a 6 mm magnetic tape, the recording area for recording data in accordance with a standard physical format is generally recorded in a video area in order to maintain system compatibility. is there. For example, it is conceivable to record the data in an audio area. However, since the error correction capability is different for voice and video, it is rare that the same type of data is given a code having a different error correction capability. Therefore, in the present embodiment, it is assumed that recording is performed only in the video data area of the standard format shown in FIG.
[0045]
In FIG. 1, data from a computer 10 is transmitted via a SCSI cable or a serial SCSI 10a cable, and the transmitted data is supplied to a digital interface 2 (hereinafter abbreviated as I / F) of a digital interface block 1. At the subsequent stage of the digital interface block 1, an error correction outer encoder 61, an error correction inner encoder 62, a modulation circuit 71, a recording / reproducing amplifier 78, a PLL equalizer 76, a demodulation circuit 77, an error correction inner decoder 63, and an error correction A circuit group constituted by the outer decoder 64 is constituted. Such a circuit configuration is the same as that of the ordinary video / audio recording / reproducing circuit shown in FIG. 10 described in the related art, but the input / output unit and compression / decompression unit shown in the block diagram of FIG. Is omitted. That is, it is a circuit for recording and reproducing using the standard track format shown in FIG. 9 in the prior art.
[0046]
Input data from the I / F 2 is supplied to the outer error correcting encoder 61. The error correcting outer encoder 61 adds an error correcting code of the outer code (149, 138, 12) of the standard track format (see FIG. 9) to the compressed data, and thereafter, the inner code (85, 77) is output by the error correcting inner encoder 62. , 9) are further added. The outer error correcting encoder 61 and the inner error correcting encoder 62 encode the compressed data into a product code such as a Reed-Solomon code and output the encoded data. This results in formatting into a code configuration as shown in FIG.
[0047]
The data (coded output) to which the error correction code is added is supplied to the modulation circuit 71. The modulation circuit 71 modulates the supplied data by a modulation method suitable for high-density recording, for example, a 24-25 modulation method, and generates a tracking pilot signal by the recording code string itself and sends it to the recording / reproducing amplifier 78. Supply. The recording / reproducing amplifier 78 performs a recording / reproducing process necessary for recording data on a magnetic tape via a magnetic head (not shown), and supplies the data to the magnetic head. Thereafter, recording is performed on a magnetic tape having a width of 6 mm by a magnetic head.
[0048]
At the time of reproduction, reproduction data from a magnetic tape is supplied to a recording / reproduction amplifier 78 via a magnetic head. The recording / reproducing amplifier 78 uses a PLL equalizer 76 to perform a reproducing process necessary for reproducing the reproduced data, and supplies the data to a demodulation circuit 77. At this time, the equalizer 76 compensates for the amount of attenuation of the reproduced data to make the frequency characteristics uniform. The demodulation circuit 77 demodulates the reproduced data by, for example, a 25-24 modulation method, and performs an error correction process on the demodulated data by the inner error correction decoder 63 and the outer error correction decoder 64. The video data from the error-correction outer decoder 64 is output to an external digital device via the digital interface block 1.
[0049]
Next, a description will be given of a means for performing packet conversion according to an input packet transmission mode and a configuration of a recording format which are features of the present invention.
[0050]
In the present embodiment, a case where data is transmitted by, for example, a transmission method using a SCSI cable 10a is shown as a data streamer connected to the computer 10 or its peripheral device for data transmission. As described above, the input signal supplied from the digital interface 2 may not only be transmitted in the form of transmission by the SCSI cable 10a, but may also be input in the form of data transmitted in various transmission forms. For this reason, as described in the prior art, it is desirable for the purpose of the present invention to have a system that can cope with various transmission modes. As other various transmission forms, a transport stream 11a of MPEG2, which is an international standard image compression, which is to be adopted in digital broadcasting in the United States and Europe for multimedia handling video and audio data and the like, and ISDN ( A transmission form using an ATM communication network (ATM cell) 12 used in a digital communication network or a high-speed LAN can be considered.
[0051]
Therefore, in the multimedia data recording / reproducing apparatus according to the present embodiment, the digital interface 2 of the digital interface block 1 is provided with a changeover switch 6 for selecting various data transmitted in various transmission modes. The changeover switch 6 arbitrarily switches data transmitted in one transmission mode from data transmitted in various transmission modes and supplies the data to the buffer control unit 4. The buffer control unit 4 performs packet conversion based on the transmission form of the supplied data, and controls reading or writing from the buffer memory 3 connected to the control unit 4. The output of the buffer control unit 4 is supplied to an error correcting outer encoder 61. The μ-COM 5 connected to the digital interface 2 transmits a control signal to the servo control unit 79 of the recording / reproducing apparatus for setting a recording state, for example, when receiving a data recording instruction from the computer 10. Output and drive control. As described above, in the multimedia data recording / reproducing apparatus of the present embodiment, data transmitted by one of the various transmission modes to be input can be input / output.
[0052]
Next, a description will be given of a format according to the present invention which is common and compatible with a recording format of a data streamer which can support SCSI even when inputting / outputting data transmitted by various transmission modes.
[0053]
First, in the case of a data streamer such as a multimedia data recording / reproducing apparatus shown in FIG. 1, data transmitted from a peripheral device such as a computer 10 or a hard disk via a connected SCSI 10a is usually called a logical block by a SCSI command. The data is logically divided and transmitted in units of blocks having a size of 2 m. In this case, the user generally designates a logical block length of 1024 bytes, 512 bytes, 256 bytes, 128 bytes or the like depending on the type of application, and sets the logical block length to be larger as the transfer capacity is larger. It is common. Since the digital VTR for consumer use has an extremely high transfer rate as compared with the conventional recording / reproducing apparatus, the logical block transmission of about 1024 bytes is mainly performed at the highest transfer rate. Therefore, it is desirable to provide an appropriate format for a logical block of 1024 bytes or less.
[0054]
On the other hand, as described in the prior art, in a consumer digital VTR having an image input / output unit for analog input / output, the compression / expansion unit (see FIG. 10) connected to the error-correcting outer code decoder is not shown in FIG. As shown in FIG. 11, five macroblocks have a fixed length, are packetized into 5SYNC blocks, and data is transmitted. Of the digital data input / output via the digital interface, video data is input / output continuously in units of 15 SYNC as shown in FIG. Therefore, the data input / output processing of the error correction outer code decoder for video data is performed, for example, in such a manner that data is continuously transmitted in units of 5 SYNC blocks or in units of 5 SYNC blocks × 3 = 15 SYNC blocks. In the case of the digital interface block connected to the decoder and the compression / decompression unit, the processing of the input / output unit of the error-correcting outer code decoder for the transmitted data can be performed in common.
[0055]
Therefore, in order to packetize 1024 bytes, 1 SYNC 77 bytes of the consumer digital VTR is converted into a 15 SYNC 1 packet which is three times 5 SYNC, which is one physical block. FIG. 2 shows the configuration of this physical block that has been packetized.
[0056]
As shown in FIG. 2, as described above, when 1 SYNC 77 bytes of the consumer digital VTR standard is converted into a 15 SYNC 1 packet which is three times 5 SYNC, as described above, 1 048 bytes of data One physical block from which the area is obtained. Also, for example, a header of 24 bytes is added to one block of input logical data. In the header part, for example, a value indicating a block format (user data, file mark, gap, etc.), a value indicating a method of storing block information, a series number of a logical block, a series number of a physical block, An ID indicating a block size or the like is included.
[0057]
FIG. 4 is a configuration diagram showing a specific example of an input logical data block in one physical block of 1155 bytes. The diagram shown in the upper part of FIG. 4 shows a case where the input logical data block is designated by 1024 bytes. FIG. 4 shows a case where the data is designated by 512 bytes, and FIG. 4B shows a case where the data is designated by 256 bytes.
[0058]
It is assumed that the size of the input logical data block is specified to be 1024 bytes. In this case, as shown in the upper part of FIG. 4, one physical block is provided with one logical block. That is, one logical block is composed of 1024 bytes of data, 24 bytes of header, and 107 bytes of invalid data.
[0059]
It is also assumed that the size of the input logical data block is specified to be 512 bytes. In this case, as shown in the middle part of FIG. 4, one physical block has two logical blocks. That is, two logical blocks of 512 bytes of data are provided, a header of 24 bytes is added to the head, and a two-byte SYNC is provided between the two logical blocks. Further, 105 bytes of invalid data are arranged in the last column.
[0060]
Further, it is assumed that the size of the input logical data block is specified to be 256 bytes. In this case, as shown in the lower part of FIG. 4, one physical block has four logical blocks. That is, four logical blocks of 256 bytes of data are provided, a header of 24 bytes is added in the same manner as described above, a 2-byte SYNC is provided between each logical block, and 101 bytes of invalid data is further provided in the last column. Arrange and configure. In this way, one physical block of 15 SYNC1 packets is configured.
[0061]
Next, the operation of the digital interface block shown in FIG. 1 will be described.
[0062]
Now, it is assumed that the data transmitted by the SCSI 10a is supplied to the changeover switch 6 from the computer 10 shown in FIG. Then, in this embodiment, since data based on the transmission form by SCSI is supplied, the changeover switch 6 selects data transmitted by SCSI from among various transmission forms and supplies the data to the digital interface 2. I do. The changeover switch 6 can be set arbitrarily according to the user's desire.
[0063]
When the device shown in FIG. 1 is a data slitter of a digital recording VTR, the digital interface 2 is a SCSI I / F circuit 2. The SCSI / I / F circuit 2 blocks the data transmitted from the computer into units specified by the user. That is, when 256 bytes are designated, the block is divided into 256-byte data units, and when 1024 bytes are designated, the block is divided into 1024-byte units. Then, the blocked data is supplied to the buffer memory 3 via the buffer control unit 4 at the next stage. The buffer memory 3 has a buffer memory size much larger than the logical block. Further, the buffer memory 3 is used to record data at a constant rate by the recording unit of the data streamer device, or to transmit data reproduced at a constant rate from the reproducing unit to the computer in logical block size units. Adjust (buffer) time and time.
[0064]
Now, it is assumed that the tape recording / reproducing unit has been stopped. At this time, when a data storage request is transmitted from the computer 10, the μ-COM 5 drives and controls the servo control unit 79 on the recording / reproducing apparatus side (deck side) to start shifting the operation to the recording state. Then, data input in logical block units from the computer 10 is buffered in the buffer memory 3 via the SCSI I / F 2 and data of a predetermined number of bytes is transmitted during a predetermined time.
[0065]
For example, assuming that the time from when the tape recording / reproducing unit stops to when the tape running reaches the steady state is 1 second, and the data transfer speed between the error-correcting outer encoder 61 and the buffer memory is 3.1 Mbytes. In this case, after 3.1 Mbytes of data are buffered in the buffer memory 3, the data is output from the buffer memory 3 to the error-correcting outer encoder 61, and processing necessary for recording thereafter is performed. Record on tape. At this time, if there is more data, the recording is further continued.
[0066]
The operation of the buffer control unit for outputting from the buffer memory 3 to the error correcting outer encoder 61 will be described in detail with reference to FIG. FIG. 5 is a configuration diagram showing a specific configuration of the buffer control unit 4.
[0067]
In FIG. 5, when reading and outputting input data from the buffer memory 3, the buffer control unit 4 performs packet conversion so as to output data divided by a predetermined number of bytes (76 bytes). A 24-byte logical block header generating circuit 4b for generating a 24-byte header in order to add a 24-byte header to the head of this data; a 3-byte ID and a header for each sink In order to add 1 byte, a sync header / ID 3-byte generating circuit 4c for generating a 3-byte ID and a 1-byte sync header and an area where data is insufficient when 15 block data are configured Invalid data generation circuit that generates invalid data to fill in invalid data And d, in make up. Note that the data array before the 3-byte ID is added may be, for example, an array of invalid data from the previous I / F 2 shown in FIG.
It is assumed that data transmitted from the computer 10 via the SCSI 10a is divided into blocks by the SCSI I / F 2 and supplied to the buffer memory 3. Then, the memory controller / packet conversion control circuit 4 a reads out the data from the buffer memory 3 in units of 76 bytes and outputs the data to the adder 14. Thereafter, a 24-byte header generated by the 24-byte logical block header generating circuit 4b is added to the head of this data using the adder 14, and the added data is supplied to the adder 15. Further, an adder 15 adds a 3-byte ID generated by the sync header / ID 3-byte generating circuit 4c and a 1-byte header (packet identification ID and series number in a physical block) for each sync. Finally, the adder 16 multiplexes the data from the buffer memory 3 with the data delimited by 76 bytes to form 1 SYNC block data. At this time, the memory controller / packet conversion control circuit 4a controls so as to output fifteen 1SYNC blocks. In this case, if the logical block ends in the middle of 1024 bytes of valid data, an eob mark is added, and the remaining data is output as invalid data. Even when the input logical block is 256 bytes, 512 bytes, or 1024 bytes, the method of reading from the buffer memory 3 is always the same. Thereby, the data of one physical block supplied to the error correcting outer encoder 61 is as shown in FIG.
[0068]
The capacity of the data area in one physical block corresponding to 15 SYNCs configured as described above is such that the data area in one SYNC is 76 bytes because one byte is added for each packet type and the series number in the physical block for each sink. Then
76 bytes x 15 = 1140 bytes
It becomes.
[0069]
Therefore, the capacity of the data area at the time of input is

Therefore, the capacity of the data area at the time of input can be included in one physical block area. The surplus area may be arranged as invalid data, or may be configured as a system for adding an ECC in physical block units as an option for improving reliability.
[0070]
As a result, since the video data area in the consumer digital VTR is 135 SYNC per track, it is possible to record nine physical blocks each composed of one 15 SYNC block as shown in FIG. Note that the error correction code by the error correction outer encoder 61 is added to the data in 9 blocks (+ SYNC of 3 VAVA) corresponding to the video data area of one track to be recorded.
[0071]
At the time of reproduction, processing opposite to the processing at the time of recording is performed. That is, after the error correction of the reproduced data for one track (135 SYNC + VAUX 3 SYNC) is performed by the error correction outer decoder 64, the data is transmitted to the buffer memory 3 by 15 SYNC data at a time. Then, after decoding the header 24 bytes and decoding the packet identification and the sync series No. by the header 1 byte of each sync, the valid data of each sync 76 bytes is written to the buffer memory 3 in order of 15SYNC. In this way, 1024 bytes of valid data are written to the buffer memory 3. Similarly, 1024 bytes of valid data from the next block are written into the buffer memory 3 and (1024 × 9 bytes) data is written into the buffer memory 3 from data of 9 blocks per track. In this case, the write control to the buffer memory 3 is performed by the buffer control unit 4 as in the recording. Further, the data transfer speed from the error-correction outer decoder 64 to the buffer memory 3 is set to be the same as the recording speed, that is, 3.1 Mbytes / sec.
[0072]
Therefore, according to the present embodiment, the data transmitted through the SCSI from the computer or the like is converted into the physical format of 15 SYNC × 9 blocks, thereby recording and reproducing without breaking the original packet configuration. It has the effect of being able to.
[0073]
In the data streamer of this embodiment, the SCSI cable has been described as a transmission method for inputting / outputting computer data from a computer. However, the present invention is not limited to this, and transmission may be performed using another type of cable. good. For example, transmission may be performed by using a serial SCSI system such as P1394 capable of high-speed transfer.
Next, a multimedia data recording / reproducing apparatus according to a second embodiment of the present invention will be described with reference to FIGS.
[0074]
In the present embodiment, it is an object of the present invention to record and reproduce input data in packet units through different types of transmission paths in a physical format of 15 SYNC × 9 blocks without breaking the original packet configuration. In order to achieve the above, a case will be described in which input data is supplied in a transmission form different from that of the above embodiment. For example, a digital interface of a multimedia data recording / reproducing device as a data streamer is connected to the ATV decoder 11 shown in FIG. 1, and data is input / output in a transmission form of the MPEG2 system. In other words, this is a case where the transport stream of MPEG2 is converted into the transmission packet of the present invention, transmitted to the error-correcting outer code decoder, and recorded or reproduced in the same physical block format as in the above embodiment and output. .
[0075]
FIG. 7 is an explanatory diagram for explaining the packet conversion processing of the present invention in the case of the transmission mode according to the MPEG2 system.
[0076]
Now, it is assumed that data transmitted by the MPEG2 system is supplied to the changeover switch 6 from the ATV decoder 11 shown in FIG. Then, in this embodiment, since data based on the transmission form by MPEG2 is supplied, the changeover switch 6 selects the data transmitted by MPEG2 from among various transmission forms and supplies the data to the digital interface 2. I do. At this time, the data supplied to the digital interface 2 is transmitted from the ATV decoder 11 or the like as an MPEG2 transport stream packet. The packet size of the transport stream of MPEG2 is 188 bytes as shown in FIG. In other words, in the case of the present example, since the packet is transmitted by being divided into packets, error propagation is small and hardware processing becomes easy. In other words, it is important to transmit a packet without breaking it.
[0077]
Therefore, the fact that it is convenient to convert these two packets (188 × 2 = 376 bytes) to the 5SYNC size (385 bytes) of the digital VTR has already been studied by the digital VTR conference. Therefore, as shown in FIG. 7, a header is added to the head of each sink. In this case, the header is composed of the identification 4 bits of the MPEG2 packet and the sync series No. 4 bits, that is, a 1-byte header. Also, a one-byte mark is added to the connection of two packets, and the last three bytes of the fifth SYNC are arranged as invalid data.
[0078]
Also in this case, in FIG. 1, in response to the data input from the ATV decoder, the MPEG2 packet is converted into 5 SYNC units in the buffer memory 3, and 5 SYNCs are arranged in 3 units from the buffer memory 3 and read out in 15 SYNC units, As described above, the timing can be adjusted to the timing of every 15 SYNC which is the video data area timing of the digital interface of the error correcting outer encoder 61. Hereinafter, as in the case of the data streamer in the above embodiment, it is possible to record in the recording format shown in FIG. 3 in the form of 15 SYNC × 9 blocks. That is, the MPEG2 transport stream per block can be recorded as 6 packets, that is, as 54 packets per track.
[0079]
On the other hand, at the time of reproduction, the reproduction process is performed in the same manner as in the first embodiment. That is, data is read out from the error-correction outer decoder 64 in units of 15 SYNC, only the valid data portion is written into the buffer memory 3, and 5 SYNC data is read from the buffer memory 3 and 2 MPEG2 packet data is read. Thus, the digital VTR can output to the ATV decoder 11 an ATV packet which is an MPEG2 bit stream.
[0080]
Therefore, also in the present embodiment, by performing the packet conversion according to the present invention as in the first embodiment, there is an effect that the data transmitted from the ATV decoder in the MPEG2 system can be recorded and reproduced.
[0081]
Next, a third embodiment of the multimedia data recording / reproducing apparatus according to the present invention will be described with reference to FIGS.
[0082]
In this embodiment, an ATV converter 12 shown in FIG. 1 is connected to a digital interface of a multimedia data recording / reproducing apparatus as a data streamer, and an MPEG2 transport stream is transmitted over an ATM network such as ISDN or high-speed LAN. Data is input and output using the (hereinafter referred to as ATM cell) 12a. That is, the packet format for transmitting the MPEG2 transport stream by the ATM cell 12a is converted into the transmission packet of the present invention, transmitted to the error-correcting outer code decoder, and recorded in the same physical block format as in the above embodiment. Or play and output.
[0083]
FIG. 8 is an explanatory diagram for explaining the packet conversion processing of the present invention when the transport stream of the MPEG2 system is transmitted using ATM cells.
[0084]
Now, it is assumed that data in which a transport stream of the MPEG2 system is transmitted from the ATM converter 12 shown in FIG. 1 in the form of transmission by the ATM cell 12a is supplied to the changeover switch 6. Then, in this embodiment, since data based on the transmission form by the ATM cell 12a is supplied, the changeover switch 6 selects the data transmitted by the ATM cell 12a from among various transmission forms, and Supply to interface 2. At this time, the data supplied to the digital interface 2 is such that an MPEG2 transport stream is transmitted from the ATV converter 12 in the ATM cell transmission system.
[0085]
For example, it is assumed that the ATM cell 12a is set in the case of AAL5 for data communication. Then, in this case, one cell is 48 bytes as shown in FIG. For this reason, since the transport stream packet of MPEG2 is 188 bytes per packet as described in the above embodiment, the transport stream packet of MPEG2 can be transmitted by four ATM cells.
[0086]
Therefore, as described in the second embodiment, two MPEG-2 transport stream packets are transmitted by eight ATM cells in such a manner that packet conversion into digital VTR SYNC units is performed. At this time, an 8-byte ATM transmission overhead (CONVERGENCE SUBLAYER) is added to the last part of the 376-byte transport stream as shown in FIG. In other words, the ATV cell 12a transmits data in 384 bytes. However, since the 8-byte ATM transmission overhead is data only during transmission, the data is written in the buffer memory 3 shown in FIG. Data will be written.
[0087]
Thereafter, the 376-byte data is converted from the buffer memory 3 into packets of 5 SYNC by the memory control / packet conversion control circuit 4a shown in FIG. In the subsequent processing, a 1-byte header is added to the head of each sink, as in the second embodiment. In this case, the header is composed of 4 bits for identification of the ATM packet and 4 bits for the sync series number, and is a 1-byte header.
[0088]
Also in this case, the data input from the ATM converter 12 such as the B-ISDN shown in FIG. 1 is converted into 5SYNC units by the buffer memory 3, and three 5SYNCs are arranged from the buffer memory 3 and read in 15SYNC units. This makes it possible to match the timing of every 15 SYNC which is the video data area timing of the digital interface of the error correcting outer encoder 61. Hereinafter, similarly to the case of the data streamer of the SCSI transmission in the first embodiment, it is possible to record in the format of 15 SYNC × 9 blocks of the recording format shown in FIG. That is, the number of ATM cells per block is 24, that is, 216 cells can be recorded per track.
[0089]
On the other hand, at the time of reproduction, the reproduction processing is performed in the same manner as in the first embodiment. That is, the data is read out from the error-correction outer decoder 64 in units of 15 SYNC, only the valid data part is written into the buffer memory 3, and the data corresponding to 5 SYNCs are read out of the buffer memory 3 in units of 48 bytes of ATM cells. As a result, it is possible to output from the digital VTR to the ATM converter 12 in the form of transmission by the ATM cell 12a for every two packet data of MPEG2.
[0090]
Therefore, also in this embodiment, by performing packet conversion according to the present invention in the same manner as in the first embodiment, recording and reproduction of data transmitted from the ATV converter 12 in the form of transmission of the MPEG2 transport stream by the ATM cell. Can be performed.
[0091]
In the first to third embodiments of the present invention, a description has been given of the case where a changeover switch is provided to arbitrarily select and switch input data transmitted in a plurality of different transmission modes at the time of input. This switch may determine the code of the transmission type recorded at the head of the reproduced data at the time of output such as reproduction of the digital VTR, and switch based on the result of the determination. As a result, it is apparent that the device can function as a multimedia data recording / reproducing device that can handle input / output data in a plurality of different transmission forms.
[0092]
【The invention's effect】
As described above, according to the present invention, even in a plurality of input / output data in different transmission modes, a logical block can be converted into a packet suitable for a digital VTR without destroying the input data transmission method and recording format as it is. Can be recorded and reproduced. Therefore, there is an effect that recording and reproduction can be performed not only for a data streamer dedicated to a computer but also for data transmitted in different transmission forms from other digital devices.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of a multimedia data recording / reproducing apparatus according to the present invention.
FIG. 2 is an explanatory diagram illustrating a packet conversion process according to the present invention.
FIG. 3 is a diagram showing a physical format for one track according to the present invention.
FIG. 4 is a diagram showing a packetized logical block according to the present invention;
FIG. 5 is a configuration diagram showing a configuration of a buffer control unit in FIG. 1;
FIG. 6 is an explanatory diagram for explaining an operation of a buffer control unit in FIG. 5;
FIG. 7 is an explanatory diagram for explaining a multimedia data recording / reproducing apparatus according to a second embodiment of the present invention.
FIG. 8 is an explanatory diagram for explaining a third embodiment of the multimedia data recording / reproducing apparatus according to the present invention.
FIG. 9 is a configuration diagram showing a standard format of a conventional digital data recording / reproducing apparatus.
FIG. 10 is a block diagram showing a conventional digital data recording / reproducing apparatus.
FIG. 11 is an explanatory diagram for explaining the operation of the conventional example.
FIG. 12 is a diagram showing a recording format of a digital data recording / reproducing device.
FIG. 13 is a format showing one logical block of a conventional 8 mm VTR.
FIG. 14 is a configuration diagram showing a configuration of an error correction code area unit in FIG. 13;
FIG. 15 is an explanatory diagram for explaining an operation of a conventional 8 mm VTR.
[Explanation of symbols]
1. Digital interface block 2. Digital interface
3 ... buffer memory, 4 ... buffer control unit, 5 ... μ-COM,
10 ... computer, 10a ... SCSI, 11 ... ATV decoder,
11a: MPEG2, 12: ATM converter, 12a: ATM cell (high-speed LAN),

Claims (5)

Recording means capable of recording data on a recording medium having a fixed data length and a fixed number of sync blocks as a recording unit,
Switch means for selecting and outputting predetermined input data from one or more input data different from the format,
A buffer memory for storing the input data selected by the switch means in the format thereof;
Control means for reading and outputting the input data stored in the buffer memory, with the data length being an integer fraction of the fixed sync block number and based on the packet size of the input data as a read unit; ,
Adding means for adding a header indicating the type of format of the input data to the input data read by the control means for each read unit, and outputting the input data;
Packetizing means for packetizing the data of the read unit from the adding means and providing the data to the recording means, and recording the data;
A multimedia data recording device, comprising: The control means sets the read unit to 15 sync blocks,
2. The multimedia data recording apparatus according to claim 1, wherein said packetizing means records 9 physical blocks of data in a predetermined recording unit of said recording medium. The input data is SCSI standard data in which the maximum unit of a logical block is 1024 bytes,
3. The control unit according to claim 2, wherein the control unit allocates a maximum unit of a logical block to 15 sync blocks of the read unit, thereby enabling the recording unit to record the data of the SCSI standard. Multimedia data recording device. The input data is an MPEG2 bit stream,
The control means enables the recording means to record the MPEG2 bit stream by associating two packets of input data with five sync blocks and setting 15 sync blocks as a read unit. The multimedia data recording device according to claim 1. The input data is an ATM data cell,
The control means enables the recording means to record the data cells of the ATM system by making 8 data cells of the input data correspond to 5 sync blocks and setting 15 sync blocks as a read unit. The multimedia data recording device according to claim 1, wherein

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