JP3556309B2 - Computer system and I/O control device used in the system - Google Patents

Description

[0001]
[Industrial application field]
The present invention relates to a computer system, and more particularly to a computer system including an I/O device whose hardware resources are changeable, and an I/O control device used in the computer system.
[0002]
2. Description of the Related Art
In recent years, various types of portable personal computers, such as notebook or laptop type computers, have been developed that are easy to carry and can be operated by batteries. These types of personal computers are provided with expansion connectors for connecting expansion devices such as option cards as necessary. As option cards, the so-called ISA card, which conforms to the ISA specification, is well known as an industry standard card.
[0003]
For this type of option card, the hardware resources required to use it (interrupt level, DMA channel number, I/O address space, etc.) are specified for each card. Most option cards also have jumpers or DIP switches that can be operated by the user, and are configured so that the interrupt level, etc. can be changed according to the settings of these jumpers or DIP switches. By operating these jumpers or DIP switches, the option card's interrupt level and DMA channel values can be set to an interrupt level and DMA channel that are not being used by other I/O devices, and the option card can be used normally.
[0004]
However, in order to correctly set the jumpers or dip switches, it is necessary to check what hardware resources are being used by all I/O devices, such as the various peripheral LSI controllers built into the portable computer, and by other option cards already connected to the expansion connector, which can be a very difficult task for the user.
[0005]
If the interrupt levels of an option card and another I/O device overlap, the CPU will not be able to distinguish which of the two devices has generated an interrupt request, and the option card will not be able to operate normally.
[0006]
Recently, development has begun on next-generation OSs that advocate the so-called Plug and Play (PNP) approach, that is, OSs that have the functionality to manage hardware resources such as interrupt levels and DMA channel numbers to be assigned to specific I/O devices built into the system. This has created a demand for the design of I/O devices that allow hardware resources to be changed.
[0007]
In order to realize an I/O device that can change such hardware resources, it is necessary to prepare an environment setting register that specifies the hardware resources to be assigned to the I/O device, and to configure the environment setting register so that information on the hardware resources specified by the OS is written.
[0008]
[Problem to be solved by the invention]
However, even in a system in which the OS has a hardware resource management function and includes an I/O device whose hardware resources can be changed, the hardware configuration of the system actually varies from model to model, so that depending on the model, it is not always possible to use the hardware resources specified by the OS.
[0009]
For example, in the case of a system that does not have an expansion bus, the number of DMA channels that should be supported by the hardware in the system is usually kept to a minimum, and in this case, there is a risk that a DMA channel specified by the OS is not actually supported, which may cause a malfunction.
[0010]
This invention has been made in consideration of these points, and aims to provide a computer system and an I/O control device that can prohibit writing to environment setting registers in a hardware manner, thereby preventing malfunctions due to changes in hardware resources without affecting the OS environment.
[0011]
Means for solving the problems and actions
The computer system of the present invention is a computer system composed of a CPU, memory, and an I/O device whose hardware resources can be changed, and is characterized in having: an environment setting register configured to be readable/writable by the CPU, and into which an operating system writes environment setting information that specifies the DMA channel and interrupt level to be assigned to the I/O device as hardware resources of the I/O device; a control register configured to be readable/writable by the CPU, and into which a system BIOS can write write lock information that specifies a write prohibition to the environment setting register; and a write prohibition circuit that prohibits writing to the environment setting register when the write lock information is written to this control register, and allows writing to the environment setting register when the write lock information is not written .
[0012]
In this computer system, the hardware resources to be allocated to the I/O devices are determined according to the contents of the configuration information written to the configuration register by the operating system, but if the system BIOS has written write lock information to the control register, a write prohibition circuit prohibits writing to the configuration register in a hardware manner , whereas if no write lock information has been written, writing to the configuration register is permitted.
[0013]
For this reason, for example, in a model that supports relatively few hardware resources, such as a system without an expansion bus, by writing default environment setting information to the environment setting register at system startup and then writing write lock information to the control register, it is possible to prohibit the OS from writing to the environment setting register thereafter. This makes it possible to prevent malfunctions caused by the specification of unsupported hardware resources. On the other hand, in a model that supports all hardware resources, if write lock information is not written, the hardware resources assigned to I/O devices can be changed as desired under OS management as usual.
[0014]
EXAMPLES
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described with reference to the accompanying drawings, in which: Fig. 1 shows the system configuration of a personal computer according to an embodiment of the present invention.
This personal computer is a laptop or notebook type system, and as shown in the figure, comprises a CPU local bus (processor bus) 10A, an ISA-compliant system bus 10B, a CPU 11, a level-shifting gate array 12, system memory 13, a display controller 14, a video memory (VRAM) 15, and a flat panel display 16 such as an LCD.
[0015]
The CPU 11 is responsible for controlling the entire system, and executes programs to be processed that are stored in the system memory 13. The CPU 11 is capable of operating at 3.3V/5V, for example, a microprocessor SL Enhanced Intel 486 manufactured and sold by Intel Corporation of the United States, and a power supply voltage of 3.3V is supplied to the CPU 11 by a power supply controller 23 described below. The CPU 11 includes a built-in cache memory with a data size of 32 bits x 4 per line. A 32-bit wide data bus, a 32-bit wide address bus, various status signal lines, etc. are defined on the local bus 10A of the CPU 11.
[0016]
The system memory 13 stores the operating system, application programs to be processed, and user data created by the application programs. The operating system (OS) used has a function for managing hardware resources (interrupt level, DMA channel number, I/O address space, etc.) of I/O devices. This system memory 13 is composed of a 5V dynamic RAM.
[0017]
The level shifting gate array 12 is connected between the 32-bit data bus defined in the CPU local bus 10A and the system memory 13, and converts the voltage level of the data signal transferred therebetween from 3.3 V to 5 V or from 5 V to 3.3 V. The voltage level conversion of the data signal is performed by a buffer circuit in the level shifting gate array 12. In addition, in order to enable asynchronous execution of the CPU bus cycle and the read access cycle of the system memory 13, the buffer circuit is provided with a data latch function for latching read data from the system memory 13.
[0018]
The display controller 14 is for controlling the display of a flat panel display 16 consisting of an STN monochrome, STN color, or TFT color LCD panel, etc., and receives display data from the CPU 11 via the CPU local bus 10A and writes it to a video memory (VRAM) 15.
[0019]
A BIOS ROM 17, a system controller 18, and an I/O controller 19 are connected to the system bus 10B.
The BIOS ROM 17 is for storing the system BIOS (Basic I/O System) and is configured with a flash memory so that the program can be rewritten. The system BIOS includes an IRT routine executed when the power is turned on, device drivers for controlling various I/O devices, a system management program, a setup program, and the like.
[0020]
The system controller 18 is composed of a bridge device that connects the CPU local bus 10A and the system bus 10B, memory control logic that controls various memories within the system, and the like.
[0021]
The I/O controller 19 controls I/O devices connected to a serial port 20 , a printer/external FDD connected to an ECP (Extended Capabilities Port) 21 which is a bidirectional parallel port, and a built-in 3.5-inch FDD 22 .
[0022]
The I/O controller 19 is composed of one LSI, and as shown in Fig. 2, it is provided with an I/O control unit 191 including an ECP control circuit 192, an I/O decoder 192, a system timer (PIT; Programmable Interval Timer) 193, two interrupt controllers (PIC; Programmable Interrupt Controller) 194, two DMA controllers 195, two UARTs 196, two floppy disk controllers (FDC) 197, and a VFO 198. The ECP control circuit 192 has a mechanism for making the interrupt level and DMA channel assigned to the parallel port (ECP) 21 programmable. The configuration of the ECP control circuit 192 is a feature of the present invention, and its specific configuration will be described in Fig. 3 and subsequent figures.
[0023]
Further connected to the system bus 10B are an internal HDD 24, a real time clock (RTC) 25, a keyboard controller (KBC) 26, a PCMCIA controller 27, a CD-ROM 34, and a sound card 35.
[0024]
The real-time clock (RTC) 25 is a clock module with its own operating battery, and has a CMOS-configured static RAM (called CMOS memory) that is constantly powered by the battery. This CMOS memory is used to store environment setting information that indicates the system operating environment.
[0025]
The keyboard controller (KBC) 26 controls a built-in keyboard 29 incorporated in the computer body, scans the key matrix of the built-in keyboard 29 to receive signals corresponding to pressed keys, and converts them into a predetermined key code (scan code).
[0026]
The keyboard controller 26 also has a function of controlling an external keyboard 30 that is optionally connected, and a function of controlling a pointing stick 31 and a mouse 32 using a dedicated processor (IPS controller) 28. The pointing stick 31 is provided integrally with the keyboard unit of the built-in keyboard 29.
[0027]
The PCMCIA controller 27 controls access to an optional JEIDA/PCMCIA PC card 33. The sound card 25 includes a PCM sound source and a digital signal processing circuit for audio signals, and is connected to a line input terminal 36, a line output terminal 37, a headphone terminal 38, a microphone terminal 39, and a joystick terminal 40.
[0028]
FIG. 3 shows the configuration of the ECP control circuit 192.
As shown in the figure, the ECP control circuit 192 comprises an ISA bus interface 201, an ECP PNP circuit 202, an I/O control circuit 203, and a slew rate control circuit 213. The I/O control circuit 203 is provided with various I/O registers such as a device control register DCR 204, a device status register DSR 205, an extended control register ECR 206, a configuration A register 207, a configuration B register 208, and the like, as well as logic 209-212 for controlling data input/output.
[0029]
The ECP PNP circuit 202 detects the DMA channel (DRQ) and interrupt level (IREQ) assigned to the parallel port (ECP) 21 according to the environment setting information set in the Configuration B register 208, and controls the interface with the bus 10B using the DMA channel (DRQ) and interrupt level. The ECP PNP circuit 202 also includes an ECP PNP control register for specifying whether to disable or enable writing to the Configuration B register 208.
[0030]
FIG. 4 shows the relationship between the ECP PNP Control Register 202 and the Configuration B Register 208.
The configuration B register 208 is an 8-bit register that can be read/written by the CPU 11, and stores information (b5-3) that specifies the interrupt level (IREQ) to be assigned to the ECP 21, and information (b2-0) that specifies the DMA channel to be assigned to the ECP 21.
[0031]
Bits b5-3 and bits b2-0 of the configuration B register 208 are normally readable/writable, but the configuration B register 208 can be made read-only by setting a write lock flag of "1" to bit 0 of the ECP PNP control register 202 of the ECP PNP circuit 202 by the system BIOS or the like.
[0032]
That is, a write lock flag of "0" is normally set in bit 0 of the PNP control register 202, and in this state, the configuration B register 208 is readable/writable, and the IREQ and DMA channels to be assigned to the ECP 21 can be changed in response to an instruction from the OS. On the other hand, when a write lock flag of "1" is set in bit 0 of the PNP control register 202, the configuration B register 208 becomes read-only, and the OS is prohibited from changing the IREQ and DMA channels.
[0033]
Next, the configuration of a write invalidation circuit for invalidating writing to the configuration B register 208 in accordance with the write lock flag will be described with reference to FIG.
[0034]
This write invalidation circuit is provided in the ECP PNP circuit 202, and is composed of two gates G1 and G2 as shown in the figure. These gates G1 and G2 are each a negative logic AND gate.
[0035]
When the CPU 11 executes an I/O write cycle to write information to the configuration B register 208, the I/O address on the bus 10B at that time is decoded by the ECP PNP circuit 202, and if the I/O address belongs to the I/O address space of the ECP 21, the IO Decode# signal becomes active. At this time, the I/O write signal IOW# on the bus 10B is also active.
[0036]
Therefore, at this time, if the write lock flag is “0”, a latch signal is supplied as a write signal to each flip-flop 301 constituting the configuration B register 208 , and the data on the bus 10 B is written to the configuration B register 208 .
[0037]
On the other hand, if the write lock flag is "1", the supply of a write signal to each flip-flop 301 constituting the configuration B register 208 is prohibited, and the I/O write cycle of the CPU 11 is invalidated.
[0038]
As described above, in this embodiment, the hardware resources (DMA channel, interrupt level) to be assigned to the ECP 21 are determined in accordance with the contents of the information written by the OS to the configuration B register 208. However, if a write lock flag of "1" is written to the ECP PNP control register 301, writing to the configuration B register 208 is prohibited in a hardware manner by the write disable circuits (G1, G2).
[0039]
For this reason, for example, when the I/O controller 19 is mounted on a model that supports relatively few hardware resources, such as a system that does not have an expansion bus, by writing default setting information to the configuration B register 208 at system startup and then writing a write lock flag of "1" to the ECP PNP control register 301, it is possible to prohibit the OS from subsequently writing to the configuration B register 208. This makes it possible to prevent malfunctions caused by the specification of an unsupported hardware resource.
[0040]
On the other hand, if the I/O controller 19 is installed in a model that supports all hardware resources, the hardware resources assigned to the ECP 21 can be changed arbitrarily under OS management as usual, provided that the write lock flag is not written to "1".
[0041]
In this embodiment, a write prohibition mechanism for changing the hardware resources of ECP21 has been described, but if the hardware resources of an I/O device are configured to be changeable, writing to the I/O register in which the hardware resources assigned to that I/O device are stored can be prohibited in a hardware manner, in a manner similar to the control of ECP21.
[0042]
For example, when the mechanism of the present invention is applied to the sound card 35 of FIG. 1, it is possible to inhibit writing to the configuration register in the sound card 35 by preparing a dedicated register corresponding to the ECP PNP control register 301 and a write disable circuit and setting a write lock flag in the dedicated register.
[0043]
Effect of the Invention
As described above, according to the present invention, the hardware resources to be assigned to the I/O devices are determined according to the contents of the environment setting information written to the environment setting register by the OS or the like, but when write lock information is written to the control register, the write prohibition circuit disables writing to the environment setting register in a hardware manner. This makes it possible to prevent malfunctions caused by the specification of unsupported hardware resources without affecting the OS environment.
[Brief description of the drawings]
FIG. 1 is a block diagram showing the system configuration of a portable personal computer according to an embodiment of the present invention.
FIG. 2 is a block diagram showing the configuration of an I/O controller provided in the system of FIG.
3 is a block diagram showing the configuration of an ECP control circuit provided in the I/O controller of FIG. 2;
4 is a diagram for explaining the relationship between an environment setting register provided in the ECP control circuit of FIG. 3 and a control register for invalidating writing to that register.
5 is a circuit diagram showing the configuration of a write invalidation circuit provided in the ECP control circuit of FIG.
[Explanation of symbols]
10A...CPU local bus (processor bus), 11...CPU, 12...level shifting gate array, 13...system memory, 14...display controller, 15...video memory, 16...flat panel display, 17...BIOS ROM, 18...system controller, 19...I/O controller, 192...ECP control circuit, 202...ECP PNP circuit, 208...configuration B register, 301...ECP PNP control register.

Claims (6)

A computer system comprising a CPU, a memory, and an I/O device whose hardware resources are changeable,
an environment setting register configured to be readable/writable by the CPU, into which environment setting information is written by an operating system, the environment setting information designating a DMA channel and an interrupt level to be assigned to the I/O device as hardware resources of the I/O device;
a control register configured to be readable/writable by the CPU, and in which write lock information for designating a write prohibition on the environment setting register can be written by a system BIOS;
A computer system comprising: a write prohibition circuit that prohibits writing to the environment setting register when the write lock information is written to the control register, and allows writing to the environment setting register when the write lock information is not written . 2. The computer system of claim 1, wherein the I/O device is a bidirectional parallel port. 2. The computer system according to claim 1, wherein the I/O device is a sound source card. The write protection circuit includes:
2. The computer system according to claim 1, wherein when the write lock information is written to the control register, a data write pulse supplied to the environment setting register in response to an I/O write cycle executed when the CPU writes the environment setting information to the environment setting register is invalidated, thereby prohibiting writing to the environment setting register. In a computer system consisting of a CPU, memory, and various I/O devices,
an I/O device configured to have changeable hardware resources;
an environment setting register configured to be readable/writable by the CPU and into which environment setting information is written by an operating system, the environment setting information designating, as hardware resources, DMA channels and interrupt levels to be assigned to I/O devices configured to be changeable by the hardware resources;
a control register configured to be readable/writable by the CPU, and in which write lock information for designating a write prohibition on the environment setting register can be written by a system BIOS;
a write prohibition circuit which permits writing to the environment setting register when the write lock information is not written to the control register, and which, when the write lock information is written to the control register, invalidates a data write pulse supplied to the environment setting register in response to an I/O write cycle executed when the CPU writes environment setting information to the environment setting register, thereby changing the access mode of the environment setting register to read-only. In an I/O control device for controlling an I/O device used in a computer system,
an environment setting register configured to be readable/writable by a CPU of the computer system, and into which environment setting information is written by an operating system, the environment setting information designating a DMA channel and an interrupt level to be assigned to the I/O device as hardware resources of the I/O device;
a control register configured to be readable/writable by the CPU, and in which write lock information for designating a write prohibition on the environment setting register can be written by a system BIOS;
and a write prohibition circuit which permits writing to the environment setting register when the write lock information is not written to the control register, and which, when the write lock information is written to the control register, invalidates a data write pulse supplied to the environment setting register in accordance with an I/O write cycle executed when the CPU writes environment setting information to the environment setting register, thereby changing the access mode of the environment setting register to read-only.

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