JP3556437B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a technology for manufacturing the same, and more particularly to a technology effective when applied to a semiconductor integrated circuit device including a planarization step in which a CMP (Chemical Mechanical Polishing) method is applied to the manufacturing process. .
[0002]
[Prior art]
As the minimum processing size of the semiconductor integrated circuit device decreases, it is necessary to improve the performance of the stepper, and the aperture diameter of the lens is increased and the exposure wavelength is shortened. As a result, the depth of focus of the exposure optical system becomes shallow, and slight irregularities on the surface to be processed also pose a problem. As a result, planarization of the surface to be processed has become an important technical problem in device processing. In addition, the above-mentioned flattening is not flattening intended to alleviate the step shape required for preventing disconnection of wiring formed on the step, but global flattening, that is, complete flattening is required. Things.
[0003]
As a technique for flattening the surface, a SOG (spin on glass) film or a low melting point glass is applied and applied by melting, a heat treatment method using a glass flow, and a surface reaction mechanism of CVD (Chemical Vapor Deposition) are applied to make the surface flattened. Although there is known a method for performing such a process, complete planarization, that is, global planarization cannot be performed in many cases due to surface conditions, conditions such as heat treatment to be applied, or restrictions on the processing thereof. Therefore, the etch-back method and the CMP method are promising as technologies that can be completely flattened practically.
[0004]
As the etch-back method, a method using a photoresist as a sacrificial film, a method using an SOG film, a method using a self-planarizing CVD film, and the like are known. However, the process complexity, cost, and reduction in yield due to particles are reduced. On the other hand, it has been generally recognized that the CMP method is an overall superior process in comparison with the problem of the etch-back method. In other words, it is considered that the CMP method is the most promising as a practical technique that can realize complete flattening.
[0005]
As an example that describes the CMP technology in detail, for example, there is “Electronic Materials”, May, 1996, p.
[0006]
[Problems to be solved by the invention]
However, in the process of studying a device surface flattening technique to which the CMP method is applied, the present inventor has recognized that there are the following problems.
[0007]
That is, a phenomenon was observed in which the remaining film thickness of the polishing film polished by the CMP method increased in the peripheral region of the semiconductor wafer, and as a result, the uniformity of the polishing film was impaired. Such non-uniformity of the polishing film may reduce exposure margin and etching margin in photolithography in a subsequent process, and may cause a reduction in the manufacturing yield of the semiconductor integrated circuit device.
[0008]
An object of the present invention is to improve the uniformity of the remaining thickness of a polishing film in a CMP process.
[0009]
It is another object of the present invention to improve an exposure margin and an etching margin in a photolithography process after a CMP process, and to improve a manufacturing yield of a semiconductor integrated circuit device.
[0010]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0011]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0012]
(1) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes a product chip region located in an effective processing region of a semiconductor wafer and in which product chips constituting the semiconductor integrated circuit device are formed; Said Located on the outer periphery of the semiconductor wafer, Said Unfinished product chips All A method of manufacturing a semiconductor integrated circuit device for processing a semiconductor wafer including a pseudo chip region where a chip is formed, comprising: Said Configure semiconductor integrated circuit devices in product chip area Convex At the same time as forming the conductive element components, Said In the pseudo chip area Said Made of the same material as the element components Convex A first step of forming a pseudo member; Said On the entire surface of the semiconductor wafer Said Depositing an insulating film covering the element constituent member and the pseudo member, Said A second step of polishing the insulating film by a CMP method.
[0013]
According to such a method of manufacturing a semiconductor integrated circuit device, in the first step, not only the element forming member is formed in the product chip region, but also the pseudo member is formed in the pseudo chip region. Since the insulating film formed on both the element forming member and the pseudo member is polished by the CMP method, the uniformity of the remaining film thickness of the insulating film after the CMP can be improved.
[0014]
That is, when the pseudo member is not provided in the pseudo chip region, a film or the like for forming the element forming member remains in the pseudo chip region without being patterned at all, and the insulating film in the pseudo chip region is entirely covered by the region. Is in a convex state. Therefore, in the pseudo chip region, the pressure received from the polishing pad during the CMP polishing is applied to the entire surface of the flat insulating film, and the pressure per unit area applied to this region decreases. That is, since the insulating film on the patterned element forming member has a surface shape according to the unevenness of the element forming member, and the pressure received from the polishing pad is received only by the convex portion, the applied pressure per unit area Becomes larger, while the applied pressure becomes relatively lower in the pseudo chip region. Since the polishing rate is generally proportional to the applied pressure, the difference in the applied pressure causes the remaining film thickness of the insulating film to be non-uniform.
[0015]
If the non-uniformity of the insulating film is limited only to the pseudo chip region, no problem occurs because the pseudo chip formed in this region does not become a product, but the non-uniformity is adjacent to the pseudo chip. It extends to product chips. Therefore, this is a factor that reduces the yield of product chips adjacent to the pseudo chip.
[0016]
Therefore, in the present invention, patterning is performed even in the pseudo chip region to form a dummy pseudo member. By providing the dummy member in this manner, a reduction in polishing pressure during CMP polishing of the insulating film on the dummy member is prevented, and the uniformity of the remaining film thickness of the insulating film is improved. As a result, the film thickness uniformity of the insulating film of the product chip adjacent to the pseudo chip can be improved, and the product yield of the chip can be improved.
[0017]
In addition, as an element forming member, an active region of a semiconductor substrate having a shallow trench element isolation structure, a polycrystalline silicon wiring serving as a gate electrode on a gate insulating film, a metal or a polycrystalline silicon wiring on an interlayer insulating film are exemplified. Can be.
[0018]
(2) A method of manufacturing a semiconductor integrated circuit device according to the present invention, wherein a product chip region located in an effective processing region of a semiconductor wafer and a product chip constituting the semiconductor integrated circuit device is formed; Said Located on the outer periphery of the semiconductor wafer, Said Unfinished product chips All A method of manufacturing a semiconductor integrated circuit device for processing a semiconductor wafer including a pseudo chip region where a chip is formed, comprising: Said At the same time as forming a concave portion in which a conductive element constituting a semiconductor integrated circuit element is formed in an insulating film in a product chip area, Said A first step of forming a pseudo recess in the insulating film in the peripheral chip area; Said On the entire surface of the semiconductor wafer Said Includes inner surface of recess and pseudo recess Said Depositing a conductive film on the surface of the insulating film, Said Polish the conductive film by CMP method By removing the conductive film on the surface of the insulating film, Recess Inner surface and pseudo concave inner surface And a second step of forming a conductive element forming member.
[0019]
According to such a method of manufacturing a semiconductor integrated circuit device, in the first step, not only the concave portion for forming the element constituent member in the product chip region is formed in the insulating film, but also the pseudo concave portion is formed in the pseudo chip region. Forming and, in the second step, forming a conductive film on the surface of the insulating film including the inner surface of the concave portion and the pseudo concave portion, and polishing the conductive film by a CMP method; therefore, the conductive film can be uniformly polished. The constituent members can be formed uniformly.
[0020]
The reason why the conductive film can be polished uniformly is the same as the reason why the insulating film is uniformly polished as described in the above (1).
[0021]
In addition, as the element constituent member, a tungsten plug or a wiring by a damascene method can be exemplified, and as the concave portion, a connection hole for forming a plug or a groove for forming a wiring can be exemplified. Further, since the recess includes both the connection hole and the wiring groove, the formation of the connection hole and the wiring by the so-called dual damascene method is also included. Further, examples of the conductive film include polycrystalline silicon in addition to a metal film such as aluminum and copper.
[0022]
(3) The method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to the above (1) or (2), wherein the pattern of the pseudo member or the pseudo recess in the pseudo chip region is a product. This is the same as the pattern of the element constituent member or the concave portion in the chip area.
[0023]
According to such a method of manufacturing a semiconductor integrated circuit device, the pseudo member or the pseudo concave pattern in the pseudo chip region is made the same as the element constituent member or the concave pattern in the product chip region. And the CMP pressure of the insulating film or the metal film can be made uniform.
[0024]
Further, the pattern density of the pseudo chip region is not limited to the same as that of the product chip region. Or it can be an approximation. In this way, not only by making the patterns of the pseudo chip region and the product chip region the same, but also by making the densities the same or similar, the polishing pressure per unit area applied to both regions can be substantially reduced. The same can be achieved, and the CMP polishing rate of the insulating film or the metal film can be made uniform.
[0025]
Further, according to experiments and studies by the present inventors, practical uniformity can be obtained even when the following conditions are satisfied. That is, the pattern density N1 of the pseudo member or the pseudo concave portion in the pseudo chip region is 0.5 × N2 ≦ N1 ≦ 2 × N2 which is 0.5 × N2 ≦ N1 ≦ 2 × N2 with respect to the pattern density N2 of the element component member or the concave portion in the product chip region. This is a case where both the condition and the second condition of 0.1 ≦ N1 ≦ 0.8 are satisfied. That is, the pattern density N1 of the pseudo chip region may be between 50% and 200% of the pattern density N2 of the product chip region, and need not exactly match or approximate N2. However, the pattern density N1 of the pseudo chip region needs to be between 10% and 80%. For example, when the pattern density N2 of the product chip area is 20%, the pattern density N1 of the pseudo chip area may be in the range of 10% to 40%. However, when N2 is 10%, N1 needs to be in the range of 10% to 20%, and when N2 is 50%, N1 needs to be in the range of 25% to 80%.
[0026]
Further, the pattern size of the pseudo member or the pseudo recess may be not less than twice the pattern width of the element constituent member or the recess and may be not more than 1 mm. In such a case, since the pattern size of the pseudo member or the concave portion is twice or more the pattern width of the element constituent member or the concave portion, it is possible to prevent dust generation factors such as pattern collapse in the pseudo chip region. That is, since the pseudo member or the pseudo concave portion is formed outside the effective processing region outside the process control range in the wafer processing step or over the region, the lithography or etching is not performed well. In particular, if the metal film in the wiring forming step is not etched well, the metal pieces may peel off from the wafer and become conductive dust, which may cause a defect. Therefore, in the present invention, the pattern size of the pseudo member or the pseudo concave portion is set to be twice or more the pattern width of the element constituent member or the concave portion to prevent the separation of these members and suppress the occurrence of defects in the manufacturing process of the semiconductor integrated circuit device. Things. However, if the pattern size of the pseudo member or the pseudo recess is too large, the effect of patterning may be weakened, so the maximum is 1 mm.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0028]
(Embodiment 1)
FIG. 1 is a plan view showing an example of a wafer to which a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention is applied, and FIG. 2 is an enlarged view of a portion II in FIG.
[0029]
The wafer 1 used in the manufacturing method according to the first embodiment includes a product chip area 3 where a product chip 2 is formed and a pseudo chip area 5 where an incomplete pseudo chip 4 that does not become a product is formed. . The product chip 2 is formed in the effective processing area 6 where the process management in each manufacturing process is guaranteed. Conversely, in a region outside the effective processing region 6, the product chip 2 cannot be formed, and all chips formed in such a region become pseudo chips 4, which are discarded after the end of the process. . Therefore, the thin film formed in the pseudo chip region 5 is not generally patterned, and is left as a solid film.
[0030]
However, in the wafer 1 of the present embodiment, as shown in FIG. 2, the same pattern 7 as the pattern 7 of the product chip 2 is also patterned on the pseudo chip 4 in the pseudo chip region 5. By forming the pattern 7 on the pseudo chip 4 as well, the uniformity of the amount of CMP of the insulating film on the pattern is improved, and the uniformity of the remaining film thickness of the insulating film can be improved.
[0031]
Hereinafter, the manufacturing method of the first embodiment will be described with reference to FIGS. 3 to 7 are cross-sectional views illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps. FIG. 3A is a cross-sectional view taken along line aa in FIG. ) Shows a cross section taken along line bb in FIG.
[0032]
First, a silicon nitride film (not shown) is deposited on the main surface of the wafer 1, and after patterning the silicon oxide film, a thermal oxidation process is performed using the patterned silicon oxide film as a mask to form a field insulating film made of a thick silicon oxide film. A film 8 is formed. The well 9 is formed by ion-implanting a low concentration impurity. Thereafter, a silicon oxide film to be the gate insulating film 10 is sequentially deposited by, for example, a thermal CVD method, a polycrystalline silicon film to be the gate electrode 11 is deposited by, for example, an LPCVD method, and a silicon oxide film to be the cap insulating film 12 is deposited by, for example, a plasma CVD method. The gate insulating film 10, the gate electrode 11, and the cap insulating film 12 are formed by patterning the stacked films. Further, impurities are ion-implanted using the gate electrode 11 and the cap insulating film 12 as a mask to form an impurity semiconductor region 13. Thereafter, a silicon oxide film is deposited, and is subjected to anisotropic etching to form a sidewall 14 (FIG. 3). Note that the cap insulating film 12 and the sidewalls 14 may be silicon nitride films.
[0033]
Known photolithography and etching techniques can be used for patterning the laminated film, and the impurity semiconductor region 13 may be formed into an LDD (Lightly Doped Drain) structure by ion-implanting high-concentration impurities after forming the sidewalls 14. When the MISFET formed in the above step is of n-type conductivity, the impurity introduced into the well 9 is a p-type impurity such as boron, and the impurity introduced into the impurity semiconductor region 13 is n-type such as phosphorus or arsenic. Can be shaped impurities. If the conductivity type of the MISFET is p-type, the reverse can be achieved.
[0034]
The MISFET is formed in the product chip area 3 and is not formed in the pseudo chip area 5.
[0035]
Next, after an insulating film 15 is deposited on the entire surface of the wafer 1, the insulating film 15 is planarized by using an etch-back method, a CMP method, or the like. The insulating film 15 can include a film having a self-planarizing function such as a BPSG film, an SOG film, or a silicon oxide film formed by a high-density plasma CVD method. In this case, in order to prevent diffusion of impurities such as boron and phosphorus, a silicon oxide film or the like by a CVD method using TEOS can be included on the MISFET side. Further, after opening the connection hole 16, a metal film to be the wiring 17 is deposited, and the metal film is patterned using a known photolithography and etching technique to form the wiring 17. An insulating film 18 covering the wiring 17 is deposited on the wiring 17 (FIG. 4).
[0036]
The wiring 17 can be, for example, a metal film containing aluminum as a main component, and can be deposited by a sputtering method or an evaporation method. At the time of this deposition, a film is simultaneously deposited in the connection hole 16, and the wiring 17 can be connected to the impurity semiconductor region 13 on the main surface of the wafer 1.
[0037]
The wiring 17 is formed not only in the product chip area 3 but also in the pseudo chip area 5 and is one of the patterns 7 described in FIG. By forming the wiring 17 also in the pseudo chip region 5, the uniformity of the remaining film thickness of the insulating film 18 after the CMP of the insulating film 18 can be improved as described later.
[0038]
The insulating film 18 may include a film having a self-planarizing function such as a BPSG film, an SOG film, or a silicon oxide film formed by a high-density plasma CVD method, and may be stacked with a silicon oxide film formed by a CVD method using TEOS. It can also be a membrane.
[0039]
Next, the surface of the insulating film 18 is polished by the CMP method (FIG. 5). As shown in FIG. 5, in the first embodiment, the convex portion of the insulating film 18 at the boundary between the pseudo chip region 5 and the product chip region 3 contacts the polishing pad 19 with a length of 12 L (see FIG. )), The protruding portion of the insulating film 18 at the boundary between the product chip regions 3 is also in contact with the polishing pad 19 with a length of 12 L (FIG. 5B). This is because the wiring 17 is also formed in the pseudo chip region 5 with the same pattern as the pattern of the product chip region 3, and thus the insulating film 18 and the polishing pad 19 are in contact with the same area. Therefore, the polishing rate of the insulating film 18 can be made uniform regardless of the location of the pseudo chip region 5 or the product chip region 3.
[0040]
That is, in the CMP polishing, the polishing speed R is generally represented by a function of a pressure Ps applied to a sliding surface and a relative speed v between the wafer 1 and the polishing pad 19, and R = Kp × Ps × v (Kp is Coefficient). Therefore, when the pressure Ps decreases, the polishing rate R decreases in proportion thereto, and the remaining film thickness of the insulating film 18 increases.
[0041]
Now, for the sake of simplicity, assuming that the wiring 17 in FIG. 5 is a simple line and space and that the pattern density does not change in the direction perpendicular to the paper, the pressure Ps per unit area applied to the sliding surface is Is given as a value obtained by dividing the uniform applied pressure P applied to the back surface of the substrate by the contact area, and becomes P / 12L. This value is the same at the boundary between the pseudo chip region 5 and the product chip region 3 (FIG. 5A) and at the boundary between the product chip regions 3 (FIG. 5B). This shows that the polishing rate of the insulating film 18 by polishing is not different.
[0042]
On the other hand, considering the case where the solid pattern 20 of the wiring 17 is left in the pseudo chip region 5 as shown in FIG. 17, the boundary between the pseudo chip region 5 and the product chip region 3 as shown in FIG. Pressure (Ps) per unit area at P / 21L (FIG. 18 (a)), and pressure Ps per unit area at the boundary between product chip regions 3 is P / 12L (FIG. 18 (b)). ), The pressure Ps at the boundary between the pseudo chip region 5 and the product chip region 3 is smaller than the pressure Ps at the boundary between the product chip regions 3, and the boundary between the pseudo chip region 5 and the product chip region 3 In this case, the remaining film thickness of the insulating film 18 becomes large.
[0043]
However, according to the manufacturing method of the first embodiment, as described above, since the pattern 7 of the wiring 17 is also formed in the pseudo chip region 5, as shown in FIG. The remaining film thickness becomes uniform, and the process margin of the photolithography or etching process in the subsequent process can be improved. Specifically, when the size of the protruding portion of the pattern 7 is, for example, 80 μm and the pattern density is 20%, in the insulating film 18 having the remaining film thickness of 800 nm, the variation in the film thickness can be suppressed to 100 nm, Although the variation when the pattern 7 is not formed in the chip region 5 is 300 nm, the uniformity of 200 nm can be improved.
[0044]
In addition, as a condition of the CMP polishing, the pressure applied to the wafer 1 was set to 500 g / cm. ² The rotation speed of both the platen and the carrier can be 20 rpm, and the polishing pad 19 can be a hard pad.
[0045]
Further, as shown in FIG. 7, a second-layer wiring 21 and an insulating film 22 may be further formed on the insulating film 18. It goes without saying that the pattern 7 is formed on the wiring 21 in the pseudo chip region 5 in the same manner as the wiring 17 so that the uniformity of the remaining film thickness of the insulating film 22 can be improved. Further, it goes without saying that three or more wiring layers may be formed.
[0046]
(Embodiment 2)
8 to 11 are sectional views showing an example of a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention in the order of steps. Hereinafter, the manufacturing method of the second embodiment will be described with reference to FIGS.
[0047]
First, a silicon nitride film 23 is deposited on the main surface of the wafer 1, and the silicon nitride film 23 and the main surface of the wafer 1 are patterned to form shallow grooves 24 (FIG. 8). Known photolithography and etching techniques can be used for patterning the silicon nitride film 23 and the wafer 1.
[0048]
This shallow groove is formed not only in the product chip region 3 but also in the pseudo chip region 5. Further, the pattern of the shallow groove 24 formed in the pseudo chip region 5 is the same as the pattern in the product chip region 3.
[0049]
Next, a silicon oxide film 25 is deposited on the entire surface of the wafer 1 by, for example, a plasma CVD method using TEOS (FIG. 9). Since the shallow groove 24 having the same pattern as the shallow groove pattern in the product chip region 3 is also formed in the pseudo chip region 5, the surface unevenness of the silicon oxide film 25 is the same in the pseudo chip region 5 and the product chip region 3. Shape.
[0050]
Next, CMP polishing is performed as shown in FIG. As described in the first embodiment, the contact area between silicon oxide film 25 and polishing pad 19 at the boundary region between pseudo chip region 5 and product chip region 3 is equal to the contact area at the boundary region between product chip regions 3. Thus, the polishing rate of the silicon oxide film 25 can be made uniform over the entire surface of the wafer 1. As a result, a uniform element isolation region 26 can be formed (FIG. 11).
[0051]
Note that the silicon nitride film 23 in FIG. 11 is removed to complete the wafer 1 on which the element isolation regions 26 are formed. However, the subsequent element formation steps are the same as in the first embodiment, and a description thereof will be omitted.
[0052]
(Embodiment 3)
12 to 15 are sectional views showing an example of a method of manufacturing a semiconductor integrated circuit device according to still another embodiment of the present invention in the order of steps. Hereinafter, the manufacturing method of the second embodiment will be described with reference to FIGS. (A) shows a cross section taken along the line aa in FIG. 1, and (b) shows a cross section taken along the line bb in FIG. 1.
[0053]
Since the manufacturing method of the third embodiment is the same as that of the first embodiment until the first wiring layer is formed, the description is omitted.
[0054]
An insulating film 27 is deposited on the insulating film 18 to form a groove 28 for forming a wiring and a connection hole 29 (FIG. 12).
[0055]
The insulating film 27 can be, for example, a TEOS silicon oxide film. When the insulating film 18 is sufficiently thick, the insulating film 27 can be omitted. The groove 28 and the connection hole 29 can be formed using known photolithography and etching techniques, and are formed not only in the product chip region 3 but also in the pseudo chip region 5. The patterns of the grooves 28 and the connection holes 29 formed in the pseudo chip region 5 are the same as the patterns in the product chip region 3.
[0056]
Next, a metal film 30 such as copper or aluminum is deposited on the entire surface of the wafer 1 by, for example, a sputtering method (FIG. 13). Since the grooves 28 and the connection holes 29 having the same pattern as the shallow groove pattern in the product chip region 3 are also formed in the pseudo chip region 5, the surface unevenness of the metal film 30 is reduced in the pseudo chip region 5 and the product chip region 3. It has a similar shape.
[0057]
Next, as shown in FIG. 14, CMP polishing is performed. As described in the first embodiment, the contact area between metal film 30 and polishing pad 19 at the boundary region between pseudo chip region 5 and product chip region 3 is the contact area at the boundary region between product chip regions 3. The polishing speed of the metal film 30 can be made uniform over the entire surface of the wafer 1. As a result, a uniform wiring 31 can be formed by the damascene method (FIG. 15).
[0058]
(Embodiment 4)
FIG. 16 is a plan view showing a boundary region between the pseudo chip region 5 and the product chip region 3.
[0059]
In the manufacturing method according to the fourth embodiment, the pattern 32 formed in the pseudo chip region 5 is a pattern different from the pattern 7 formed in the product chip region 3. However, the pattern densities of the pattern 32 and the pattern 7 are the same.
[0060]
As described above, by making the pattern densities of the pattern 32 and the pattern 7 the same, the CMP polishing rates in the pseudo chip region 5 and the product chip region 3 can be made uniform, and the remaining CMP polishing film on those patterns can be obtained. The uniformity of the film thickness can be improved.
[0061]
The pattern densities of the pattern 32 and the pattern 7 do not need to be exactly the same. According to experiments and studies conducted by the inventor, the pattern density N1 of the pattern 32 is set to 0.5 × N2 ≦ N1 ≦ 2 × N2 with respect to the pattern density N2 of the pattern 7, and 0.1 ≦ N1. ≦ 0.8. That is, the pattern density N1 of the pattern 32 may be between 50% and 200% of the pattern density N2 of the pattern 7. However, the pattern density N1 of the pattern 32 needs to be between 10% and 80%.
[0062]
Specifically, for example, when N2 is 20%, N1 may be in the range of 10% to 40%. When N2 is 10%, N1 may be in the range of 10% to 20%, and when N2 is 50%, N1 may be in the range of 25% to 80%.
[0063]
Further, the pattern size of the pattern 32 can be not less than twice the pattern width of the pattern 7 and not more than 1 mm. In such a case, it is possible to prevent a dust generation factor such as a pattern collapse of the wiring formed by the pattern 32. That is, the wiring formed by the pattern 32 may not fall within the effective processing area 6, and the processing of the member located outside the effective processing area 6 is generally not good. However, if the pattern width of the pattern 32 is increased, such a problem hardly occurs.
[0064]
However, if the pattern size of the pseudo member or the pseudo recess is too large, the effect of patterning may be weakened, so the maximum is 1 mm.
[0065]
Note that the pattern 32 of the fourth embodiment can be used in the first to third embodiments.
[0066]
As described above, the invention made by the inventor has been specifically described based on the embodiment of the invention. However, the invention is not limited to the embodiment, and can be variously modified without departing from the gist of the invention. Needless to say, there is.
[0067]
For example, in the first to third embodiments, the case where the present invention is applied to the element isolation region and the metal wiring has been described. However, the present invention can be applied to other members such as a gate wiring and a bit line.
[0068]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0069]
(1) The uniformity of the remaining thickness of the polishing film in the CMP process can be improved.
[0070]
(2) The exposure margin and the etching margin in the photolithography process after the CMP process can be improved, and the production yield of the semiconductor integrated circuit device can be improved.
[Brief description of the drawings]
FIG. 1 is a plan view showing an example of a wafer to which a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention is applied.
FIG. 2 is an enlarged view of a portion II in FIG.
3A to 3C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps, wherein FIG. 3A is a cross-sectional view taken along line aa in FIG. 1 and FIG. 1 shows a cross section taken along the line bb in FIG.
4A and 4B are cross-sectional views illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps, wherein FIG. 4A is a cross-sectional view taken along line aa in FIG. 1 and FIG. 1 shows a cross section taken along the line bb in FIG.
5A and 5B are cross-sectional views illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps, wherein FIG. 5A is a cross-sectional view taken along line aa in FIG. 1 and FIG. 1 shows a cross section taken along the line bb in FIG.
6A and 6B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps, wherein FIG. 6A is a cross-sectional view taken along line aa in FIG. 1 and FIG. 1 shows a cross section taken along the line bb in FIG.
7A and 7B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps, wherein FIG. 7A is a cross-sectional view taken along line aa in FIG. 1 and FIG. 1 shows a cross section taken along the line bb in FIG.
FIG. 8 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention in the order of steps.
FIG. 9 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention in the order of steps.
FIG. 10 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention in the order of steps.
FIG. 11 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention in the order of steps.
12A and 12B are cross-sectional views illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to still another embodiment of the present invention in the order of steps, wherein FIG. 12A is a cross-sectional view taken along line aa in FIG. ) Shows a cross section taken along line bb in FIG.
13A and 13B are cross-sectional views illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to still another embodiment of the present invention in the order of steps, and FIG. 13A is a cross-sectional view taken along line aa in FIG. ) Shows a cross section taken along line bb in FIG.
FIGS. 14A and 14B are cross-sectional views illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to still another embodiment of the present invention in the order of steps, and FIG. 14A is a cross-sectional view taken along line aa in FIG. ) Shows a cross section taken along line bb in FIG.
15A and 15B are cross-sectional views illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to still another embodiment of the present invention in the order of steps; FIG. 15A is a cross-sectional view taken along line aa in FIG. ) Shows a cross section taken along line bb in FIG.
FIG. 16 is a plan view showing a boundary region between a pseudo chip region and a product chip region according to the fourth embodiment.
FIG. 17 is a plan view showing an example in which a solid pattern is left in a pseudo chip region.
FIG. 18 is a cross-sectional view showing an example in which a solid pattern is left in a pseudo chip region.
[Explanation of symbols]
1 wafer
2 Product chips
3 Product chip area
4 pseudo chip
5 pseudo chip area
6 Effective processing area
7 patterns
8 Field insulation film
9 wells
10 Gate insulating film
11 Gate electrode
12 Cap insulating film
13 Impurity semiconductor region
14 Sidewall
15 Insulating film
16 Connection hole
17 Wiring
18 Insulating film
19 Polishing pad
20 solid patterns
21 Wiring
22 insulating film
23 Silicon nitride film
24 Shallow groove
25 Silicon oxide film
26 Device isolation area
27 Insulating film
28 grooves
29 Connection hole
30 metal film
31 Wiring
32 patterns
N1 pattern density
N2 pattern density
P applied pressure
Ps pressure
R Polishing speed
v Relative speed

Claims (3)

An incomplete chip which is located in the effective processing area of the semiconductor wafer, in which a product chip constituting the semiconductor integrated circuit device is formed, and which is located on the outer peripheral portion of the semiconductor wafer and does not become the product chip. A method of manufacturing a semiconductor integrated circuit device for processing a semiconductor wafer including a pseudo chip region to be formed,
At the same time as forming a projecting conductive element constituting a semiconductor integrated circuit element in the product chip region, the pseudo chip region is formed of the same material in a size of at least twice the pattern size of the element component and at most 1 mm. A first step of forming a convex pseudo member;
A second step of depositing an insulating film covering the element constituent member and the pseudo member on the entire surface of the semiconductor wafer and polishing the insulating film by a CMP method. . An incomplete chip which is located in the effective processing area of the semiconductor wafer, in which a product chip constituting the semiconductor integrated circuit device is formed, and which is located on the outer peripheral portion of the semiconductor wafer and does not become the product chip. A method of manufacturing a semiconductor integrated circuit device for processing a semiconductor wafer including a pseudo chip region to be formed,
At the same time as forming a recess in which an electrically conductive element constituting a semiconductor integrated circuit device is formed in the insulating film in the product chip area, the insulating film in the peripheral chip area is twice or more the pattern size of the recess and 1 mm or less. A first step of forming a pseudo concave portion of
Depositing a conductive film on the surface of the insulating film including the inner surface of the concave portion and the pseudo concave portion over the entire surface of the semiconductor wafer, and polishing the conductive film by a CMP method to remove the conductive film on the surface of the insulating film; Forming a conductive element forming member on the inner surface of the concave portion and the inner surface of the pseudo concave portion by the method according to the first aspect of the present invention. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein
The pattern density N1 of the pseudo member or the pseudo concave portion in the pseudo chip region is smaller than the pattern density N2 of the element component member or the concave portion in the product chip region.
A first condition that is 0.5 × N2 ≦ N1 ≦ 2 × N2,
A second condition that satisfies 0.1 ≦ N1 ≦ 0.8,
A method for manufacturing a semiconductor integrated circuit device, which satisfies both of the above conditions.

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