JP3557563B2 - Electronic camera - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to an electronic camera that uses a flash memory as a recording medium for captured image data.
[0002]
[Prior art]
2. Description of the Related Art In recent years, electronic cameras have been advanced, and electronic cameras that record captured images on a floppy disk or an IC memory card have been put into practical use.
[0003]
Such a conventional electronic camera has a mounting portion for detachably mounting a floppy disk or an IC memory card on the camera body, and an image of an image taken on the floppy disk or the IC memory card mounted on the mounting portion. The data is being recorded.
[0004]
In recent years, a flash memory has been attracting attention as a recording medium. A flash memory does not require a battery backup for data retention like a DRAM, and can be more highly integrated than a DRAM. And a substitute for a hard disk or a floppy disk is also possible. For this reason, the flash memory is also promising as a recording medium for the electronic camera.
[0005]
The data writing process in the flash memory will be described with reference to the flowchart shown in FIG.
[0006]
In FIG. 11, when writing data to the flash memory, first, the address Address of the write destination on the flash memory and the number of NGs n during writing are set (initialized) (steps P1 and P2), and the write ( Write) A program command is input to read out the write data, write the 1-byte data to the set address (Step P3), wait for a predetermined time (Wait) (Step P4), and verify (Step P4). (Verify) command is input (step P5).
[0007]
Next, after waiting for a predetermined time again (step P6), the previous write data is read, and it is confirmed whether or not the data matches the data written to the flash memory (step P7). If they do not match (NG), The number of NG is increased by 1 (n + 1) (step P8), and it is determined whether or not the address has reached "50" (step P9). If this has been reached, this processing is interrupted.
[0008]
If the read data and the write data match in Step P7, it is determined whether or not the current write destination address is the last address (Step P10). If not, the write destination address is incremented by 1 (Address + 1). (Step P11), and returns to Step P2. If the write destination address is the last address, the process ends.
[0009]
As described above, when writing data to the flash memory, a wait operation for a predetermined time is required at the time of writing and at the time of verification.
[0010]
[Problems to be solved by the invention]
However, in such a conventional electronic camera, when a flash memory is used as a recording medium, as shown in FIG. 11, when writing data, a wait time of a predetermined time is required between writing and verifying. When the electronic camera is used as a recording medium because of the necessity of an operation, a vacant time due to a wait time occurs in a recording process of image data, and the recording process is prolonged, thereby reducing the processing efficiency. There was a point.
[0011]
Also, in the event that some kind of accident occurs during the recording of captured image data and the power of the electronic camera main body is cut off, even if a situation occurs where complete encoded data is not recorded, in the conventional electronic camera, Since it was not possible to know that the data was incompletely coded data, there was also a problem that a composite error occurred during the decompression of the incompletely coded data and an incomplete image was displayed on a monitor. there were.
[0012]
An object of the present invention is to provide a process for writing image data.ReasonAn object of the present invention is to provide an electronic camera capable of improving a problem that occurs when performing the operation.
[0013]
[Means for Solving the Problems]
The invention according to claim 1 is
Imaging means for imaging a subject;
Digital conversion means for converting an image signal for one screen input from the imaging means into digital image data;
Compression means for encoding the digital image data for one screen converted by the digital conversion means by a predetermined encoding method to generate encoded data for one screen;
Decompression means for decoding the encoded data,
Data conversion means for converting the digital image data decoded by the decompression means into a display signal for displaying on a display unit;
SaidData recording means for recording one screen of encoded data encoded by the compression means;
During a period in which encoded data for one screen is written in the data recording unit, a process related to an encoding process in the compression unit is performed.And data conversion processing in the data conversion meansControl means for executing
It is characterized by having.
[0014]
In this case, as described in claim 2,
The data recording unit records the coded data for one screen by dividing the coded data for one screen in a predetermined data unit at a predetermined writing timing,
The control unit uses a waiting time when dividing and writing one screen of encoded data into the data recording unit, and performs processing related to encoding processing in the compression unit.And data conversion processing in the data conversion meansIt is effective to distribute and execute.
[0015]
Further, as described in claim 3,
SaidData recording meansThe compression meansRecording control means for recording identification information for identifying an encoding start position and an encoding end position of one screen of digital image data encoded by
When reproducing the encoded data recorded in the data recording means, it is determined whether or not the encoded data for one screen based on the identification information,The extension meansPlayback control means for controlling whether or not to decrypt by
It is effective to provide
Claims4The data recording means may be constituted by a flash memory.
[0019]
【Example】
Hereinafter, embodiments will be described with reference to FIGS.
[0020]
FIG. 1 is a diagram showing one embodiment of an electronic camera to which the present invention is applied.
[0021]
First, the configuration will be described.
[0022]
FIG. 1 is a block diagram of the electronic camera 1.
[0023]
Referring to FIG. 1, an electronic camera 1 includes a CCD 2, an A / D converter 3, a DRAM 4, a flash memory 5, a CPU 6, a compression / expansion unit 7, an encoder 8, a D / A converter 9, and a monitor 10. The converter 3, the DRAM 4, the flash memory 5, the CPU 6, the compression / expansion unit 7, and the encoder 8 are connected to the bus B.
[0024]
The CCD (Charge Coupled Device) 2 outputs, for example, an image signal (analog signal) for one screen formed of m × n pixels based on the intensity of light formed by imaging a subject by a lens (not shown). Then, the image signal is output to the A / D converter 3.
[0025]
The A / D converter 3 converts an image signal (analog signal) for one screen input from the CCD 2 into image data (digital signal) for one screen so that subsequent image processing can be performed digitally. The data is output to the CPU 6 via the bus B.
[0026]
A DRAM (Dynamic Random Access Memory) 4 forms a memory area for storing luminance signal data and chrominance signal data generated from image data for one screen by color process processing executed by the CPU 6.
[0027]
The flash memory 5 forms a data write area for storing coded data that has been extracted and encoded by the compression / expansion unit 7 in units of 8 × 8 pixels as one block. Also, before the luminance / color difference signal data for one block is compressed by the compression / expansion unit 7, the flash memory 5 has a start code writing area for writing a specific star code indicating the start position of the luminance / color difference signal data. An end code writing area for writing a specific end code indicating the final position of the encoded data compressed by the compression / expansion unit 7 is formed separately from the data writing area.
[0028]
A CPU (Central Processing Unit) 6 controls each unit in the electronic camera 1 according to a predetermined control program. The CPU 6 generates a luminance signal and a color difference signal from the image data for one screen input from the A / D converter 3 by color process processing, stores the luminance signal and the color difference signal in the DRAM 4, and stores the luminance / color difference for one screen stored in the DRAM 4. Of the signals, 8 × 8 pixels are cut out as one block and output to the compression / expansion unit 7 to execute an encoding process, and a writing process of sequentially writing the encoded data into the flash memory 5 is executed.
[0029]
Further, when writing the encoded data to the flash memory 5 in units of one block, the CPU 6 utilizes the wait time (empty time) at the time of writing to perform the next encoding in the interrupt control processing described later. The writing of the luminance / color difference data of the block into the compression / decompression unit 7 is performed, and the setting of image data to the encoder 8 is performed.
[0030]
That is, the CPU 6 executes the data writing process or the data setting process for the compression / expansion unit 7 and the encoder 8 in a distributed manner by using the wait time generated at the time of the process of writing the encoded data to the flash memory 5, thereby performing photographing. The recording processing time of the image data at the time is shortened.
[0031]
As shown in FIG. 2, the compression / decompression unit 7 includes a RAMG 21, a DCT unit 22, a quantization unit 23, a Huffman encoding unit 24, and a RAMC 25.
[0032]
The RAMG 21 forms a memory area for storing one block of luminance / color difference signal data written by the CPU 6.
[0033]
The DCT unit 22 performs DCT (Discrete Cosine Transform) processing on the luminance / color difference signal data in units of one block written in the RAMG 21 at the time of image recording, and quantizes the DCT data in units of one block. Output to the conversion unit 23. The DCT unit 22 also has a function of performing an inverse DCT process for one screen of coded data written in the flash memory 5 for each block when reproducing a recorded image.
[0034]
When recording an image, the quantization unit 23 performs a quantization operation on the DCT data in units of one block subjected to the DCT processing input from the DCT unit 22 in accordance with a value of a predetermined quantization table. The quantized data is output to the Huffman encoding unit 24. Further, when reproducing the recorded image, the quantization unit 23 performs an inverse quantization process on the encoded data for one screen written in the flash memory 5 in units of one block based on a predetermined inverse quantization table. It also has the function of
[0035]
The Huffman encoding unit 24 performs a Huffman encoding process on the quantized data in units of one block input from the quantization unit 23 according to the Huffman encoding method, and stores the Huffman encoded data in units of one block in the RAMC 25. Further, the Huffman encoding unit 24 has a function of decoding encoded data for one screen written in the flash memory 5 in units of one block when reproducing a recorded image.
[0036]
The RAMC 25 forms a memory area for storing Huffman-encoded data in units of one block input from the Huffman encoding unit 24, and the stored Huffman-encoded data in units of one block is read out by the CPU 6 and stored in the flash memory Written in 5.
[0037]
Therefore, in the image recording, the compression / expansion unit 7 repeatedly executes the DCT processing, the quantization processing, and the Huffman encoding processing on the luminance / color difference signal data sequentially written to the RAMG 21 in units of one block by the CPU 6. The luminance / color difference signal data for one screen is sequentially encoded.
[0038]
When the encoded data written in the flash memory 5 is reproduced, the compression / expansion unit 7 performs the decoding process, the inverse quantization process, and the decoding process on the encoded data written in the RAMC 25 in block units. The inverse DCT process is repeatedly performed, and the encoded data for one screen is sequentially returned to the luminance / color difference signal.
[0039]
The encoder unit 8 encodes the luminance / color difference signal data written by the CPU 6 into a video signal to be displayed on the monitor 10 and outputs the video signal to the monitor 10 to display a captured image.
[0040]
Next, the operation will be described.
[0041]
First, when the CPU 6 writes the encoded data into the flash memory 5 using the wait time generated at the time of writing, the relationship between the tasks executed by the interrupt control process of the CPU 6 is shown in FIG. Shown in units.
[0042]
In FIG. 3, first, when the encoding process for one block is completed in the compression / expansion unit 7, an end interrupt is output to the CPU 6. When a termination interrupt is generated, the CPU 6 executes an encoding termination process, sets an event B, and executes “data reading from RAMC and data writing to flash memory” indicated by a task 2 block in FIG. Is
[0043]
In the processing indicated by the task 2 block, when the free space of the RAMC 25 is equal to or larger than a predetermined byte, an event A is set, and "data writing to RAMG" indicated by a task 1 block in the figure is performed.
[0044]
Further, "set data to the encoder" indicated by a task 3 block in the figure is performed asynchronously with the tasks 1 and 2.
[0045]
Next, details of each process executed by the CPU 6 in the blocks of the tasks 1 to 3 shown in FIG. 3 will be described based on the flowcharts shown in FIGS.
[0046]
First, the encoding end processing shown in FIG. 3 will be described based on the flowchart shown in FIG.
[0047]
In FIG. 4, when an encoding end interrupt is generated from the compression / expansion unit 7, the CPU 6 starts an encoding end process, sets an event B (step S1), and frees the RAMC 25 in the compression / expansion unit 7. Is calculated (step S2). It is determined whether or not the free space is equal to or larger than a predetermined byte (step S3). If the free space is equal to or larger than a predetermined byte, an event A is set (step S4), and the main encoding end process is terminated. If the capacity is not equal to or larger than the predetermined byte, the present encoding end processing ends without setting the event A.
[0048]
Next, the process of writing data to the RAMG 21 shown in task 1 of FIG.
[0049]
In FIG. 5, first, one block (8 × 8 pixels) is written from the luminance / color difference signal data for one screen stored in the DRAM 4 into the RAMG 21 in the compression / expansion unit 7 (step S11), and the written data block is written. Is the last block (step S12). If the written data block is the last block, the present task is ended. If the written data block is not the last block, the task enters a wait state for setting the event A by the above-described encoding end processing (step S13). When the event A is set, the process returns from the waiting state, clears the event A by itself (step S14), returns to step S11, and writes the luminance / color difference signal data for one block into the RAMG 21 again. Do.
[0050]
Next, the process of reading data from the RAMC 25 and writing data to the flash memory shown in task 2 of FIG. 3 will be described with reference to the flowchart shown in FIG.
[0051]
In FIG. 6, first, the start code of the luminance / color difference signal data for one block cut out from the DRAM 4 is written into the start code writing area in the flash memory 5 (step S21), and the setting of the event B by the above-mentioned encoding end processing is waited. The state is reached (step S22). When the event B is set by the end of the encoding process, the process returns from the waiting state, reads out the encoded data which has been encoded and stored in the RAMC 25 by 1 byte (step S23), and writes the encoded data which has been read out to the flash memory 5. (Step S24). Next, during a predetermined time for the writing, the processing authority is transferred to the OS (Operating System), and a time waiting state is entered (step S25).
[0052]
At this time, if there is another executable task, the OS passes the processing authority to the task and sets the task to the execution state.
[0053]
When a predetermined time elapses after entering the time waiting state, the task returns from the time waiting state, and if no other task is in the executing state, the operation starts as it is. If another task is executing, the task is executed. It waits until it enters a wait state, and upon receiving processing authority from the OS, immediately resumes its operation. When the operation is restarted, this task performs verification of the encoded data written in the flash memory 5 (step S26), and enters a waiting state for a predetermined time as in step S25 (step S27).
[0054]
Next, when returning from the waiting state, the free space of the RAMC is calculated (step S28), and it is determined whether or not the free space is equal to or more than a predetermined byte (step S29). If the free space is equal to or larger than the predetermined byte, event A is set (step S30), and the process proceeds to step S30. If the free space is not equal to or larger than the predetermined byte, event A is set without setting event A. Move to the processing of. In the process of step S30, it is determined whether or not the number of coded data is “0”. If the number of coded data is not “0”, the process returns to step S22 to enter the event B set waiting state, and If the number is "0", it is determined whether or not the block is the last block (step S32). If it is not the last block, the event B is cleared (step S33). If it is the last block, an end code indicating the last block is written in the end code writing area in the flash memory 5 (step S34). , End this task.
[0055]
Next, the data setting process for the encoder shown in task 3 of FIG. 3 will be described based on the flowchart shown in FIG. The task 3 is a task that operates asynchronously with the tasks 1 and 2 described above.
[0056]
In FIG. 7, first, one line of image data is set in the encoder (step S41), and it is determined whether or not the set image data is the last line (step S42). If the image data is not the last line, the process enters a waiting time for a certain period of time (step S43). If the image data is the last line, this task ends.
[0057]
FIG. 8 shows the relationship between the tasks 1 to 3 sequentially processed by the interrupt control processing of the CPU 6 and the encoding processing in the compression / expansion unit 7 in block units.
[0058]
That is, an image signal for one screen is output to the A / D converter 3 by the CCD 2, and is digitally converted by the A / D converter 3 to be converted to image data for one screen. Is output to the CPU 6, luminance / color difference signal data for one screen is generated by the color process processing and stored in the DRAM 4. Next, the first one block (first block) is cut out from the luminance / color difference signal data for one screen stored in the DRAM 4 and written into the RAMG in the compression / expansion unit 7 (block B1).
[0059]
Next, in the compression / expansion unit 7, DCT processing is performed on the first block luminance / color difference signal data, followed by quantization processing and Huffman coding processing (blocks B2 and B3), and the first block coded data is processed. Is written to the RAMC 25. When the encoding process for the first block is completed, the encoding / completion end interrupt is output from the compression / expansion unit 7 to the CPU 6, the CPU 6 starts the encoding end process, sets the event B, and sets the RAMC25. Event A is set based on the free space of
[0060]
With the setting of the event B, the first block encoded data is read from the RAMC 25, and writing to the flash memory 5 is started (block B4). When a wait time occurs when writing the first block encoded data to the flash memory 5, the second block luminance / color difference signal data is written to the RAM G21 by setting the event A based on the free space of the RAM C25 (block). B5).
[0061]
Next, the compression / expansion unit 7 performs DCT processing on the second block luminance / color difference signal data, and subsequently performs quantization processing and Huffman coding processing (blocks B6 and B7), and outputs the second block encoded data. Is written to the RAMC 25. When the encoding process for this second block is completed, the encoding / completion interrupt is output from the compression / expansion unit 7 to the CPU 6, the encoding end process is started by the CPU 6, the event B is set, and the RAMC 25 is set. Event A is set based on the free space of
[0062]
With the setting of the event B, the second block encoded data is read from the RAMC 25, and writing to the flash memory 5 is started (block B8). Hereinafter, similarly, the encoding process from the third block to the last block is repeatedly performed, and the writing process to the flash memory 5 is performed (blocks Bn1 to Bn4). The CPU 6 outputs the luminance / color difference signal data for one screen stored in the DRAM 4 for each line, asynchronously with the timing at which the encoding processing for one screen and the data writing processing to the flash memory 5 are performed. A process of setting the encoder 8 is performed (block BE).
[0063]
FIG. 9 is a timing chart showing transition states of the tasks 1 to 3 shown in block units in FIG.
[0064]
In FIG. 9, a part shown by a solid line indicates that each of the tasks 1 to 3 is in an execution state, and a part shown by a broken line indicates a transition state between the tasks 1 to 3. In the figure, the portion marked with “write” indicates a write operation to the flash memory 5, and the portion marked with “b” indicates a verify operation of data written to the flash memory 5. In the figure, the portion marked with “calculation” indicates the operation of calculating the free space of the RAMC 25.
[0065]
In this figure, data is initially written to the RAM G21 during a waiting time that occurs when data is written to the flash memory 5, but when the free space in the RAM C25 becomes small, data is not written to the RAM G21 and the encoder is not written. The data is set in the RAM 8 and when the free space of the RAMC 25 is available, the data is written into the RAMG 21 again.
[0066]
Next, a reproduction process for reproducing the encoded data written in the flash memory 5 will be described with reference to a flowchart shown in FIG.
[0067]
In FIG. 10, first, it is determined whether or not a start code is written in a start code writing area in the flash memory 5 (step S51). It is determined whether or not an end code has been written in the end code writing area (step S52). If the end code has been written, it is determined that the encoding process for one screen has been completed, and the encoded data written in the data writing area in the flash memory 5 is read out and compressed and expanded. The DCT unit 22 and the quantization unit 23 in the compression / decompression unit 7 perform an inverse DCT process and an inverse quantization process to expand the luminance signal data and the chrominance signal data (step S53). The luminance / color difference signal data is set in the encoder 8 line by line and encoded into a video signal, then D / A converted by the D / A converter 9, displayed on the monitor 10, and the processing is terminated.
[0068]
If the start code or the end code is not written in the start code writing area and the end code writing area in the flash memory 5 in the steps S51 and S52, the encoding process for one screen is in an intermediate state. Alternatively, it is determined that the encoded data is in a broken state, and the encoded data written in the data write area is deleted (step S54), and the process ends.
[0069]
As described above, in the electronic camera 1 of the present embodiment, the CPU 6 sets the event A by the encoding end interruption process using the wait time generated when the encoded data is written to the flash memory 5, thereby achieving the compression. The processing of writing the luminance / color difference signal data to the RAM G21 in the decompression unit 7 is performed, and the CPU 6 sets the event B by the encoding end interrupt processing, thereby reading and flashing the encoded data written in the RAMC 25. The process of writing the encoded data into the memory 5 is performed, and the process of setting the luminance / color difference signal data to the encoder 8 is performed asynchronously between the processes of setting the event A and the event B.
[0070]
For this reason, conventionally, during a wait time that occurs when writing data to a flash memory, data processing is performed in a distributed manner during a time that is wasted without performing any processing. It is possible to improve the data recording processing efficiency and shorten the recording processing time.
[0071]
Also, it is determined whether or not the encoding process of the image data for one screen is completed based on the start code and the end code written in the start code writing area and the end code writing area in the flash memory 5. Therefore, when incomplete coded data is recorded in the flash memory 5, the start code or the end code is not recorded. Thus, a situation in which an incomplete image is reproduced can be avoided.
[0072]
【The invention's effect】
BookAccording to the invention, during the wait time that occurs when data is written to the flash memory, the data processing is performed in a distributed manner during the time that is wasted without performing any processing. The recording processing efficiency can be improved, and the recording processing time can be shortened.
[0073]
Also bookAccording to the invention, when incomplete coded data is recorded in the flash memory, the start position or the end position is not recorded as identification information, so that it is determined that the data is incomplete coded data before reproduction.hand,A situation in which an incomplete image is reproduced can be avoided.
[Brief description of the drawings]
FIG. 1 is a block diagram of a main part of an embodiment of an electronic camera according to the present invention.
FIG. 2 is a block diagram of a compression / expansion unit in FIG. 1;
FIG. 3 is a diagram showing, in block units, a relationship between tasks executed by an interrupt control process of a CPU using a wait time generated in a process of writing encoded data to a flash memory.
FIG. 4 is a flowchart of an encoding end process of FIG. 3;
FIG. 5 is a flowchart of a task 1 in FIG. 3;
FIG. 6 is a flowchart of a task 2 in FIG. 3;
FIG. 7 is a flowchart of a task 3 in FIG. 3;
FIG. 8 is a diagram showing, in block units, a relationship between tasks 1 to 3 sequentially processed by an interrupt control process of a CPU and an encoding process in a compression / expansion unit.
FIG. 9 is a timing chart showing transition states of tasks 1 to 3 shown in block units in FIG. 8;
FIG. 10 is a flowchart of a reproducing process for reproducing encoded data written in a flash memory.
FIG. 11 is a flowchart for writing data to a conventional flash memory.
[Explanation of symbols]
1 electronic camera
2 CCD
3 A / D converter
4 DRAM
5 Flash memory
6 CPU
7 Compression / expansion unit
8 Encoder
9 D / A converter
10 Monitor
21 RAMG
22 DCT section
23 Quantization unit
24 Huffman coding unit
25 RAMC

Claims (4)

Imaging means for imaging a subject;
Digital conversion means for converting an image signal for one screen input from the imaging means into digital image data;
Compression means for encoding one screen of digital image data converted by the digital conversion means by a predetermined encoding method to generate one screen of encoded data;
Decompression means for decoding the encoded data,
Data conversion means for converting the digital image data decoded by the decompression means into a display signal for displaying on a display unit;
A data recording means for recording encoded data of one picture encoded by said compressing means,
Control means for executing processing relating to encoding processing in the compression means and data conversion processing in the data conversion means during a period in which encoded data for one screen is written in the data recording means;
An electronic camera comprising: The data recording unit records the coded data for one screen by dividing the coded data for one screen in a predetermined data unit at a predetermined writing timing,
The control unit utilizes a waiting time when dividing and writing one screen of encoded data into the data recording unit, and performs processing related to encoding processing in the compression unit and data conversion in the data conversion unit. 2. The electronic camera according to claim 1, wherein the processing is executed in a distributed manner. A recording control means for recording the identification information for identifying the coding start position and end of encoding the position of the digital image data for one screen to be coded by said compression means to said data recording means,
When reproducing the encoded data recorded in the data recording means, it is determined whether or not the encoded data exists for one screen based on the identification information, and whether or not the data is to be decoded by the decompression means is determined. Playback control means for controlling;
The electronic camera according to claim 1, further comprising: It said data recording means, electronic camera according to any one of claims 1 to 3, characterized by being configured by a flash memory.

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