JP3557645B2 - Electronic computer - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to an electronic computer having a fraction calculation function.
[0002]
[Prior art]
For example, an electronic computer having a fraction calculation function has been conventionally used in a desktop electronic computer and a portable electronic computer.
When a desired fraction is input in the order of an integer, a denominator, and a numerator, the computer provided with the fraction calculation function can display the keyed numerical values sequentially on the display unit and display fractions. Alternatively, it can perform arithmetic processing including fractions and reduce fractions, and is widely used as necessary, and is also used for teaching fraction calculation.
[0003]
[Problems to be solved by the invention]
However, in a conventional computer having a fraction calculation function, if a value such as a denominator or a numerator is erroneously input during the input of a fraction, after operating the clear key once to erase the entire fraction, Fractional input must be redone from the beginning. For example, if an integer, denominator, and numerator with a large number of digits are sequentially input, and only the numerator is incorrectly input, the input operation of the same number is repeated. And the operability is poor.
[0004]
Further, in the conventional electronic computer having the function of calculating a number, although it is possible to perform a reduction process of a fraction, the reduction process is performed only on a fraction input and displayed alone or a fraction displayed as a calculation result. At the same time, when the user designates a contract, only the result of the contract is immediately displayed, so that it is impossible to know the content of the contract, and this is particularly unsuitable for education.
[0005]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and when performing fraction reduction processing, it is possible to easily know what kind of reduction was performed without immediately displaying only the reduction result. An object of the present invention is to provide an electronic computer having an improved fraction processing function.
[0007]
[Means for Solving the Problems]
That is, the first computer according to the present invention comprises: input means for inputting a fraction; display means for displaying the fraction; and reduction instruction means for indicating a reduction of the fraction displayed on the display means; A reduction processing means for reducing the fraction displayed on the display means by the reduction instruction by the reduction instruction means, and a divisor when the fraction is reduced by the reduction processing means is displayed on the display means. And a divisor display means.
[0008]
A second computer according to the present invention is the first computer, wherein the reduction processing means is configured to reduce the immediately preceding fraction input by the input means. .
[0009]
Further, the third computer according to the present invention is the first computer, wherein the divisor processing means calculates a denominator of the fraction displayed on the display means and a least common divisor of the numerator. The divisor display means is configured to display the least common divisor.
[0010]
Further, a fourth computer according to the present invention comprises: input means for inputting a fraction; display means for displaying a fraction; and reduction instruction means for indicating a reduction of the fraction displayed on the display means. By the reduction instruction by the reduction instruction means, a reduction processing means for calculating the denominator and the least common divisor of the numerator by calculating the denominator and the least common divisor of the numerator, the reduction processing means, and the reduction processing means After displaying the least common divisor of the fraction calculated in the above for a predetermined time on the display means, and displaying the fraction reduced by the reduction processing means on the display means. It was done.
[0011]
Further, the fifth computer according to the present invention is the fourth computer, wherein the fourth computer is capable of determining whether or not the fraction displayed by the reduction process display means can be reduced. A symbol display means for displaying, on the display means, a symbol indicating that the reduction is possible when the reduction determination means determines that the reduction is possible.
[0013]
[Action]
In other words, in the first computer, when the fraction displayed on the display is subjected to the reduction processing in accordance with the reduction instruction by the reduction instruction means, the divisor is displayed on the display means. The reduced content of the fraction will be displayed.
[0014]
Also, in the second computer, in the first computer, the fraction immediately before being input and displayed by the input means is processed by about minutes, so that, for example, a state in which a plurality of fractions are input and displayed, or Even in the state where the operator is input, the reduction processing is performed on the last fraction input and displayed immediately before, and the content of the reduction is displayed.
[0015]
Further, in the third computer, in the first computer, the fraction displayed on the display means is subjected to the denominator and the least common denominator of the numerator, and is subjected to the divisor processing. The least common divisor will be displayed.
[0016]
Further, in the fourth computer, when a reduction instruction is given by the reduction instruction means, the fraction immediately input and displayed on the display means is calculated by the denominator and the least common divisor of the numerator, and the reduction processing is performed. Then, after the least common divisor of the fraction calculated in the reduction processing is displayed on the display means for a certain period of time, the reduced fraction is displayed on the display means.For example, a plurality of fractions are input and displayed. Even if the operator is in the input state or in the state in which the operator is input, the divisor processing is performed on the last fraction input and displayed immediately before that, and the divisor process is sequentially displayed.
[0017]
Further, in the fifth electronic computer, in the fourth electronic computer, it is determined whether or not the fraction displayed by the reduction process display means is possible to reduce, and when it is determined that the reduction is possible, Is displayed on the display means to indicate that a divisor is possible, so that a divisor process is performed on the last fraction input and displayed immediately before, and the divisor process is displayed not only sequentially. , It will be displayed that further reduction is possible.
[0019]
【Example】
An embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of an electronic circuit of an electronic computer having a fraction calculation function.
[0020]
This computer includes a central processing unit (CPU) 11.
The CPU 11 activates a system program stored in advance in the ROM 13 in response to a key operation signal from the key input unit 12 to execute operation control of each circuit unit. The CPU 11 includes the key input 12 and the ROM 13 In addition, a RAM 14 is connected, and a liquid crystal display unit 16 is connected via a display drive circuit 15.
[0021]
The key input unit 12 includes a numeric keypad 12a for inputting numerical values and a function key 12b including various operator keys and function keys. The key input unit 12 is operated according to a delimiter from an integer when performing fractional input. Key 12c, a "minute" key 12d operated in accordance with the denominator / numerator delimiter, a "correction" key 12e operated when correcting the content immediately before inputting a fraction, and an input display immediately before A "minute" key 12f or the like operated to reduce the set fraction is provided.
[0022]
The RAM 14 is provided with a work area 14a and an input type register 14b. In addition, an integer delimiter flag register F and a "minute" key 12d which are set when the "to" key 12c is operated in inputting a fraction are operated. And a numeric flag register E which is set when the numeric keypad (numerical key) 12a is operated.
[0023]
In the liquid crystal display unit 16, fractions input in accordance with the operation of the numeric keypad 12, the "to" key 12c, and the "minute" key 12d of the key input unit 12 are represented by an integer, a denominator, a denominator / numerator delimiter symbol, and a numerator. When the "correction" key 12e is operated, the numerical value or the delimiter symbol input immediately before the "correction" key 12e is deleted, and when the "about" key 12f is operated, the display section is displayed. In 16, after the least common divisor of the fraction input and displayed last is displayed for a certain period of time, the result of the reduction is displayed.
[0024]
Next, the operation of the computer having the fraction calculation function according to the above configuration will be described.
FIG. 2 is a flowchart showing the fraction processing by the computer having the above-mentioned fraction calculation function.
[0025]
FIG. 3 is a flowchart showing an input correction process accompanying the fraction processing of the electronic computer having the fraction calculation function.
FIG. 4 is a diagram showing a fraction display state corresponding to a key operation associated with a fraction input and correction process of the electronic computer having the fraction calculation function.
[0026]
That is, for example, when it is desired to input a fraction of “2 and 6/72”, when “2” of the ten key 12 a of the key input unit 12 is operated, it is determined that the numeric key is operated, and the denominator / RAM in the RAM 14 is operated. It is determined that both the numerator delimiter flag register G and the integer delimiter flag register F are not "1", and the keyed integer value "2" is written into the input expression register 14b (steps S1 → S2 → S3 → S4). .
[0027]
Then, the number flag register E in the RAM 14 is set to "1", and the integer value "2" written in the input type register 14b is displayed on the liquid crystal display 16 (steps S5 and S6).
[0028]
Subsequently, when the "to" key 12c of the key input unit 12 is operated, based on the key judgment, the integer delimiter flag register F in the RAM 14 is set to "1" and the numeric flag register E is set to "0". (Steps S7 → S8, S9).
[0029]
Then, although "7" of the numeric keypad 12a is supposed to be operated, if "6" is erroneously operated, it is determined that the numeric key has been operated, and then the denominator / numerator separation flag register G is determined not to be "1". At the same time, based on the determination that the integer delimiter flag register F is set to "1", the key input numerical value "6" is written into the input expression register 14b as a denominator (step S1 → S2 → S3 → S10).
[0030]
Then, the number flag register E in the RAM 14 is set to "1", and as shown in FIG. 4A, the numerical value "6" written in the input type register 14b follows the integer value "2". It is displayed at the denominator position of the liquid crystal display 16 (steps S5 and S6).
[0031]
Here, when the "correction" key 12e of the key input unit 12 is operated in order to correct the erroneously input denominator value "6" to the correct "7", the input correction processing in FIG. (Step S11 → SA).
[0032]
That is, in the input correction process (see FIG. 3), it is determined that the denominator / numerator delimiter flag register G in the RAM 14 is not "1", and both the integer delimiter flag register F and the numeric flag register E are "1". 4B, the least significant digit of the input and displayed denominator, that is, the erroneously input denominator value “6” is erased (see FIG. 4B). Steps A1 → A2 → A3 → A4 “→ S6”).
[0033]
When the correct numeric value of the denominator "7" is operated on the numeric keypad 12a, the input numeric value "7" is written as the denominator in the input expression register 14b through the steps S1, S2, S3, and S10. The number flag register E is set to "1", and is displayed at the denominator position of the liquid crystal display 16 following the integer value "2" (steps S5 and S6).
[0034]
Furthermore, if the "2" key on the numeric keypad 12a should be operated, if the "minute" key 12d is operated by mistake, the key judgment is made and the integer delimiter flag register F is currently set to "1". , The denominator / numerator delimiter flag register G is set to "1" and the numeric flag register E is reset to "0" (steps S12 → S13 → S14, S15).
[0035]
Then, as shown in FIG. 4C, a denominator / numerator delimiter symbol "-" is displayed on the liquid crystal display 16 following the numerical value "7" input to the denominator (step S6).
[0036]
Here, when the "correction" key 12e of the key input unit 12 is operated in order to erase the erroneously input denominator / numerator delimiter symbol "-", the process shifts to the input correction processing in FIG. 3 based on the key determination. (Step S11 → SA).
[0037]
That is, in the input correction process (see FIG. 3), the denominator / numerator delimiter flag register G in the RAM 14 is determined to be "1" and the numeric flag register E is determined to be "0". The denominator / numerator delimiter flag register G is reset to "0", and the numeric flag register E is set to "1" (steps A1->A5-> A6, A7).
[0038]
Then, as shown in FIG. 4D, the erroneously input and displayed denominator / numerator delimiter symbol "-" is deleted (steps SA and S6).
When the integer value “2” and the denominator value “7” are displayed and the subsequent denominator value “2” is operated, the input value “2” is obtained through the steps S1 → S2 → S3 → S10. Is written into the input expression register 14b as a denominator, the number flag register E in the RAM 14 is set to "1", and displayed on the liquid crystal display unit 16 as the denominator "72" (steps S5 and S6).
[0039]
When the "minute" key 12d is further operated, the key is determined, and the denominator / numerator delimiter flag register G is set based on the determination that the integer delimiter flag register F is currently set to "1". It is set to "1" and the number flag register E is reset to "0" (steps S12 → S13 → S14, S15).
[0040]
Then, the denominator / numerator delimiter symbol “−” is displayed on the liquid crystal display 16 following the numerical value “72” input to the denominator (step S6).
Then, "6" of the numeric keypad 12a is supposed to be operated as the number of numerators. If "3" is erroneously operated, it is determined that the numeric key has been operated, and then the denominator / numerator delimiter flag register G is set to "1". Based on the determination that the key input has been performed, the numerical value "3" input by the key is written as a numerator in the input expression register 14b (steps S1 → S2 → S16).
[0041]
Then, the number flag register E in the RAM 14 is set to "1", and as shown in FIG. 4E, the numerical value "3" written in the input type register 14b is changed to the integer value "2" and the denominator. The number “72” and the denominator / numerator delimiter symbol “−” are displayed at the numerator position of the liquid crystal display 16 (steps S5 and S6).
[0042]
Then, when "+" of the function key 12b is operated, the operator symbol "+" is displayed on the liquid crystal display unit 16.
Here, when the "correction" key 12e of the key input unit 12 is operated in order to correct the erroneously input number of molecules "3" to a correct "6", the input correction processing in FIG. The process proceeds (step S11 → SA).
[0043]
That is, in the input correction process (see FIG. 3), it is determined that the denominator / numerator delimiter flag register G in the RAM 14 is set to "1" and the numeric flag register E is set to "1". 4F, the least significant digit of the input and displayed molecule, that is, the number of incorrectly input molecules “3” is deleted (step A1 → A5 →). A8 “→ S6”).
[0044]
When the correct number of numerators "6" is operated on the numeric keypad 12a, the input numerical value "6" is written as a numerator into the input expression register 14b through the steps S1 → S2 → S16, and the number flag register in the RAM 14 is stored. E is set to “1”, and as shown in FIG. 4D, following the integer value “2”, denominator “72”, denominator / numerator delimiter symbol “−”, It is displayed (steps S5, S6).
[0045]
Thus, the desired fraction “2 and 6/72” is input and displayed.
On the other hand, when the integer value “2” and the “to” key 12c are input using the numeric keypad 12a and the input integer value “2” is to be corrected, the “correction” key 12e is operated. 3, the denominator / numerator delimiter flag register G in the RAM 14 is determined not to be "1", the integer delimiter flag register F is "1", and the numeric flag register E is "0". Based on the determination that there is, the integer delimiter flag register F is reset to "0" and the numeric flag register E is set to "1" (steps A1, A2, A3, A9, A10).
[0046]
Further, when the "correction" key 12e is operated, the denominator / numerator delimiter flag register G is determined not to be "1", and the integer delimiter flag register F is determined to be "0". The least significant digit of the input and displayed integer part, that is, the erroneously input integer value “2” is deleted, and a new integer value can be input (step A1 → A2 → A11).
[0047]
Further, in the fraction input processing, when there are a plurality of digits of the integer value, the denominator, or the numerator input immediately before, when the “correction” key 12e is repeatedly operated, in the input correction processing (see FIG. 3), In the case of an integer value, the steps A1 → A2 → A11 are repeated. In the case of a denominator, the steps A1 → A2 → A3 → A4 are repeated. In the case of a numerator, the steps A1 → A5 → A8 are repeated. Is repeated, and in each case, the data is sequentially deleted from the least significant digit each time the "correction" key 12e is operated.
[0048]
On the other hand, when there is no integer part in the fraction to be input, in a state where the input and display of the integer value are performed through steps S1 → S2 → S3 → S4, S5, and S6, the “and” key 12c is not operated. When the "minute" key 12d is directly operated, the integer-separated flag register F in the RAM 14 is determined to be "0" based on the key determination, and the numerical value input as an integer is displayed as a denominator. At the same time, the denominator / numerator delimiter flag register G is set to “1”, and the numeric flag register E is reset to “0”, so that the liquid crystal display unit 16 follows the numerical value input and displayed as the denominator, The denominator / numerator delimiter symbol "-" is displayed (steps S12 → S13 → S17, S14, S15, S6).
[0049]
As a result, the desired fraction is input and displayed, and if the "correction" key 12e is operated, at any time, only the integer value, the denominator, or the numerator input immediately before that is erased by one digit, Correction of erroneous input can be easily performed.
[0050]
As described above, instead of deleting only the integer value, the denominator, or the numerator one digit at a time, a numerical value configured for each integer, denominator, or numerator may be deleted.
[0051]
On the other hand, the fractional reduction process will be described below.
FIG. 5 is a flowchart showing a reduction process accompanying a fraction process of an electronic computer having the fraction calculation function.
[0052]
FIG. 6 is a diagram showing a reduction process display state corresponding to a key operation associated with a fraction input and a reduction process of the electronic computer having the fraction calculation function.
That is, in the fraction processing shown in FIG. 2, for example, as shown in FIG. 6A, a numerical value "1", a numerical value "2", a "minute" key 12d, and a numerical value "6" are sequentially operated by the ten keys 12a. Then, when the "minute" key 12f is operated in the state where the fraction "6/12" is input and displayed, the process shifts to the minute reduction process in FIG. 5 based on the key determination (step S18 → SB).
[0053]
Then, in the reduction processing in FIG. 5, first, it is determined that the fraction display is performed on the liquid crystal display unit 16, and therefore, the most recently inputted fraction (in this case, “6/12”) is displayed. In the denominator and the numerator, the least common divisor of "2" or more (in this case, "2") is calculated (step B1 → B2).
[0054]
Then, the divisible symbol “approximately” is displayed on the liquid crystal display unit 16, and if it is determined in step B 2 that the least common divisor of “2” or more has been calculated, the calculated least common divisor is calculated. “2” is displayed on the liquid crystal display unit 16 for a certain period of time as shown in FIG. 6B (steps B3, B4 → B5).
[0055]
Then, when it is determined that a predetermined time indicating the least common divisor “2” with respect to the fraction “6/12” has elapsed, a divisor process is executed based on the least common divisor “2”, and the divisor processing is performed. The result “3/6” is displayed on the liquid crystal display unit 16 as shown in FIG. 6B (steps B6 → B7, B8).
[0056]
Then, it is determined whether or not further reduction is possible based on whether or not there is a least common divisor of "2" or more with respect to the fraction "3/6" which is the result of the reduction displayed in step B8. In this case, since the least common divisor “3” exists for the fraction “3/6”, it is determined that the divisor can be reduced, and the divisible symbol “about” is converted to the divisor result “3/6”. (Steps B9 and S6).
[0057]
In this way, since the divisible symbol "approximately" is displayed together with the first dividable result "3/6", when the "approximately" key 12f is further operated, in the reduction processing shown in FIG. Since it is determined that the fraction "3/6" is displayed on the liquid crystal display unit 16, the denominator of the fraction and the least common divisor of "2" or more in the numerator (in this case, "3") are calculated (step 3). B1 → B2).
[0058]
Then, the divisible symbol “approximately” is displayed on the liquid crystal display unit 16, and if it is determined in step B 2 that the least common divisor of “2” or more has been calculated, the calculated least common divisor is calculated. “3” is displayed on the liquid crystal display unit 16 for a certain period of time as shown in FIG. 6C (steps B3, B4 → B5).
[0059]
When it is determined that a certain period of time indicating the least common divisor “3” for the fraction “3/6” has elapsed, a divisor process is executed based on the least common divisor “3”, and the divisor is calculated. The result “1/2” is displayed on the liquid crystal display unit 16 as shown in FIG. 6C (steps B6 → B7, B8).
[0060]
Then, it is determined whether or not further reduction is possible based on whether or not there is a least common divisor of "2" or more with respect to the fraction "1/2" which is the second reduction result displayed in step B8. In this case, since the least common divisor of “2” or more does not exist for the fraction “1/2”, it is determined that the divisor cannot be reduced, and the dividable symbol “subtract” is deleted. Then, only the reduction result "1/2" is displayed (step B9 → B10, S6).
[0061]
Thereby, the divisor process consisting of the least common divisor and the divisor result corresponding to the divisor to be reduced displayed on the display unit 16 is sequentially staged together with the divisor symbol indicating whether or not a further divisor is possible. Will be displayed.
[0062]
Therefore, according to the electronic computer having the fraction calculating function having the above-described configuration, the fraction input using the numeric keypad 12a, the “to” key 12c, and the “minute” key 12d of the key input unit 12 has its integer, denominator, and numerator. Are written in the input type register 14b in the RAM 14 in the input order, and displayed on the liquid crystal display unit 16, when the numerical correction of the displayed fraction is indicated by the "correction" key 12e, Is set when the "to" key 12c is operated, the denominator / numerator separation flag register G which is set when the "minute" key 12d is operated, and when the ten key (numerical key) 12a is operated. Judgment is made from the content of each flag of the numeric flag register E to be set, and only the immediately preceding input content, that is, the lowest value in any of the integer value, denominator and numerator Since only digits are erased, it is not necessary to clear the entire inputted fraction, it can be corrected by erasing only the easily the number entered by mistake.
[0063]
Further, according to the electronic computer having the fraction calculating function having the above-described configuration, when an instruction for a minute is given by the “about minutes” key 12 f of the key input unit 12, the key input unit 12 is operated to immediately display the liquid crystal display unit 16. Is calculated by calculating the least common divisor of the denominator and the numerator of “2” or more, and performing the divisor processing. The least common divisor of the fraction calculated in the divisor processing is fixed on the liquid crystal display unit 16. After the time is displayed, the fraction as a result of the reduction is displayed on the liquid crystal display unit 16, so that, for example, even if a plurality of fractions are input or displayed, or if an operator is input, the The user can perform a reduction process on the last fraction input and displayed on the screen, and can successively display the reduction process to inform the user of the content of the reduction.
[0064]
Furthermore, it is determined whether or not further reduction is possible based on whether or not there is a least common divisor of “2” or more. Since the reduced symbol “approximate” indicating that there is a certain fraction is displayed on the liquid crystal display unit 16 together with the fraction, the user looks at the reduced symbol and operates the “approximate” key 12f again to perform further reduction processing. Can be executed.
[0065]
【The invention's effect】
As described above, according to the first computer of the present invention, when the fraction displayed on the display means is subjected to the reduction processing in response to the reduction instruction by the reduction instruction means, the divisor is displayed on the display means. , The content of the fraction is displayed.
[0066]
Further, according to the second computer of the present invention, in the first computer, the fraction immediately before input and displayed by the input means is reduced by approximately minutes, so that a plurality of fractions are input and displayed, for example. Even in the state or the state where the operator is input, the reduction processing is performed on the last fraction input and displayed immediately before, and the details of the reduction are displayed.
[0067]
Further, according to the third computer of the present invention, in the first computer, the fraction displayed on the display means is subjected to the reduction by calculating its denominator and the least common divisor of the numerator. At the same time, the least common divisor is displayed.
[0068]
Further, according to the fourth computer of the present invention, when a reduction instruction is given by the reduction instruction means, the fraction immediately input and displayed on the display means is calculated by the denominator and the least common divisor of the numerator. After the fraction processing is performed, the least common divisor of the fraction calculated in the divisor processing is displayed on the display means for a certain period of time, and then the fraction obtained by the divisor processing is displayed on the display means. Even in a state where an input is displayed or an operator is input, a reduction process is performed on the last fraction input and displayed immediately before that, and the reduction process is sequentially displayed.
[0069]
Further, according to the fifth computer of the present invention, in the fourth computer, it is determined whether or not the fraction displayed by the reduction process display means can be reduced, and it is determined that the reduction is possible. In this case, a symbol indicating that dichotomization is possible is displayed on the display means, so that a dichotomization process is performed on the last fraction input and displayed immediately before, and the dichotomization process is sequentially displayed. In addition, it is displayed that further reduction can be performed.
[0070]
Therefore, when performing fraction reduction processing, the fraction processing function has been improved so that it is possible to easily know what kind of reduction was performed without immediately displaying only the reduction result. An electronic computer can be provided.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an electronic circuit of an electronic computer having a fraction calculation function according to an embodiment of the present invention.
FIG. 2 is a flowchart showing fraction processing by an electronic computer having the fraction calculation function.
FIG. 3 is a flowchart showing an input correction process accompanying a fraction process of an electronic computer having the fraction calculation function.
FIG. 4 is a diagram showing a fraction display state corresponding to a key operation accompanying a fraction input and a correction process of the electronic computer having the fraction calculation function.
FIG. 5 is a flowchart showing a reduction process accompanying a fraction process of an electronic computer having the fraction calculation function.
FIG. 6 is a view showing a fraction process display state corresponding to a key operation associated with a fraction input and a fraction process of the electronic computer having the fraction calculation function.
[Explanation of symbols]
11: central processing unit (CPU), 12: key input unit, 12a: numeric keypad, 12b: function key, 12c: "to" key, 12d: "minute" key, 12e: "correction" key, 12f: "about minute" , Key, 13 ROM, 14 RAM, 14a work area, 14b input expression register, F integer flag register, G denominator / numerator flag register, E numeric flag register, 15 display drive circuit, 16 ... Liquid crystal display unit.

Claims (5)

An input means for inputting a fraction,
Display means for displaying fractions,
Reduction instruction means for indicating the reduction of the number of minutes displayed on the display means,
Reduction processing means for reducing the number of minutes displayed on the display means by the reduction instruction by the reduction instruction means;
A divisor display means for displaying a divisor when the fraction is reduced by the divisor processing means on the display means,
An electronic computer comprising: 2. The computer according to claim 1, wherein said reduction processing means reduces the immediately preceding fraction input by said input means. The divisor processing means calculates the denominator of the fraction displayed on the display means and the least common divisor of the numerator and divides it, and the divisor display means displays the least common divisor. The electronic computer according to claim 1. An input means for inputting a fraction,
Display means for displaying fractions,
Reduction instruction means for indicating the reduction of the number of minutes displayed on the display means,
By the reduction instruction by the reduction instruction means, the fraction input immediately before and displayed on the display means, the denominator and the least common divisor of the numerator to calculate and reduce the fraction,
After displaying the least common divisor of the fraction calculated by the divisor processing means on the display means for a certain period of time, the divisor process display means for displaying the divisor reduced by the divisor processing means on the display means When,
An electronic computer comprising: A reduction determination means for determining whether or not the fraction displayed by the reduction process display means can be reduced;
A symbol display means for displaying, on the display means, a symbol indicating that reduction is possible when it is determined that the reduction is possible by the reduction determination means;
The electronic computer according to claim 4, further comprising:

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