JP3558608B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and more particularly to an output data voltage level conversion circuit configuration in a semiconductor memory circuit device in which an internal circuit is driven by an internal power supply and an output driver is driven by an external power supply.
[0002]
[Prior art]
In recent years, semiconductor memory circuit devices tend to have lower withstand voltage of memory cells due to miniaturization of design standards. For this reason, in a general semiconductor memory device, an internal circuit is operated using an internal power supply (IVCC: Internal VCC) which is internally stepped down to a voltage lower than an external power supply (EVCC: External VCC), and an output driver unit is provided with an external power supply. It operates using EVCC. In such a semiconductor memory circuit device, a power supply having a different voltage is used between the output driver section and the other internal circuits. Therefore, the data voltage level is set to the internal power supply level before the read data is transferred from the internal circuit to the output driver section. It is necessary to convert the voltage level to the external power supply voltage level. For the conversion of the data voltage level, for example, voltage level conversion is performed using a level shifter circuit.
[0003]
[Problems to be solved by the invention]
However, as described above, the conventional semiconductor memory circuit device converts a data voltage level from an internal power supply level to an external power supply level by a level shifter circuit provided at a preceding stage for transferring read data from an internal circuit to an output driver section by a level shifter circuit. ing. For this reason, a data access delay occurs due to the number of stages of the level shifter circuit and an operation peculiar to the level shifter circuit. It is conceivable to deal with data access delay caused by the operation unique to the level shifter circuit by increasing the current, but this leads to further disadvantages such as increased current consumption and unexpected noise. Would.
[0004]
Also, in order to respond to the ever-increasing integration of semiconductor memory circuit devices, the realization of a semiconductor memory circuit device configuration in which the level shifter circuit provided in the previous stage of the output driver section is omitted is necessary to secure chip space. It is also highly expected that it will be connected.
[0005]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor integrated circuit device according to the present invention includes a semiconductor operating with an external power supply having an external power supply voltage and an internal power supply having an internal power supply voltage internally reduced to a voltage lower than the external power supply voltage. In an integrated circuit, an internal circuit that includes a memory cell and operates using an internal power supply, a current mirror amplifier that operates using the internal power supply and receives and amplifies a data signal read from the memory cell, and an external power supply A differential amplifier that operates using and receives and amplifies the data signal at the internal power supply voltage level output from the current mirror type amplifier and converts it to an external power supply voltage level. And an output driver for outputting a signal.
[0006]
BEST MODE FOR CARRYING OUT THE INVENTION
First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of the present invention. FIG. 2 is a timing chart showing the operation of the first embodiment of the present invention. The semiconductor memory circuit shown in FIG. 1 includes a current mirror type amplifier 2 for amplifying data read from a memory cell onto a data bus 1 by selecting a column line (not shown), and a data output from the current mirror type amplifier 2. , A data latch circuit 4 for latching data output from the differential amplifier 3 in accordance with a data latch signal DATAL, and an output for outputting data output from the data latch circuit 4 to the outside. And a driver 5.
[0007]
The current mirror type amplifier 2 uses the internal power supply IVCC as a power supply, and amplifies data appearing at the nodes n1 and n1B on the data bus 1 in accordance with the read amplifier active signal RAC. The differential amplifier 3 includes four PMOS transistors P1 to P4, three NMOS transistors N1 to N3, and two inverters M1 and M2, uses an external power supply EVCC as a power supply, and responds to a row address enable signal RAE. The data appearing at the output nodes n2 and n2B of the current mirror type amplifier 2 is amplified. Since the power supply used by the differential amplifier 3 is the external power supply EVCC, the data potential levels of the output nodes n4 and n4B of the differential amplifier 3 are converted into signals of the external power supply voltage level (EVCC level).
[0008]
The “High” level in the read amplifier active signal RAC, the row address enable signal RAE, and the data latch signal DATAL use the external power supply voltage level (EVCC level). The row address enable signal RAE is a signal obtained by delaying the read amplifier active signal RAC using two stages of inverters M3 and M4.
[0009]
Next, the operation will be described. The data on the data bus 1 is amplified by the current mirror type amplifier 2 in response to the read amplifier active signal RAC changing from “Low” level to “High” level. At this time, the output nodes n2 and n2B of the current mirror type amplifier 2 start to be divided into “High” level and “Low” level, respectively. The data appearing at the output nodes n2 and n2B are further amplified in the next-stage differential amplifier 3 in response to the change of the row address enable signal RAE from “Low” level to “High” level, and output from the inverter M2. You. In the data latch circuit 4 at the next stage, data appearing at the output node 4n of the differential amplifier 3 is latched in response to the change of the data latch signal DATAL, which is a one-shot pulse signal, from the “Low” level to the “High” level. You. Then, the output data of the data latch circuit 4 is output from the next stage output driver 5 to the outside.
[0010]
In the present embodiment, since the internal power supply IVCC is used for the first-stage current mirror type amplifier 2 and the external power supply EVCC is used for the next-stage differential amplifier 3, it is conventionally provided before the output driver section. The semiconductor memory circuit device configuration without the level shifter circuit can be realized. As a result, the data access operation of the semiconductor memory circuit can be speeded up.
[0011]
Second Embodiment FIG. 3 is a circuit diagram showing a second embodiment of the present invention. The difference from the first embodiment is as follows. The point that the NMOS transistor N3 on the ground voltage VSS side constituting the differential amplifier 13 is divided into N4 and N5. The control circuit 16 inputs a signal based on the output of the differential amplifier 13 to the control gate of the NMOS transistor N4 and the row address enable signal RAE to the control gate of the NMOS transistor N5. The control circuit 16 controls switching of the conduction / non-conduction of the NMOS transistors N4 and N5. In the present embodiment, an example in which the NMOS transistor N3 is divided into two parts will be described. However, the present invention is not limited to two parts and can be divided into three or more parts.
[0012]
The semiconductor memory circuit according to the present embodiment has the same configuration as that of FIG. 1 described in the first embodiment, except that the control circuit 16 is connected to the differential amplifier 13. Omitted. The differential amplifier 13 includes four PMOS transistors P1 to P4, four NMOS transistors N1, N2, N4, N5, and two inverters M1, M2. The differential amplifier 13 uses an external power supply EVCC as a power supply, and amplifies data appearing at the output nodes n2 and n2B of the current mirror type amplifier 2 according to the row address enable signal RAE. Since the power supply used by the differential amplifier 13 is the external power supply EVCC, the data potential levels of the output nodes n4 and n6 of the differential amplifier 13 are converted into signals of the external power supply voltage level (EVCC level).
[0013]
The control circuit 16 includes two stages of inverters M3 and M4 for generating and outputting a row address enable signal RAE from the read amplifier active signal RAC, and two signals appearing at two output nodes n4 and n6 of the differential amplifier 13, respectively. A three-input NOR circuit M5 to which a signal appearing at the output node n7 of the inverter M3 is input. The output side of the three-input NOR circuit M5 is connected to the control gate of the NMOS transistor N4, and the output side (row address enable signal RAE) of the inverter M4 is connected to the control gate of the NMOS transistor N5.
[0014]
Next, the operation of the second embodiment will be described. The description overlapping with the operation of the first embodiment will be omitted, and the operation of the differential amplifier 13 which is a feature of the second embodiment will be described. FIG. 4 is a timing chart showing the operation of the second embodiment of the present invention. When read amplifier active signal RAC is at "Low" level (differential amplifier 13 is not operating), output node n7 of 3-input NOR circuit M5 is at "Low" because output node n7 of inverter M3 is at "High" level. "Level. Therefore, both the NMOS transistors N4 and N5 are off. On the other hand, when the read amplifier active signal RAC is at the “High” level (when the differential amplifier 13 is operating), the output node n7 of the inverter M3 is at the “Low” level, and when the operation of the differential amplifier 13 starts, the output node Since n4 and n6 are both at "Low" level, the output node n8 of the three-input NOR circuit M5 is at "High" level. At this time, since the row address enable signal RAE is also at the “High” level, both the NMOS transistors N4 and N5 are turned on.
[0015]
Thereafter, one of the output nodes n4 and n6 is set to the "High" level due to the data amplification in the differential amplifier 13. As a result, the output node n8 of the three-input NOR circuit M5 transitions from “High” level to “Low” level, so that the NMOS transistor N4 is turned off. The NMOS transistor N4 is reset once when the read amplifier active signal RAC goes to the “Low” level, and keeps the off state until the read amplifier active signal RAC goes to the “High” level again.
[0016]
As in the first embodiment, the “High” level of the read amplifier active signal RAC, row address enable signal RAE, and data latch signal DATAL used in the present embodiment all use the external power supply voltage level (EVCC level).
[0017]
In the present embodiment, as in the first embodiment, the data access operation of the semiconductor memory circuit can be speeded up, and the current consumption of the differential amplifier 13 is reduced when the output data of the differential amplifier 13 is determined. can do. This advantage can also be understood from FIG. FIG. 4 shows that the active period B of the differential amplifier 13 in this embodiment is shorter than the active period A of the conventional differential amplifier. Such a reduction in the active period of the differential amplifier realizes a reduction in current consumption. In addition, since the differential amplifier 13 is not completely turned off, in other words, the internal node of the differential amplifier 13 does not enter a floating state, no malfunction occurs due to noise or the like.
[0018]
Third Embodiment FIG. 5 is a circuit diagram showing a third embodiment of the present invention. The difference from the first embodiment is as follows. The point that NMOS transistors N6 and N7 are connected in parallel to the ground voltage VSS side of the differential amplifier 23. The control circuit 26 inputs a signal based on the burn-in signal BI to the control gate of the NMOS transistor N6 and the row address enable signal RAE to the control gate of the NMOS transistor N7. The control circuit 26 controls switching of the conduction / non-conduction of the NMOS transistors N6 and N7. In this embodiment, an example in which two NMOS transistors are connected in parallel to the ground voltage VSS is described. However, the number of NMOS transistors is not limited to two, and three or more NMOS transistors can be connected in parallel. .
[0019]
The semiconductor memory circuit according to the present embodiment has the same configuration as that of FIG. 1 described in the first embodiment, except that the control circuit 26 is connected to the differential amplifier 23. Omitted. The differential amplifier 23 includes four PMOS transistors P1 to P4, four NMOS transistors N1, N2, N6, N7, and two inverters M1, M2. The differential amplifier 23 uses an external power supply EVCC as a power supply, and amplifies data appearing at output nodes n2 and n2B of the current mirror type amplifier 2 according to a row address enable signal RAE. Since the power supply used by the differential amplifier 13 is the external power supply EVCC, the data potential levels of the output nodes n4 and n6 of the differential amplifier 13 are converted into signals of the external power supply voltage level (EVCC level).
[0020]
The control circuit 26 has two stages of inverters M3 and M4 for generating and outputting a row address enable signal RAE from the read amplifier active signal RAC, and a two-input which receives a burn-in signal BI and a signal appearing at the output node n6 of the inverter M3. And a NOR circuit M6. The output side of the two-input NOR circuit M6 is connected to the control gate of the NMOS transistor N6, and the output side (row address enable signal RAE) of the inverter M4 is connected to the control gate of the NMOS transistor N7.
[0021]
Next, the operation of the second embodiment will be described. A description overlapping with the operation of the first embodiment will be omitted, and the operation of the differential amplifier 23 during a burn-in test, which is a characteristic part of the second embodiment, will be described. At the time of the burn-in test, the burn-in signal BI transits from the “Low” level to the “High” level, so that the output node n7 of the two-input NOR circuit M6 becomes the “Low” level. As a result, since the NMOS transistor N6 is turned off and no current flows, the current flowing through the differential amplifier 23 is narrowed down, and the operation becomes slower than in the normal operation. The burn-in test is a kind of accelerated test of a semiconductor device, and is a test in which a semiconductor device is operated in a relatively loose cycle under a high temperature and high voltage environment.
[0022]
In the present embodiment, as in the first embodiment, the data access operation of the semiconductor memory circuit can be speeded up, and the current flowing through the differential amplifier 23 is narrowed down during the burn-in test, so that it is slower than in the normal operation. Operation can be performed. As a result, an increase in peak current due to a high voltage can be suppressed, and malfunction of the memory circuit due to power supply noise during a burn-in test can be prevented.
[0023]
As in the first and second embodiments, the “High” level of the read amplifier active signal RAC, the row address enable signal RAE, and the data latch signal DATAL used in the present embodiment all correspond to the external power supply voltage level (EVCC level). Used. Also, the “High” level of the burn-in signal BI uses the external power supply voltage level (EVCC level).
[0024]
【The invention's effect】
As described in detail above, according to the present invention, it is possible to realize a semiconductor memory circuit device configuration in which the level shifter circuit provided in the preceding stage of the output driver section is omitted. As a result, it is possible to speed up the data access operation in the memory circuit and to secure a chip space without using a level shifter circuit. According to another aspect of the present invention, it is possible to reduce current consumption and prevent malfunction due to noise or the like.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
FIG. 2 is a timing chart showing the operation of the first embodiment of the present invention.
FIG. 3 is a circuit diagram showing a second embodiment of the present invention.
FIG. 4 is a timing chart showing an operation of the second exemplary embodiment of the present invention.
FIG. 5 is a circuit diagram showing a third embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Data bus 2 Current mirror type amplifier 3, 13, 23 Differential amplifier 4 Data latch circuit 5 Output driver section 16, 26 Control circuit

Claims (3)

In a semiconductor integrated circuit operating with an external power supply having an external power supply voltage and an internal power supply having an internal power supply voltage internally reduced to a voltage lower than the external power supply voltage,
An internal circuit including a memory cell and operating using the internal power supply;
A current mirror amplifier that operates using the internal power supply and receives and amplifies a data signal read from the memory cell;
A differential amplifier connected between the external power supply and ground, receiving and amplifying the data signal of the internal power supply voltage level output from the current mirror type amplifier, and converting the data signal to the external power supply voltage level;
An output driver that operates using the external power supply and outputs a data signal of the external power supply voltage level;
A semiconductor integrated circuit device, comprising: a control circuit that switches conduction / non-conduction of a MOS transistor on the ground side of the differential amplifier according to a burn-in permission signal and an activation signal. The current mirror type amplifier, a semiconductor integrated circuit device according to claim 1, characterized in that the amplification of the data in accordance with a read amplifier active signal. The differential amplifier, a semiconductor integrated circuit device according to claim 1, characterized in that the amplification of the data in accordance with a row address enable signal.

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