JP3559840B2 - Super frame synchronization signal generation circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a superframe synchronization signal generation circuit that generates a signal synchronized with a superframe (hereinafter, referred to as a superframe synchronization signal) from a transmission frame of digital satellite broadcasting.
[0002]
[Prior art]
In digital satellite broadcasting, a format based on hierarchical transmission is used. In this format, one superframe is composed of eight frames, and a transmission multiplexing configuration control (TMCC) signal indicating information such as frame transmission information and a modulation method is inserted from the top of the superframe. In addition, signal processing is performed for each superframe, for example, multiplexing in digital satellite broadcasting is performed in superframe units.
[0003]
However, when multiplexing data in accordance with the frame configuration defined in digital satellite broadcasting, unless a TMCC signal is formed at the beginning of a transmission frame in accordance with the data configuration, the transmission channel encoder at the subsequent stage forms a multiplex configuration. Therefore, digital modulation cannot be applied.
[0004]
For example, when a superframe synchronization signal is transmitted together with a transport stream (TS), the transport stream can be formed into a frame based on the superframe synchronization signal, but the superframe synchronization signal is transmitted. If not, it is necessary to generate a superframe synchronization signal synchronized with the head of the superframe.
[0005]
Also, on the receiving side, it is necessary to detect the head of the superframe when separating the deinterleaved multiplexed transport stream into individual transport streams.
[0006]
The generation of the conventional superframe synchronization signal is specifically shown in FIG.
[0007]
FIG. 2A schematically shows an input transport stream, and FIG. 3 schematically shows one superframe for each frame. One slot is composed of 204 bytes, one frame is composed of 48 slots, and one superframe is composed of eight frames. 1B95h (W1) is a frame synchronization word, and A340h (W2) and 5CBFh (W3) are superframe identification synchronization words.
[0008]
At the beginning of each slot, a TMCC signal including a synchronization word is added one byte at a time. Specifically, the frame synchronization word W1 is one byte at the beginning of the first and second slots of each frame, the superframe identification synchronization word W2 is one byte at the beginning of the eleventh and twelfth slots of the first frame, The superframe identification synchronization word W3 is added one byte at a time to the head of the eleventh and twelfth slots of the second to eighth frames. Here, h indicates a hexadecimal number.
[0009]
FIG. 2B shows a configuration of a conventional superframe synchronization signal generation circuit 20.
[0010]
The superframe synchronization signal generation circuit 20 stores a memory 21 for storing 204 bytes of the input transport stream, a memory 22 for storing 12 slots of the transport stream read from the memory 21, and a 204 byte of the transport stream read from the memory 22. A synchronizing word W2 is detected by a synchronizing word W2 detector 24 from the input and output of the memory 21 and a synchronizing word W1 is detected by a synchronizing word W1 detector 25 from the input and output of the memory 23. Upon detection, the super frame synchronization signal transmission circuit 26 transmits a super frame synchronization signal and supplies the super frame synchronization signal to the memory 23 to output a transport stream in synchronization with the super frame synchronization signal.
[0011]
[Problems to be solved by the invention]
As described above, conventionally, the data of the transport stream for 12 slots is stored in the memory 22 and the synchronizing words (W1, W2) inserted in the TMCC portion at the head of the frame are detected, and the superframe of the superframe is detected. Although the head is recognized, it has to have a memory capacity of 12 slots, and there is a problem that the circuit scale becomes enormous.
[0012]
SUMMARY OF THE INVENTION An object of the present invention is to provide a superframe synchronization signal generation circuit that requires a small circuit scale.
[0015]
[Means for Solving the Problems]
Super frame synchronization signal generating circuit according to claim 1 of the present invention is a super-frame synchronizing signal generating circuit for generating a super-frame synchronizing signal synchronized from the transmission frame in the super frame of the digital satellite broadcasting,
A first comparator for sequentially comparing the input transport stream to detect the first half of the frame synchronization word W1, a second comparator for detecting the second half of the superframe identification synchronization word W2, and a superframe identification synchronization word A third comparator for detecting the first half of W2, a fourth comparator for detecting the second half of the frame identification synchronization word W1, and a fifth comparator for detecting the first half of the frame synchronization word W1 are cascaded. Said comparison means;
A first counter that counts 204 bytes of the input transport stream of the fifth comparator from the time when the fifth comparator detects the first half of the frame synchronization word W1, and a fourth comparator that counts the frame synchronization word W1. A second counter that counts the input transport stream of the fourth comparator for 10 slots from the time when the latter half is detected and the counting of 204 bytes by the first counter is completed, and a superframe is calculated by the third comparator. A third counter that counts 204 bytes of the input transport stream of the third comparator from the time when the first half of the identification frame synchronization word W2 is detected and the counting of 10 slots by the second counter is completed; 2 detects the latter half of the frame synchronizing word W2 for superframe identification and uses the third counter 4 Upon completion of the counting of the bytes of the fourth counter for counting the input transport stream of the second comparator over superframes remaining minutes,
And transmitting a detection signal obtained by detecting the first half of the frame synchronization word W1 by the first comparator when the counting of the remaining one superframe by the fourth counter is completed, as a superframe synchronization signal. .
[0016]
According to the super frame synchronization signal generating circuit according to claim 1 of the present invention, the first half detection and counting of the first counter of the fifth frame synchronization word W1 by the comparator are finished and the frame synchronization by the fourth comparator The frame synchronization word W1 in the first frame is detected by the latter half detection of the word W1, the counting of the second counter is completed, the first half detection of the superframe identification synchronization word W2 by the third comparator, and the end of the third counter. The second comparator detects the superframe identification synchronization word W2 in the second half, thereby detecting the superframe identification synchronization word W2 in the first frame. Therefore, the end of counting by the fourth counter is the beginning of the next superframe, and at this time, a signal when the first half of the frame synchronization word W1 is detected by the first comparator is output as a superframe synchronization signal. You.
[0017]
As described above, according to the superframe synchronization signal generation circuit according to the present invention, the comparator and the counter can generate the superframe synchronization signal, and the circuit size can be small.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of a superframe synchronization signal generation circuit according to the present invention will be described.
[0019]
FIG. 1 is a block diagram showing a configuration of a superframe synchronization signal generation circuit according to one embodiment of the present invention.
[0020]
FIG. 1 (a) is a rewrite of FIG. 2 (a).
[0021]
FIG. 1B is a block diagram illustrating a configuration of the superframe synchronization signal generation circuit 15 according to the embodiment of the present invention.
[0022]
The input transport stream has a comparator 1 for detecting 1Bh indicating the first half of the cascade-connected synchronization word W1, a comparator 2 for detecting 40h indicating a second half of the synchronization word W2, and a first half of the synchronization word W2. These are sequentially supplied to a comparator 3 for detecting A3h indicating the portion, a comparator 4 for detecting 95h indicating the second half of the synchronization word W1, and a comparator 5 detecting 1Bh indicating the first half of the synchronization word W1.
[0023]
The input transport stream is compared with the first half 1Bh of the synchronization word W1 set in the comparator 1, and the first half 1Bh of the synchronization word W1 in the input transport stream is detected. The transport stream output from the comparator 1 is compared with the latter half 40h of the synchronization word W2 set in the comparator 2, and the latter half 40h of the synchronization word W2 in the transport stream is detected. The transport stream output from the comparator 2 is compared with the first half A3h of the synchronization word W2 set in the comparator 3, and the first half A3h of the synchronization word W2 in the transport stream is detected.
[0024]
Similarly, the transport stream output from the comparator 3 is compared with the latter part 95h of the synchronization word W1 set in the comparator 4, and the latter part 95h of the synchronization word W1 in the transport stream is detected. The transport stream output from the comparator 4 is compared with the first half 1Bh of the synchronization word W1 set in the comparator 5, and the first half 1Bh of the synchronization word W1 in the transport stream is detected.
[0025]
When the comparator 5 detects the first half 1Bh of the synchronizing word W1 from the transport stream, a detection pulse is output to the 204 byte counter 6, and the counting of the input transport stream of the comparator 5 is performed by the 204 byte counter 6. Be started. This state is a state in which the first half 1Bh of the synchronization word W1 has been detected in any of the first to eighth frames.
[0026]
In this state, the comparator 4 compares the transport stream input after the 204-byte counter 6 starts counting and the second half 95h of the synchronization word W1 to be inserted next. .
[0027]
During the counting period of the 204 byte counter 6, the first half 1Bh of the synchronizing word W1 may be detected again. The input terminal to which the pulse is applied is disabled.
[0028]
When the counting of 204 bytes of the input transport stream of the comparator 4 is completed by the 204 byte counter 6, a counting end pulse is output. When this counting end pulse is output, the counting for the first slot in any of the first to eighth frames ends, and this corresponds to a state where the second half 95h of the synchronization word W1 in the second slot is detected. I do.
[0029]
The counting end pulse and the detection pulse obtained by detecting the second half 95h of the synchronizing word W1 in the comparator 4 are supplied to the AND gate 7, and the output of the AND gate 7 is supplied as a detection pulse to the counter 8 for 10 slots. The counting of transport streams input to the device 4 is started. This state corresponds to a state in which the second half 95h of the synchronization word W1 of the second slot in any of the first to eighth frames is detected.
[0030]
At this time, if the second half 95h of the synchronizing word W1 is not detected in the comparator 4, the 204 byte counter 6 is enabled again and the operation returns to the above-described first operation.
[0031]
Subsequently, the comparator 3 compares the transport stream input after the start of counting in the counter 8 for 10 slots with the first half A3h of the synchronization word W2 to be inserted next.
[0032]
In the same procedure, when the 10-slot counter 8 counts the transport stream input to the comparator 4 for 10 slots and the comparator 3 detects the first half A3h of the synchronization word W2, the AND gate 9 , A detection pulse is sent to the 204 byte counter 10, and the transport stream input to the comparator 3 is counted in the 204 byte counter 10. In this state, the first half A3h of the synchronization word W2 in the eleventh slot of the first frame is detected.
[0033]
When the second half 40h of the synchronizing word W2 is detected by the comparator 2 when the counting of 204 bytes of the input transport stream of the comparator 3 is completed by the 204 byte counter 10, the detection pulse is output from the AND gate 11 to the remaining superframe. The transport stream transmitted to the counter 12 and input to the comparator 2 is counted by the counter 12 for the remaining superframe.
[0034]
The remaining slots (372 slots (36 + 7 × 48 slots)) are counted in the superframe remaining counter 12. When this counting is completed, it should be the head of the next superframe, and the comparator 1 detects the first half 1Bh of the synchronization word W1. By this detection, the superframe synchronization signal and the transport stream input to the comparator 1 are output together.
[0035]
By repeating this, a superframe synchronization signal is always transmitted from the transport stream.
[0036]
As described above, the superframe synchronization signal generation circuit 15 detects the synchronization word in the TMCC part from the transmitted transport stream, counts the number of transport streams between the synchronization words, and generates the superframe synchronization signal. Will be generated.
[0037]
【The invention's effect】
As described above, according to the superframe synchronization signal generation circuit according to the present invention, the superframe synchronization signal generation circuit can be configured with a plurality of counters without using a large-capacity memory, and the circuit configuration of the superframe synchronization signal generation circuit is small. No.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a superframe synchronization signal generation circuit according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration of a conventional superframe synchronization signal generation circuit.
FIG. 3 is a schematic diagram for explaining one superframe.
[Explanation of symbols]
1-5 Comparators 6 and 10 204 byte counter 8 10 slot counter 12 Superframe remaining counter

Claims (1)

A superframe synchronization signal generation circuit that generates a superframe synchronization signal synchronized with a superframe from a transmission frame of digital satellite broadcasting,
A first comparator for sequentially comparing the input transport stream to detect the first half of the frame synchronization word W1, a second comparator for detecting the second half of the superframe identification synchronization word W2, and a superframe identification synchronization word A third comparator for detecting the first half of W2, a fourth comparator for detecting the second half of the frame identification synchronization word W1, and a fifth comparator for detecting the first half of the frame synchronization word W1 are cascaded. Said comparison means;
A first counter that counts 204 bytes of the input transport stream of the fifth comparator from the time when the fifth comparator detects the first half of the frame synchronization word W1, and a fourth comparator that counts the frame synchronization word W1. A second counter that counts the input transport stream of the fourth comparator for 10 slots from the time when the latter half is detected and the counting of 204 bytes by the first counter is completed, and a superframe is calculated by the third comparator. A third counter that counts 204 bytes of the input transport stream of the third comparator from the time when the first half of the identification frame synchronization word W2 is detected and the counting of 10 slots by the second counter is completed; 2 detects the latter half of the frame synchronizing word W2 for superframe identification and uses the third counter 4 Upon completion of the counting of the bytes of the fourth counter for counting the input transport stream of the second comparator over superframes remaining minutes,
And transmitting a detection signal obtained by detecting the first half of the frame synchronization word W1 by the first comparator when the counting of the remaining one superframe by the fourth counter is completed, as a superframe synchronization signal. Super frame synchronization signal generation circuit.

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