JP3565449B2 - Data phase change circuit - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a data phase change circuit that converts input data based on a first clock into data synchronized with a second clock.
[0002]
[Prior art]
For example, in an IC composed of CMOS, in order to keep the power consumption of the IC constant, there is a case where the circuit operates almost at the first clock and operates at the other second clock inside the IC. Is operated by the second clock only in the minimum necessary circuit. For this reason, for example, as shown in FIG. 3A, the IC 11 composed of CMOS operates mainly with the first clock WCL. In the IC 11, for example, the circuit 12 needs to operate with the second clock RCL. The data may be output to the outside of the IC 11 as data synchronized with the second clock. In this case, the circuit 12 that operates with the second clock RCL is configured in the IC 11 with a minimum necessary, that is, as small as possible. When outputting to the outside, the data that operates with the second clock RCL is first output at the output stage of the IC 11. And the IC 11 is operated by the first clock as much as possible. Therefore, the data input to the circuit 12 or the data output to the outside is changed from the data based on the first clock to the data synchronized with the second clock by the phase change circuit 13 in the IC 11 and supplied to the circuit 12. Or output to the outside. In this way, the IC 11 operates almost entirely with the first clock, and thus the heat generation of the IC 11 is substantially equal to the number of the first clocks per unit time, and the heat generation of the IC 11 is substantially constant. Therefore, the data propagation delay amount in the IC 11 can be kept substantially constant.
[0003]
Incidentally, the conventional phase changing circuit 13 is configured as shown in FIG. A quaternary counter 15 is provided. The quaternary counter 15 counts the first clock WCL from a terminal 16. This counting is performed only when a cycle signal from a terminal 17 is input. During this period, the previous counting state is maintained. In other words, the quaternary counter 15 includes flip-flops 18 and 19 and selectors 21 and 22. The selectors 21 and 22 select the inverted output of the flip-flop 18 while the cycle signal from the terminal 17 is being input, and output the data. The data is supplied to the input terminal, and the exclusive OR of the outputs of the flip-flops 18 and 19 is selected and supplied to the data input terminal of the flip-flop 19. When there is no cycle signal, the selectors 21 and 22 select the outputs of the flip-flops 18 and 19, respectively, and supply them to the data input terminals of the flip-flops 18 and 19 to hold the count state. That is, the flip-flops 18 and 19 form a quaternary counter and perform the counting operation only when there is a cycle signal, but maintain the current counting state when there is no cycle signal.
[0004]
The counting state of the quaternary counter 15 is decoded by the decoder 23, and the selection of the selectors 24 to 27 is controlled by the four decoded outputs. The input data is supplied from one terminal to one input of the selectors 24 to 27, the respective outputs of the registers 31 to 34 are input to the other input, and the respective outputs of the selectors 24 to 27 are respectively connected to the registers 31 to 34. Supplied to the data input, the registers 31 to 34 are configured to take in the output of the selector by the first clock WCL of the terminal 16.
[0005]
On the other hand, the second clock RCL from the terminal 35 is counted by the quaternary counter 36, the count value of the quaternary counter 36 is decoded by the decoder 37, and the four decoded outputs and the respective outputs of the registers 31 to 34 are respectively output. The outputs of the gates 41 to 44 are combined by an OR gate 46, re-timed by a second clock RCL in a flip-flop 47, and supplied to the circuit 12 (FIG. 3A).
[0006]
FIG. 3B shows an operation example of the conventional circuit shown in FIG. As input data from the input terminal 28, data D _n , D _{n + 1} , D _{n + 2} , D _{n + 3} ,... And data for each cycle are input as shown in FIG. 3A, and each cycle data (b in FIG. 3B) is input. ) Is an integral multiple of the first clock WCL. That is, the first clock WCL is be as shown in c of FIG. 3B, the data _{D n} is 1 cycle length of the first clock _{WCL, D n + 1} is 3 cycle length of the first clock _{WCL, D n + 2} is the One clock WCL has a two-cycle length, and the input data D _n , D _{n + 1} ,... Are synchronized with the first clock WCL. As shown in FIG. 3B, the cycle signal outputs one cycle of the first clock WCL for each change in synchronization with the input data (a in FIG. 3B). Thus the period cycle signal since the data D _n is 1 cycle length goes high, D n _{+ 1} cycle signal by a first clock period length of the first because it is 3 cycle length in the high level, two cycles after the Low level. Hereinafter, the same signal is output.
[0007]
The first clock WCL is a clock synchronized with the leading edge of the input data as described above, and the quaternary counter 15 performs the counting operation only when the first clock WCL matches the cycle signal, The counting operation is performed at the fall of one clock. That count value as shown in d of FIG. 3D is counted from 1 to 0 in the data D _n, the count value when the data D _{n + 1} is is 2, it is not performed for the next counting operation for the two first clock Holds the count value. This count value is decoded by the decoder 23 and supplied to the selectors 24 to 27 as a selection signal. When the quaternary counter 15 has the count value 0, the selector 24 takes in the input data, the selector value 35 takes in the input data when the count value is 1, and the selectors 26 and 27 take in the input data when the count values are 3 and 4, respectively. When the selectors 24 to 27 are ready to take in input data in accordance with the outputs of the decoder 23, the outputs of the registers 31 to 34 can be taken in.
[0008]
Thus in count value 0 of the counter 15, the input D _n data is captured at the rising edge of the first clock to the register 31, the count value is next data D _{n + 1} at the first falling edge of the clock immediately after one of the conditions Is input to the register 32, and similarly, the count values are 2 and 3, and the input data D _{n + 2} and D _{n + 3} are written into the registers 33 and 34 at the falling edge of the first clock immediately after that, respectively. The output states of the registers 31 to 34 are shown by e, f, g, and h in FIG. 3B. For example, the second clock RCL is generated as shown in FIG. 3B, and the second clock RCL is counted by the quaternary counter 36 and decoded by the decoder 37. Accordingly, the four outputs of the decoder 37 change as indicated by j, k, l, and m in FIG. 3B when the quaternary counter 36 has the count values 0, 1, 2, 3, and. When the decoder output is at the high level, the four outputs and the outputs of the registers 31 to 34 corresponding to the four outputs are taken out from the gates 41 to 44, respectively. That is, the quaternary counter 36 takes out the output of the register 31 in the state of the count value 0, takes out the output of the register 32 in the state of the count value 1, and outputs the outputs of the registers 33 and 34 in the state of the count values 2 and 3, respectively. The outputs of the registers 31 to 34 extracted by the gates 41 to 44 are combined by an OR circuit 36, and re-timed by a second clock by a flip-flop 47, and the output synchronized with the second clock is output. 3B is obtained as shown in n.
[0009]
In the above description, the radix of the quaternary counters 15 and 36 determines the largest value of the phase shift of the second clock RCL with respect to the first clock WCL by the period of the first clock as understood from the operation of the phase change circuit. What is necessary is just to make it a value larger than the value when expressing by the number of cycles. In the example shown in FIG. 3B, the quaternary counter is used because the second clock is within four cycles of the first clock even when the second clock has the largest deviation from the first clock. If the shift is N cycles, an N-ary counter is used as each of the counters 15 and 36. N counters corresponding to the registers 31 to 34 are provided, and N counters corresponding to the gates 41 to 44 are provided. Of course, although the number may be larger than the N number, the bases of the counters 15 and 36 have the same value.
[0010]
[Problems to be solved by the invention]
In the conventional phase change circuit, when the cycle length of the input data is long, or when the cycle is longer than the first clock WCL, the data is taken into one of the registers 31 to 34 at the beginning of the data. Thereafter, until the next data is input, the data of the registers 31 to 34 is fetched again via the selectors 24 to 27 and held. Therefore, the registers 31 to 34 always perform the fetching operation in each cycle of the first clock, and thus the registers 31 to 34 are rewritten in each cycle of the first clock, so that the power consumption increases accordingly. . That is, even when it is not necessary to rewrite the data in the registers 31 to 34, the data is rewritten and held, and there is a drawback that the power consumption is large.
[0011]
[Means for Solving the Problems]
In the present invention, the configuration is substantially the same as that of the prior art, except that the decode output of the N-ary counter for counting the first clock passes through the gate of the first clock, and the output of the N gates converts the input data into N data. Take in each register.
Therefore, in the case of a long data length, only writing is performed for one register selected by the decoder during the data length, and writing for holding is not performed for the other registers.
[0012]
【Example】
FIG. 1 shows an embodiment of the present invention by assigning the same reference numerals to parts corresponding to FIG. The input data from the input terminal 28 is supplied to each data terminal of the registers 31 to 34 with the timing delayed by one clock by the first clock WCL by the flip-flop 51. On the other hand, the four decode outputs of the decoder 23 are supplied to gates 52, 53, 54, and 55, respectively. The first clock WCL from the terminal 16 is supplied to the gates 52 to 55, and the flip-flop 31 is output by the outputs of the gates 52 to 55. The data is taken in to the data. The output whose count value is 0 among the decode outputs of the decoder 23 is supplied to the gate 55, and the outputs of the count values 1, 2, and 3 are supplied to the gates 52 to 54, respectively. Other configurations are the same as those in FIG.
[0013]
FIG. 2 shows an example of the operation of FIG. 1 in a case similar to the input data, the first clock, and the second clock shown in FIG. In this embodiment, the input data a is delayed by one cycle of the first clock by the flip-flop 51 and supplied to the registers 31 to 34 as shown in FIG. 2B. The cycle signal for the input data is a signal as shown in FIG. 2C, the first clock WCL is a signal as shown in FIG. 2D, and the count value of the quaternary counter 15 changes as shown in FIG. 2E. When the count value is 0, the capture clock for the register 34 is given as shown in FIG. 2f. Similarly, when the count value is 1, 2, and 3, the capture clock for the registers 31, 32, and 33 is respectively shown in FIG. It is supplied as shown in h and i. Thus _{D n} of the input data count value of the counter 15 is taken as shown in Figure 2i at 1, this time drawing 2 g, h, uptake clock to the register 32, 33, 34 as shown in i is given Absent. In the next first clock, the count value becomes 2, and in the first first clock, the data Dn _{+ 1} is taken into the register 32 by the first clock passed through the gate 53 as shown in FIG. , 33, 34 are not input as shown in FIGS. 2f, h, i. In the next first clock, the register 32 is fetched, but the other registers are not fetched.
[0014]
In the same manner, input data is fetched into only one of the registers 31 to 34 corresponding to the count value of the counter 15, and the other registers are not fetched. Therefore, in the prior art, all the registers were fetched at every first clock, that is, data for fetching or holding input data was performed. However, in the present invention, the register selected by the decoder is Data is fetched only for the other registers, and no fetch operation is performed for the other registers. Therefore, the power consumption is small. The data taken in the registers 31 to 34 is extracted by counting the second clock RCL by the quaternary counter 36, and outputting the outputs of the registers 31 to 34 from the gates 41 to 44 by the decode output obtained by decoding the count value by the decoder 37. Performing by taking in is the same as in the prior art of FIG.
[0015]
As described in the section of the related art, the base N of the counters 15 and 36 and the number of the registers 31 to 34 are determined according to the shift of the second clock from the first clock.
[0016]
【The invention's effect】
As described above, according to the present invention, only the data is fetched into one register corresponding to the count value of the counter for counting the first clock, and the fetch and hold operation is not performed on the other registers. , Power consumption is reduced accordingly. That is, the power consumption of the registers 31 to 34 becomes 1 / N.
[Brief description of the drawings]
FIG. 1 is a logic circuit diagram showing an embodiment of the present invention.
FIG. 2 is a diagram showing waveforms of respective units in an operation example in the embodiment of FIG. 1;
3A is a diagram showing an example to which a data phase changing circuit is applied, and FIG. 3B is a diagram showing waveforms of various parts in the operation of the conventional circuit in FIG.
FIG. 4 is a logic circuit diagram showing a conventional data phase change circuit.

Claims (1)

A first clock, input data based on the first clock, a cycle signal indicating each cycle point of the input data, and a second clock are input, and the input data is converted into data synchronized with the second clock. In the data phase change circuit that outputs
A first N-ary counter (N is an integer of 2 or more) that inputs the first clock and the cycle signal and counts the first clock when the cycle signal is present;
A first decoder for decoding the count value of the first N-ary counter;
N first gates to which N outputs of the first decoder and the first clock are respectively supplied;
N registers from which the input data are sequentially taken in by the outputs of the N first gates,
A second N-ary counter for counting the second clock,
A second decoder for decoding the count value of the second N-ary counter;
N second gates for respectively extracting the corresponding outputs of the N registers from the N outputs of the second decoder;
An OR circuit for combining the outputs of the N second gates to obtain the converted data.

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