JP3565719B2 - Bus connection circuit and computer system - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a bus connection circuit and a computer system, and can be applied to, for example, a computer system in which a primary side and a secondary side of a PCI-PCI bus bridge are dynamically switched.
[0002]
[Prior art]
In recent years, the amount of data processed by a computer system has increased remarkably due to multimedia, a GUI (Graphical User Interface), and the like, and a high-speed internal bus for transferring data between devices in the system has been required.
[0003]
Against this background, the PCI (Peripheral Component Interconnect) bus is an internal bus that has been standardized mainly by Intel Corporation in the United States.
[0004]
This PCI bus is not based on a specific CPU (Central Processing Unit) or architecture. Therefore, each device connected to the PCI bus has a configuration indicating the type and operation status of the device. It is stipulated that a register be provided.
[0005]
Further, up to 32 devices can be connected to the PCI bus in terms of setting. However, in practice, the limit is about 10 devices from the viewpoint of electrical load and stability. Therefore, in order to connect more devices, a plurality of PCI buses are prepared in the system, and each PCI bus is connected by a PCI-PCI bus bridge.
[0006]
FIG. 2 is a block diagram showing a configuration of a conventional PCI-PCI bus bridge. Hereinafter, the PCI-PCI bus bridge will be briefly described. In FIG. 2, the side closer to the host CPU is the primary PCI bus, and the side farther from the host CPU is the secondary PCI bus.
[0007]
At the time of system initialization such as power-on or reset, the host CPU searches each PCI bus and assigns a bus number to identify a plurality of PCI buses in the system. The assigned bus number is set by the host CPU in a configuration register of a host bridge connected to each PCI bus or a PCI-PCI bus bridge, and is used for identification of data transfer between devices thereafter. .
[0008]
Here, as shown in FIG. 2, the configuration register 15 of the PCI-PCI bridge includes a primary bus number register (PriBN) 151, a secondary bus number register (SecBN) 152, and a subordinate bus number register. (SubBN) 153, and an appropriate bus number is set in each register. It should be noted that the subordinate bus is a PCI bus that is located ahead of the secondary-side PCI bus via a PCI-PCI bus bridge, and a plurality of subordinate buses may exist. If there is no subordinate bus, the secondary bus number is set in the subordinate bus number register 153.
[0009]
[Problems to be solved by the invention]
However, the above-described conventional PCI-PCI bus bridge presupposes a system in which the primary bus and the secondary bus are fixed, so that the primary PCI bus and the secondary PCI bus operate. There is a problem that it cannot be applied to a system in which the switching is performed.
[0010]
For example, as will be described later, in a redundant system in which system switching is performed between two host CPUs of an active system and a standby system, a PCI-PCI bus bridge connecting PCI buses controlled by different host CPUs has a primary side. And the secondary side is dynamically switched, so it cannot be applied.
[0011]
Therefore, a bus connection circuit and a computer system that can dynamically switch between the primary side and the secondary side have been demanded.
[0012]
[Means for Solving the Problems]
In order to solve such a problem, the present invention includes a register in which control information for connecting an element on a first bus and an element on a second bus is set, and the control set in the register. In the inter-bus connection circuit for exchanging the information body between the first bus and the second bus via the built-in primary and secondary side dedicated interfaces based on the information, Based on the primary-side instruction command, the primary-side first or second bus is connected to the built-in primary-side dedicated interface, and the secondary-side second or first bus is built-in. Switching means for switching the connection relationship so that the connection is made to the dedicated interface Equipped (2) control information corresponding to the newly switched primary side first or second bus And control information corresponding to the second or first bus on the secondary side And reset the register Suko And features.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
(A) First embodiment
Hereinafter, a first embodiment in which a bus connection circuit according to the present invention is applied to a PCI-PCI bus bridge in which a primary side and a secondary side are dynamically switched will be described in detail with reference to the drawings.
[0014]
(A-1) Description of Configuration
FIG. 1 is a block diagram illustrating the configuration of the computer system according to the first embodiment. In FIG. 1, this computer system has an A-side PCI bus 1, a B-side PCI bus 2, and a PCI-PCI bus bridge 3, and a connection between the A-side PCI bus 1 and the PCI-PCI bus bridge 3. , A data signal line 11 and a control signal line 21, and a data signal line 12 and a control signal line 22 are connected between the B-side PCI bus 2 and the PCI-PCI bus bridge 3. The PCI-PCI bus bridge 3 and a system control unit (not shown) are connected by a primary instruction signal line 131.
[0015]
Further, the PCI-PCI bus bridge 3 includes data signal drivers / receivers 13, 14, 111 and 112, a primary bus number register (PriBN) 151, a secondary bus number register (SecBN) 152, and a subordinate bus. A configuration register group 15 having a number register (SubBN) 153, a buffer unit 16, control signal drivers / receivers 23, 24, 121 and 122, a primary side target interface 25, and a secondary side master interface 26; , A primary master interface 27, a secondary target interface 28, and a logical inversion element 134.
[0016]
The A-side PCI bus 1 and the B-side PCI bus 2 are two buses connected to the PCI-PCI bus bridge 3, each of which is closer (primary side) and farther (secondary side) to the host CPU. ). Here, the A-side PCI bus 1 is composed of a data signal (address / data bus, C / BE signal, etc.) and a control signal (FRAME signal, IRDY signal, etc.). The signal is transmitted / received to / from the PCI-PCI bus bridge 3 via the signal line 11 and the control signal line 21. The B-side PCI bus 2 is the same as the A-side PCI bus 1, and the data signal and the control signal of the B-side PCI bus 2 are transmitted by the data signal line 12 and the control signal line 22 to the PCI-PCI bus bridge 3. Will be given and received.
[0017]
The data signal drivers / receivers 13 and 111 are connected to the data signal line 11 and receive (drive) or drive (transmit) a data signal to the data signal line 11. On the other hand, the data signal drivers / receivers 14 and 112 are respectively connected to the data signal line 12 and receive (receive) or drive (transmit) a data signal to the data signal line 12.
[0018]
Here, as described later, when an active signal is given from the primary-side instruction signal line 131 by a system control unit (not shown), a signal indicating that the A-side PCI bus is the primary side (A = Pri signal). Is active and the signal indicating that the B-side PCI bus is the primary side (B = Pri signal) becomes inactive, so that the data signal drivers / receivers 13 and 14 operate and the data signal drivers / receivers 111 and 112 Stops working. On the other hand, when an inactive signal is given from the primary side instruction signal line 131, the A = Pri signal becomes inactive and the B = Pri signal becomes active, so that the data signal drivers / receivers 13 and 14 stop operating, and the data The signal drivers / receivers 111 and 112 operate.
[0019]
The configuration register group 15 has a plurality of registers in which the characteristics, types, operation methods, and the like of the PCI-PCI bus bridge 3 for the A-side PCI bus 1 and the B-side PCI bus 2 are set. In this embodiment, as shown in FIG. 1, the configuration register group 15 includes a primary bus number register (PriBN) 151 in which the bus number of the primary PCI bus is set, and a bus of the secondary PCI bus. The secondary bus number register (SecBN) 152 in which the number is set, and the subordinate bus in which the bus number of the subordinate bus (or the secondary bus number when there is no subordinate bus) are set. And a number register (SubBN) 153.
[0020]
The buffer unit 16 temporarily stores the data signals received by the data signal drivers / receivers 13 and 111 or 14 and 112, and based on an instruction from the primary master interface 27 or the secondary master interface 26, The stored data signal is supplied to the data signal drivers / receivers 14 and 111 or 13 and 112.
[0021]
The control signal drivers / receivers 23 and 121 are connected to the control signal line 21 and receive (receive) or drive (transmit) a control signal to the control signal line 21. On the other hand, the control signal drivers / receivers 24 and 122 are respectively connected to the control signal line 22 and receive (drive) or drive (transmit) a control signal to the control signal line 22.
[0022]
Here, as described later, when an active signal is given from the primary-side instruction signal line 131 by a system control unit (not shown), the A = Pri signal becomes active and the B = Pri signal becomes inactive. The drivers / receivers 23 and 24 operate, and the control signal drivers / receivers 121 and 122 stop operating. On the other hand, when an inactive signal is given from the primary side instruction signal line 131, the A = Pri signal becomes inactive and the B = Pri signal becomes active, so that the control signal drivers / receivers 23 and 24 stop operating, and The signal drivers / receivers 121 and 122 operate.
[0023]
In general, when data is transferred on a computer bus, there is a "master" and "slave" relationship between a data sender and a data receiver. Here, in the PCI bus, "initiator" may be used as a word corresponding to "master" and "target" may be used as a word corresponding to "slave". Hereinafter, the same meaning is used in this embodiment. It will be described using FIG.
[0024]
The primary-side target interface 25 receives an access request from the master device from the control signal line 21 or 22 of the primary A-side PCI bus 1 or the B-side PCI bus 2, and receives the data signal line 11 in response to the access request. Alternatively, based on the address given from 12, a destination is searched by referring to the configuration register group 15, and the search result is given to the secondary master interface 26. The primary side target interface 25 receives a configuration setting request from the host CPU connected to the primary side, and transmits the setting data given from the data signal line 11 or 12 by the setting request to the configuration register group 15. Is set to
[0025]
The secondary master interface 26 outputs a control signal based on a search result from the primary target interface 25 to the control signal line 21 or 22 of the secondary A-side PCI bus 1 or the B-side PCI bus 2 and The transmission destination address based on the search result from the primary side target interface 25 and the transmission data stored in the buffer unit 16 are transferred to the data signal line 11 of the secondary A-side PCI bus 1 or the B-side PCI bus 2 or 12 is output.
[0026]
The secondary-side target interface 28 receives an access request from the master device from the control signal line 21 or 22 of the secondary A-side PCI bus 1 or the B-side PCI bus 2, and receives the data signal line 11 in response to the access request. Alternatively, based on the address given from 12, the destination is searched for by referring to the configuration register group 15, and the search result is given to the primary master interface 27.
[0027]
The primary master interface 27 outputs a control signal based on the search result from the secondary target interface 28 to the control signal line 21 or 22 of the primary A-side PCI bus 1 or B-side PCI bus 2 and The transmission destination address based on the search result from the secondary target interface 28 and the transmission data stored in the buffer unit 16 are transferred to the data signal line 11 of the primary A-side PCI bus 1 or the B-side PCI bus 2 or 12 is output.
[0028]
The logic inversion element 134 is for inverting the logic of the applied signal. In this embodiment, when an active signal or an inactive signal is applied from the primary-side instruction signal line 131, the inactive signal or It inverts the logic of the active signal and outputs it.
[0029]
(A-2) Description of operation
Next, the operation of the computer system having such a configuration will be described with reference to FIGS.
[0030]
When an active signal is given from the primary instruction signal line 131, the A = Pri signal becomes active and the B = Pri signal becomes inactive, so that the data signal drivers / receivers 13 and 14 and the control signal drivers / receivers 23 and 24 are provided. Operate and the paths through them become valid, while the data signal drivers / receivers 111 and 112 and the control signal drivers / receivers 121 and 122 stop operating, and the paths through them become invalid. Here, FIG. 3 is a block diagram showing an operation state in this case, and a valid path portion is indicated by a thick line. Therefore, as in the conventional example shown in FIG. 2, the A-side PCI bus 1 is on the primary side and the B-side PCI bus 2 is on the secondary side.
[0031]
When an inactive signal is supplied from the primary instruction signal line 131, the A = Pri signal becomes inactive and the B = Pri signal becomes active, so that the data signal drivers / receivers 111 and 112 and the control signal driver / receiver 121 and 122 operate and the paths through them become valid, while the data signal drivers / receivers 13 and 14 and the control signal drivers / receivers 23 and 24 cease operation and the bus through them becomes invalid. FIG. 4 is a block diagram showing an operation state in this case, in which a valid path portion is indicated by a thick line. Therefore, contrary to the conventional example shown in FIG. 2, the A-side PCI bus 1 is on the secondary side and the B-side PCI bus 2 is on the primary side.
[0032]
On the other hand, after switching between the primary side bus and the secondary side bus, the bus number of each PCI bus for the PCI-PCI bus bridge 3 changes, so the bus number set in the configuration register group 15 is changed and the bus number is changed again. Must be set. Here, FIG. 5 is an explanatory diagram for explaining this resetting operation. FIG. 5A shows a computer system in which the A-side PCI bus before switching is the primary side, and FIG. 5B shows a computer system in which the B-side PCI bus after switching is the primary side. . As shown in FIG. 5, in the computer system before switching, the bus number 1 is set in PriBN, the bus number 3 is set in SecBN, and the bus number 4 is set in SubBN, but in the system after switching, The bus number 3 must be reset for PriBN, the bus number 1 for SecBN, and the bus number 2 for SubBN.
[0033]
Here, the detailed operation of setting (re-setting) the configuration register group 15 and the case of transferring data from the primary PCI bus to the target device connected to the secondary PCI bus will be described.
[0034]
1. When setting (re-setting) the configuration register group 15
First, the primary target interface 25 recognizes a configuration setting request from the host CPU output to the control signal line 21 or 22 of the primary PCI bus.
[0035]
Next, in the primary-side target interface 25, the configuration is performed based on the setting data (the address of the register to be set and the bus number to be set) from the host CPU output to the data signal line 11 or 12 of the primary-side PCI bus. The bus number is written to the target register of the register group 15.
[0036]
2. When transferring data from the primary PCI bus to a target device connected to the secondary PCI bus
First, the access request from the master device output to the control signal line 21 or 22 of the primary PCI bus is recognized by the primary target interface 25 and the data signal line 11 of the primary PCI bus is recognized. Alternatively, the transmission data from the master device output to 12 is written to the buffer unit 16.
[0037]
Next, in the primary target interface 25, a transmission destination is searched by referring to the configuration register group 15 based on the address from the master device output to the data signal line 11 or 12 of the primary PCI bus, This search result is provided to the secondary master interface 26.
[0038]
Further, in the secondary master interface 26, a control signal based on the search result is output to the control signal line 21 or 22 of the secondary PCI bus, and a transmission destination address based on the search result and the buffer unit 16 are sent to the secondary master interface 26. The stored transmission data is output to the data signal line 11 or 12 of the secondary PCI bus, and the data is transferred to the target device.
[0039]
When data is transferred from the secondary PCI bus to the target device connected to the primary PCI bus, the same operation is performed, although the description is omitted.
[0040]
For example, as shown in FIG. 6, such a PCI-PCI bus bridge connects PCI buses controlled by different host CPUs in a redundant system in which two host CPUs are switched between an active system and a standby system. This is suitable for application to a PCI-PCI bus bridge. Here, FIG. 6A shows a computer system in which the host CPU connected to the A-side PCI bus is operating and the A-side PCI bus is the primary side, and FIG. 6B shows the B-side PCI bus. This figure shows a computer system in which the host CPU connected to the bus is in operation and the b-side PCI bus is the primary side.
[0041]
(A-3) Description of effects
As described above, according to the first embodiment, (1) the primary side of the two PCI buses connected to the PCI-PCI bus bridge 3 based on the signal from the primary side instruction signal line It has data signal drivers / receivers 13, 14, 111, 112 for switching the secondary side, and control signal drivers / receivers 23, 24, 121, 122. (2) The host CPU performs the configuration based on this switching. Since the registers of the register group 15 are reset so as to be applied to the bus configuration after switching, the primary side and the secondary side of the PCI-PCI bus bridge 3 are set based on the signal from the primary side instruction signal line. Can be switched dynamically.
[0042]
(B) Second embodiment
Hereinafter, a second embodiment in which a bus connection circuit according to the present invention is applied to a PCI-PCI bus bridge in which a primary side and a secondary side are dynamically switched will be described in detail with reference to the drawings.
[0043]
(B-1) Description of Configuration
FIG. 7 is a block diagram illustrating a configuration of a computer system according to the second embodiment. In FIG. 7, this computer system has an A-side PCI bus 1, a B-side PCI bus 2, and a PCI-PCI bus bridge 3, and a connection between the A-side PCI bus 1 and the PCI-PCI bus bridge 3. , A data signal line 11 and a control signal line 21, and a data signal line 12 and a control signal line 22 are connected between the B-side PCI bus 2 and the PCI-PCI bus bridge 3. The PCI-PCI bus bridge 3 and a system control unit (not shown) are connected by a primary instruction signal line 131.
[0044]
Further, the PCI-PCI bus bridge 3 includes data signal drivers / receivers 13, 14, 111 and 112, an A-side PCI bus primary side bus number register (PriBN-A) 154, and an A-side PCI bus secondary side. Bus number register (SecBN-A) 155, A-side PCI bus subordinate bus number register (SubBN-A) 156, B-side PCI bus primary side bus number register (PriBN-B) 157, and B-side PCI bus Register group 15 having a secondary bus number register (SecBN-B) 158 and a subordinate bus number register (SubBN-B) 159 for a B-side PCI bus, a buffer unit 16, a control signal driver / Receivers 23, 24, 121 and 122 and primary side target interface 25 Has a secondary master interface 26, the primary side master interface 27, a secondary-side target interface 28, and a logic inversion element 134.
[0045]
In FIG. 7, components corresponding to those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals. Therefore, the description of the components will be omitted, and the detailed configuration of the configuration register group 15 will be described below.
[0046]
The configuration register group 15 includes an A-side PCI bus primary-side bus number register (PriBN-A) 154 for setting the bus number of the primary-side PCI bus when the A-side PCI bus 1 is the primary side. , An A-side PCI bus secondary bus number register (SecBN-A) 155 in which the bus number of the secondary-side PCI bus is set when the A-side PCI bus 1 is the primary side; Is the primary side, the subordinate bus number register (SubBN-) for the A-side PCI bus in which the bus number of the subordinate bus (the secondary bus number when there is no subordinate bus) is set. A) 156 and a primary bus number register (PriBN-B) for the B-side PCI bus in which the bus number of the primary-side PCI bus when the B-side PCI bus 2 is the primary side is set. 157, a B-side PCI bus secondary bus number register (SecBN-B) 158 for setting the bus number of the secondary-side PCI bus when the B-side PCI bus 1 is the primary side, and a B-side PCI A subordinate bus number register for the B side PCI bus in which the bus number of the subordinate bus when the bus 1 is the primary side (or the secondary bus number when there is no subordinate bus) is set. SubBN-B) 159. Note that the configuration register group 15 is provided with an A = Pri signal and a B = Pri signal.
[0047]
Here, as described later, when an active signal is given from the primary-side instruction signal line 131 by a system control unit (not shown), the A = Pri signal becomes active, the B = Pri signal becomes inactive, and the A-side PCI becomes inactive. PriBN-A154, SecBN-A155, and SubBN-A156 when the bus is the primary side are valid, and PriBN-B157, SecBN-B158, and SubBN-B159 when the B-side PCI bus is the primary side. Becomes invalid. On the other hand, when an inactive signal is given from the primary-side instruction signal line 131, the A = Pri signal becomes inactive, the B = Pri signal becomes active, and the PriBN-A154 when the A-side PCI bus is the primary side. , SecBN-A155, and SubBN-A156 become invalid, and PriBN-B157, SecBN-B158, and SubBN-B159 when the B-side PCI bus is the primary side become valid.
[0048]
(B-2) Description of operation
Next, the operation of the computer system having such a configuration will be described with reference to FIGS.
[0049]
When an active signal is given from the primary instruction signal line 131, the A = Pri signal becomes active and the B = Pri signal becomes inactive, so that the data signal drivers / receivers 13 and 14 and the control signal drivers / receivers 23 and 24 are provided. Operate and the paths through them become valid, while the data signal drivers / receivers 111 and 112 and the control signal drivers / receivers 121 and 122 stop operating, and the paths through them become invalid. Here, FIG. 8 is a block diagram showing an operation state in this case, and a valid path portion is indicated by a thick line. Therefore, as in the conventional example shown in FIG. 2, the A-side PCI bus 1 is on the primary side and the B-side PCI bus 2 is on the secondary side.
[0050]
When an inactive signal is supplied from the primary instruction signal line 131, the A = Pri signal becomes inactive and the B = Pri signal becomes active, so that the data signal drivers / receivers 111 and 112 and the control signal driver / receiver 121 and 122 operate and the paths through them become valid, while the data signal drivers / receivers 13 and 14 and the control signal drivers / receivers 23 and 24 are deactivated and the paths through them become invalid. FIG. 9 is a block diagram showing an operation state in this case, and a portion of an effective path is indicated by a thick line. Therefore, contrary to the conventional example shown in FIG. 2, the A-side PCI bus 1 is on the secondary side and the B-side PCI bus 2 is on the primary side.
[0051]
FIG. 10 is an explanatory diagram for explaining an operation of switching the configuration register group 15. FIG. 10A shows the computer system before the switching, and FIG. 10B shows the computer system after the switching.
[0052]
As shown in FIG. 10, in a computer system in which the A-side PCI bus before switching is the primary side, the A = Pri signal becomes active and the B = Pri signal becomes inactive, so that the A-side PCI bus becomes primary. PriBN-A 154, SecBN-A 155, and SubBN-A 156 when the primary side is enabled, and PriBN-B 157, SecBN-B 158, and SubBN-B 159 when the B side PCI bus is the primary side are disabled. . On the other hand, in a system in which the B-side PCI bus after switching is the primary side, the A = Pri signal becomes inactive and the B = Pri signal becomes active, so that the A-side PCI bus becomes the primary side. PriBN-A154, SecBN-A155, and SubBN-A156 become invalid, and PriBN-B157, SecBN-B158, and SubBN-B159 become effective when the B-side PCI bus is the primary side.
[0053]
The detailed operations of setting (resetting) the configuration register group 15 and transferring data from the primary PCI bus to the target device connected to the secondary PCI bus are described in the first. The description is omitted because it is the same as the embodiment.
[0054]
Further, the PCI-PCI bus bridge of the second embodiment can of course be applied to the redundant system for switching between the two host CPUs of the active system and the standby system shown in FIG.
[0055]
(B-3) Description of effects
As described above, according to the second embodiment, effects similar to those of the first embodiment can be obtained.
[0056]
Further, according to the second embodiment, the configuration register group 15 has a register in which bus numbers before and after switching are stored, and one of them is enabled based on the A = Pri signal and the B = Pri signal. Since the other is invalidated, there is no need to reset the configuration register group 15.
[0057]
(C) Other embodiments
In each of the above embodiments, the internal bus is a PCI bus. However, the present invention is not limited to the PCI bus, and any configuration register group that sets the same bus number in the inter-bus connection circuit may be used. The present invention can be similarly applied to the present invention.
[0058]
In each of the above embodiments, the bus number is set in the configuration register group. However, the present invention is not limited to the bus number, and other control information may be set. Applicable to the invention.
[0059]
Further, in the redundantly configured computer system for switching between the active system and the standby system shown in FIG. 6, the number of host CPUs is two, but the number of host CPUs may be three or more.
[0060]
【The invention's effect】
As described above, according to the present invention, there is provided the register in which the control information for connecting the element on the first bus and the element on the second bus is set, and the control set in the register is provided. An inter-bus connection circuit for exchanging an information body between a first bus and a second bus via a built-in primary-side and secondary-side dedicated interface based on information. , Giving Based on the obtained primary-side instruction command, the primary-side first or second bus is connected to the built-in primary-side dedicated interface, and the secondary-side second or first bus is built-in. Connection switching means that switches the connection relationship so that it is connected to the dedicated interface on the next side With new Control information corresponding to the primary or second bus that has just been switched And control information corresponding to the second or first bus on the secondary side And reset the register By doing , The primary and secondary buses of the first and second buses can be dynamically switched based on a primary side instruction command from the outside.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a computer system according to a first embodiment.
FIG. 2 is an explanatory diagram of a conventional PCI-PCI bus bridge.
FIG. 3 is an operation explanatory diagram in a case where an A = Pri signal is active and a B = Pri signal is inactive in the first embodiment;
FIG. 4 is a diagram illustrating an operation in the first embodiment when an A = Pri signal is inactive and a B = Pri signal is active;
FIG. 5 is an operation explanatory diagram of resetting of a configuration register group 15 in the first embodiment.
FIG. 6 is an explanatory diagram of an operation of a computer system that switches between two host CPUs of an active system and a standby system.
FIG. 7 is a block diagram illustrating a configuration of a computer system according to a second embodiment.
FIG. 8 is an operation explanatory diagram in a case where an A = Pri signal is active and a B = Pri signal is inactive in the second embodiment.
FIG. 9 is an operation explanatory diagram in a case where an A = Pri signal is inactive and a B = Pri signal is active in the second embodiment.
FIG. 10 is an explanatory diagram of an operation of resetting the configuration register group 15 in the second embodiment.
[Explanation of symbols]
13, 14, 111, 112: data signal driver / receiver, 23, 24, 121, 122: control signal driver / receiver, 131: primary instruction signal line.

Claims (4)

A register in which control information for connecting an element on the first bus to an element on the second bus is set, and the first bus and the second bus are set based on the control information set in the register. A bus connection circuit for exchanging information with the bus via a built-in primary and secondary side dedicated interface,
Based on a given primary-side instruction command, the primary-side first or second bus is connected to a primary-side dedicated interface, and the secondary-side second or first bus is built-in. Connection switching means for switching the connection relationship so as to be connected to the secondary-side dedicated interface,
In the above the switched primary first or control information corresponding to the second bus and control information corresponding to the secondary side to the second or first bus to a new, and score straight sets the register A bus connection circuit characterized by the above-mentioned. A register in which control information for connecting an element on the first bus to an element on the second bus is set, and the first bus and the second bus are set based on the control information set in the register. A bus connection circuit for exchanging information with the bus via a built-in primary and secondary side dedicated interface,
In the register, control information corresponding to the first or second bus on the primary side to be switched by the following connection switching means is also set in advance,
Based on a given primary-side instruction command, the primary-side first or second bus is connected to a primary-side dedicated interface, and the secondary-side second or first bus is built-in. Connection switching means for switching the connection relationship so as to be connected to the secondary-side dedicated interface,
The effective area of the register is changed to an area of control information corresponding to the newly switched primary-side first or second bus and an area of control information corresponding to the secondary-side second or first bus. An inter-bus connection circuit characterized in that: 3. The bus connection circuit according to claim 1, wherein the first and second buses are PCI buses. In a computer system having a plurality of CPUs of an active system and a standby system, and performing system switching from the active system to the standby system,
4. A computer system, wherein the inter-bus connection circuit according to claim 1 is applied to an inter-bus connection circuit that connects buses controlled by each CPU.

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