JP3566841B2 - Information processing equipment - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an information processing apparatus that includes a plurality of execution units that can operate simultaneously and that simultaneously decodes and executes a plurality of instructions, and in particular, supplies a plurality of instructions that are simultaneously decoded to an execution unit (hereinafter, referred to as “dispatch”). The present invention relates to an improvement in an instruction control method for controlling a command.
Information processing apparatuses that simultaneously decode and execute a plurality of instructions include a computer using a reduced in-structural set computer (RISC) system and a computer using a computer in a complex in-structural set computer (CISC) system.
The CISC system has a complicated instruction set so as to flexibly cope with compatibility and expansion of functions, and can flexibly incorporate hardware technology with rapid progress. On the other hand, the RISC method is based on the premise that a program is written in a high-level language and has been proposed as an architecture capable of executing the program efficiently. Its instruction set is limited to only the most frequently used instructions. Other functions realize high-speed processing by combining and executing the limited instructions. These differences indicate that the instruction processing cycles realized by the RISC system and the CISC system are different from each other.
[0002]
[Prior art]
FIG. 15 is an example of the configuration of an information processing apparatus provided with a RISC instruction set. In the RISC instruction set architecture, the operands of the execution units are usually registers, and memory accesses occur only for load / store instructions.
[0003]
Therefore, as shown in FIG. 15, for example, as shown in FIG. 15, a configuration for implementing the instruction set of the RISC system includes a plurality of instruction registers 200, an instruction storage unit 201, a control unit 202, and a plurality of execution units 203 that can operate simultaneously. As shown in FIG. 15, the control unit 202 performs a corresponding control operation in each of three cycles including a decoding cycle D1, a dispatch cycle D2, and an instruction execution cycle E.
[0004]
In the decoding cycle D1, a plurality of instructions fetched into the plurality of instruction registers 200 are simultaneously decoded. In the dispatch cycle D2, each decoded instruction is stored in the instruction storage means 201, and a plurality of decoded instructions are taken out from the instruction storage means 201 and dispatched to the plurality of execution units 203. In the instruction execution cycle E, instructions are simultaneously executed in a plurality of execution units.
[0005]
Next, FIG. 16 is a configuration example of an information processing apparatus including an instruction set of the CISC system. In a CISC instruction set architecture, the operands of an execution unit are usually registers and memory operands, and memory accesses occur frequently in general instructions. Obtaining a memory operand requires address calculation and memory access, and requires a larger number of clocks than obtaining a register operand.
[0006]
Therefore, as shown in FIG. 16, for example, a configuration for implementing the instruction set of the CISC system includes a plurality of instruction registers 300, an instruction storage unit 301, two control units 302 and 303, and an execution unit 304 having different characteristics. , 305. Incidentally, the execution unit 304 includes an address adder and a cache memory, and the execution unit 305 includes an arithmetic unit.
[0007]
As shown in FIG. 16, the instruction processing cycle includes a decoding cycle D1, a dispatch cycle D2, and two instruction execution cycles E1 and E2, and the control units 302 and 303 simultaneously execute the decoding cycle D1 and the dispatch cycle D2. In the instruction execution cycles E1 and E2, different operations are performed.
[0008]
That is, in the instruction execution cycle E1, the control unit 303 controls the execution unit 304. Specifically, the control unit 303 gives the source register operand to the address adder to execute the address calculation, and accesses the cache memory based on the result, and extracts the memory operand. Then, in the subsequent instruction execution cycle E2, the control unit 302 controls the execution unit 305. Specifically, the control unit 302 gives the execution unit 305 a source operand (register operand) and causes the execution unit 305 to execute an operation between the source operand (register operand) and the fetch data (memory operand) of the execution unit 304.
[0009]
[Problems to be solved by the invention]
The instruction set of the CISC system is useful because it is rich in extensibility. However, as described above, the instruction processing cycle in the CISC system is one cycle longer than the instruction processing cycle in the RISC system, so that the speed is increased. Will be lacking.
SUMMARY OF THE INVENTION It is an object of the present invention to provide an information processing apparatus that executes instruction processing at a high speed by simultaneously decoding and executing a plurality of instructions. An object of the present invention is to provide an instruction control method which can have the same number of cycles as the number of instruction processing cycles in the method.
[0010]
[Means for Solving the Problems]
FIG. 1 is a block diagram showing the principle of the first aspect of the present invention.
According to the first aspect of the present invention, in an information processing apparatus including a plurality of execution units 1 operable at the same time, a configuration for controlling the transmission of a plurality of instructions 2 decoded simultaneously to a plurality of execution units 1 is provided. A required instruction detecting means 3 for detecting an instruction requiring the execution unit 1 from a plurality of instructions 2 being decoded, an instruction storing means 4 for temporarily storing decoded instructions, and a valid instruction in the instruction storing means 4 The valid instruction detecting means 5 to be detected and the number of valid instructions detected by the valid instruction detecting means 5 are empty. Fruit Depending on the size relationship of the number of line units, Required instruction detection means detected Requires an execution unit Decoding Feed control for feeding a part of the instruction to the empty execution unit 1 and feeding the instruction during decoding, which could not be sent because the execution unit 1 was not assigned, to the instruction storage means 4 for storage. Means 6.
[0011]
That is, in the invention according to the first aspect, in the decoding cycle, the necessary instruction detecting means 3 detects an instruction requiring the execution unit 1 from among the plurality of instructions 2 being simultaneously decoded, and detects a valid instruction. Means 5 detects a valid instruction among the decoded instructions stored in the instruction storage means 4 in the previous instruction processing cycle.
And the feed control means 6 Vacant The magnitude relation between the number of necessary execution units and the number of valid instructions detected by the valid instruction detecting means 5 is determined, Vacant When there are more effective instructions than the number of execution units, 1 If not, all of the instructions being decoded are sent to the instruction storage means 4 for storage. You. one Who Than the number of free required execution units 1 When there are few valid instructions, that is, the execution unit 1 If there is a free space, a part of the decoding instruction is sent to the empty execution unit 1, and the decoding instruction that could not be sent because the execution unit 1 was not allocated is sent to the instruction storage means 4. And store it.
[0012]
Thus, the instruction during decoding can be fed to the execution unit in parallel in the same cycle (dispatch cycle) for feeding the instruction storing means, so that high-speed processing can be performed even for a complicated instruction set.
FIG. 2 is a block diagram showing the principle of the second aspect of the present invention.
According to a second aspect of the present invention, in an information processing apparatus including a plurality of execution units 1 that can operate simultaneously, a configuration for controlling the transmission of a plurality of instructions 2 decoded simultaneously to a plurality of execution units 1 is provided. A required instruction detecting means 3 for detecting an instruction requiring the execution unit 1 from a plurality of instructions 2 being decoded, an instruction storing means 4 for temporarily storing decoded instructions, and a plurality of instructions 2 for decoding processing A processing status table 7 in which the processing status of each of these is set, and a referenceable instruction detecting means 8 for detecting an instruction whose operand can be referred to among a plurality of instructions being simultaneously decoded with reference to the processing status table 7 And among the decoding instructions requiring the execution unit 1 detected by the necessary instruction detection means 3, there are available instructions which can be referenced by the operands detected by the referenceable instruction detection means 8. Fed to line units 1, characterized in that it comprises a feed control means 9 is stored by feeding instructions which could not be fed to the execution unit 1 to the instruction storage unit 4 for the operands are not visible.
[0013]
That is, in the invention according to the second aspect, in the decoding cycle, the necessary instruction detecting means 3 detects an instruction requiring the execution unit 1 from among the plurality of instructions 2 being simultaneously decoded, and also indicates a referenceable instruction. When the detecting means 8 detects an instruction whose operand can be referred to among a plurality of instructions being simultaneously decoded with reference to the processing status table 7, the feed control means 9 executes the execution detected by the necessary instruction detecting means 3. Among the instructions currently being decoded, which require the unit 1, the instruction detected by the referenceable instruction detecting means 8 is supplied to the empty execution unit 1 and the instruction to which the operand is referenceable is sent to the execution unit 1 because the operand is not referenceable. The command that could not be fed is sent to the command storage means 4 for storage.
[0014]
Accordingly, the instruction during decoding can be fed to the execution unit in parallel in the same cycle (dispatch cycle) for feeding the instruction storing means, so that even a complicated instruction set can be processed at high speed. At this time, since the feed control is performed based on whether or not the operands of the instruction being decoded can be referred to, it is possible to avoid a possibility that the processing may be stagnated due to an increase in the stored decoded instructions.
[0015]
FIG. 3 is a principle block diagram of the third aspect of the present invention.
According to a third aspect of the present invention, in an information processing apparatus including a plurality of execution units 1 that can operate simultaneously, a configuration for controlling the transmission of a plurality of instructions 2 decoded simultaneously to a plurality of execution units 1 is provided. A required instruction detecting means 3 for detecting an instruction requiring an execution unit from among a plurality of instructions being decoded, a processing status table 7 for setting processing statuses for each of the plurality of instructions to be decoded, A reference-possible-instruction detection means 8 for detecting an instruction whose operand can be referred to among a plurality of instructions being simultaneously decoded with reference to the processing status table 7; an instruction storage means 4 for temporarily storing decoded instructions; Among the instructions currently being decoded that require the execution unit detected by the instruction detection means 3, the execution unit which has an available instruction that the operand detected by the referenceable instruction detection means 8 can refer to is unoccupied. A first feed control means 10 for feeding to the instruction storage means 4 an instruction which is not supplied to the execution unit because the operands cannot be referred to, and is stored in the instruction storage means 4; When the transmission control means 10 sends a decoded instruction to the instruction storage means 4, the registration means 11 registers in the instruction storage means 4 whether or not the operand of the decoded instruction can be referred to, and the registration of the decoded instruction in the instruction storage means 4. A second feed control unit for feeding an instruction whose operand can be referred to the execution unit, and an instruction detecting unit for detecting a valid instruction whose operand can be referred to among the decoded instructions in the instruction storage unit. In the instruction storage means 4 according to the magnitude relation between the number of instructions detected by the instruction detection means 13 among the decoded instructions in the instruction storage means 13 and the number of free execution units. Effective and referenceable feeding to it all the instructions to the execution unit, fed to the execution unit to a vacant part of the effective and reference instructions To do And a third feed control means 14 for performing the following.
[0016]
That is, according to the third aspect of the present invention, in the decoding cycle, the necessary instruction detecting means 3 detects an instruction that requires the execution unit 1 from among a plurality of instructions 2 that are being decoded at the same time. When the detecting means 8 detects an instruction whose operand can be referred to among a plurality of instructions being simultaneously decoded with reference to the processing status table 7, the first feed control means 10 Of the instructions currently being decoded that require the execution unit 1, the instruction detected by the referenceable instruction detecting means 8 is supplied to the empty execution unit 1 and the instruction is referenced to the empty execution unit 1. The instruction that could not be fed to the first storage unit 1 is fed to the instruction storage unit 4 for storage.
[0017]
At this time, the registration unit 11 registers in the instruction storage unit 4 whether or not the operand of the decoded instruction to be sent to the instruction storage unit 4 by the first feed control unit 10 can be referred to. Thereby, the second feed control means 12 Supplies an instruction whose operand can be referred to among the decoded instructions in the instruction storage means 4 to the execution unit.
Then, the third feed control unit 14 sends all of the valid and referable instructions in the instruction storage unit 4 to the execution unit according to the number of instructions detected by the instruction detection unit 13 and the number of free execution units 1. Feeding, part of valid and referable instructions to a free execution unit To do I do.
[0018]
Thus, the instruction during decoding can be sent to the execution unit in parallel in the same cycle (dispatch cycle) in which the instruction is sent to the instruction storage means without causing a stagnation of the processing. Becomes possible. At this time, the feed control of the decoded instruction in the instruction storage means is performed based on the validity of the decoded instruction and whether or not the operand can be referred to, so that the feed control can be performed more smoothly and reliably.
[0019]
According to a fourth aspect of the present invention, in the information processing apparatus according to any one of the first to third aspects, the plurality of execution units 1 includes a plurality of types of execution unit groups that perform different processes, The required instruction detecting means 3 detects an instruction requiring an execution unit for each execution unit group.
That is, according to the fourth aspect of the present invention, the feed control for a plurality of types of execution unit groups that perform different processes can be realized by the first aspect of the present invention.
[0020]
As a result, the operation targeted by the instruction set of the CISC method can be processed in three cycles of {(decoding) cycle} and {(dispatch) + (execution) cycle} and {(execution) cycle}. Thus, high-speed processing of a complicated instruction set becomes possible.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0022]
FIG. 4 shows a configuration of an embodiment corresponding to claims 1 to 4. The instruction control method according to this embodiment includes a plurality of instruction registers 40-1 to 40-n, a control unit 41, a storage register group 42, and a plurality of execution units 43-1 to 43-m. The control unit 41 receives instructions from a plurality of instruction registers 40-1 to 40-n in a certain instruction processing cycle and decodes them simultaneously (decoding cycle D1). Dispatching in parallel to the execution units 43-1 to 43-m and the storage register group 42, and executing the decoded instructions stored in the storage register group 42 in the next processing cycle. -M and dispatching in parallel to the storage register group 42 are repeated in each cycle.
[0023]
That is, the control unit 41 performs the dispatch cycle D2 and the instruction execution cycle E1 in the instruction processing cycle in the CISC system in parallel so that the instruction execution cycle E2 can be executed at the same timing as the instruction execution cycle E in the RISC system. Controls dispatch of instructions.
As a result, in the dispatch cycle D2, address calculation and memory access become possible in parallel with the dispatch (instruction execution cycle E1). You Thus, the operation of the register operand and the memory operand can be executed (instruction execution cycle E2).
[0024]
That is, in the instruction control method of this embodiment, processing of an instruction set formed by the CICS method can be realized in the same number of cycles as processing of an instruction set formed by the RISC method.
This embodiment includes a first embodiment in which "a plurality of execution units are handled without being distinguished" and a second embodiment in which "a plurality of execution units are grouped according to their characteristics". However, for convenience of explanation, the number of execution units is 2 in the first embodiment and 3 in the second embodiment. In addition, the number of simultaneous decoding instructions is three.
[0025]
[First Embodiment: Corresponding to Claim 1]
FIG. 5 is a configuration example of the control unit 41 of the first embodiment. The control unit 41 of the first embodiment includes a decoder 51, a selection control circuit 52, and a selection circuit 53. The storage register group 42 is described as a storage register group 42a.
IWR0, IWR1, and IWR2 are instructions set in the instruction register, respectively, and are input to the decoder 51 and the selection circuit 53, respectively. Decoder 51 Is The instruction being decoded is decoded to detect whether the execution unit is used (that is, whether it is necessary), and the information (whether the execution unit is necessary) is given to the selection control circuit 52.
[0026]
One of the two outputs of the storage register group 42a (information of the stored instruction) is supplied to the selection circuit 53, and the other (validity flag) is supplied to the selection control circuit 52. The selection circuit 53 selects four inputs according to the output of the selection control circuit 52, and distributes (dispatches) them to the two execution units EU0 and EU1 and the storage register group 42a.
[0027]
FIG. 6 is a configuration example of the storage register group 42a according to the first embodiment. As shown in FIG. 6, the decoded instructions (instruction 1, instruction 2,...) Are stored in each register of the storage register group 42a. The validity bit (Valid bit) is set.
The validity bit is "1" (valid) while the instruction is stored in the register, but becomes "0" when fetched to the execution unit. That is, FIG. 6 shows that instructions 1 to 3 are stored instructions (valid instructions) and instruction 4 is a retrieved instruction. Note that the sequence number (IID) does not particularly relate here, and thus the description is omitted.
[0028]
In this embodiment, in each register of the storage register group 42a, the 0th register is represented by RES0, the first register is represented by RES1, the second register is represented by RES2, and the third register is represented by RES3. Also, the validity bit is denoted by V, V = “1” is denoted by “+”, and V = “0” is denoted by “−”. This is the contents of the validity flag output from the storage register group 42a to the selection control circuit 52.
[0029]
Specifically, for example, the validity flag for the 0th register is “+ RES0 · V, −RES0 · V”, and the validity flag for the first register is “+ RES1 · V, −RES1 · V”. And the validity flag for the second register is “+ RES2 · V, −RES2 · V”. In each case, the level is high.
[0030]
In addition to the decoded instruction, various information of each decoded instruction is given from each register of the storage register group 42a to the selection circuit 53. This is necessary for execution of instructions in the execution unit. In this embodiment, “OPECODE” is taken as an example. Specifically, for example, “+ RES0 · OPECODE” is output for the instruction of the 0th register, and “+ RES1 · OPECODE” is output for the instruction of the first register.
[0031]
FIG. 7 is an example of an ENTRY signal generation circuit in the selection control circuit 52. This ENTRY signal generation circuit is a circuit for detecting the number of valid instructions stored in the storage register group 42a.
In this embodiment, as shown in FIG. 6, four registers 0 to 3 are considered. Therefore, the input (validity flag) from the storage register group 42a is "+ RES0.V or -RES0.V", "+ RES1.V or -RES1.V", "+ RES2.V or -RES2.V", " + RES3.V or -RES3.V ".
[0032]
The NAND 71 receives −RES0 · V, −RES1 · V, −RES2 · V, and −RES3 · V. That is, the NAND 71 sets the output to a low level when there is no valid instruction in any of the four registers from the 0th to the 3rd. This is the content of "-0 ENTRY". That is, in the NAND 71, if there is a valid instruction in any one of the four registers, the output is set to the high level. This is one input of AND81 in FIG.
[0033]
The AND72 receives + RES0.V, -RES1.V, -RES2.V, and -RES3.V. That is, the AND 72 sets the output to a high level when a valid instruction exists in the 0th register among the 0th to 3rd registers. This is the first input of the NOR 76. The AND73 receives −RES0 · V, + RES1 · V, −RES2 · V, and −RES3 · V. That is, AND 7 No. 2 sets the output to a high level when a valid instruction exists in the first register among the four registers from the 0th to the 3rd. This is the NOR76 1 Input.
[0034]
AND74 receives -RES0.V, -RES1.V, + RES2.V, and -RES3.V. That is, the AND 74 sets the output to a high level when a valid instruction exists in the second register among the four registers from the 0th to the 3rd. This is NOR 7 6 is the third input.
AND75 receives -RES0.V, -RES1.V, -RES2.V, and + RES3.V. That is, the AND 75 sets the output to a high level when a valid instruction exists in the third register among the four registers from the 0th to the 3rd. This is the fourth input of NOR 66.
[0035]
In these ANDs 72, 73, 74, and 75, when there are two or more valid instructions, the output is set to low level. Therefore, in the NOR 76, when an effective instruction exists in any one of the four registers from the 0th to the 3rd, the output is set to the low level. This is the content of "-1 ENTRY". On the other hand, when there are two or more valid instructions, the NOR 76 sets the output to a high level. This is the other input of AND81 in FIG.
[0036]
FIG. 8 is an example of a selection signal generation circuit in the selection control circuit 52. The output (selection signal) of the selection signal generation circuit is output to the selection circuit 53. In FIG. 8, one input of the AND 81 is “−0 ENTRY”, the other input is “−1 ENTRY”, and the output is connected to one input of the ANDs 84 and 87. The input of the inverter 82 is “−0 ENTRY”, and the output is connected to one input of the AND 85, the first input of the AND 90, and the second input of the AND 91. The input of the inverter 83 is “−1 ENTRY”, and the output is connected to one input of the AND 86 and the first input of the AND 88 and AND 92.
[0037]
The signals “+ D0 EX”, “+ D1 EX” and “−D0 EX” are 5 Input from 1. These are obtained from the instructions (IWR0, IWR1) being decoded by the decoder 51. “+ D0 EX” is a signal indicating that the instruction of IWR0 uses the execution unit. “+ D1 EX” is a signal indicating that the IWR1 instruction uses the execution unit. “−D0 EX” is a signal indicating that the instruction of IWR0 does not use the execution unit. These are at a high level in each case. FIG. 8 shows that the decoder 51 detects whether or not the instructions of IWR0 and IWR1 require an execution unit.
[0038]
The input signal “+ D0 EX” is applied to the other input of AND84, 85, 86, the second input of AND88, and the first input of AND91. The input signal “+ D1 EX” is applied to the other input of AND77, the third input of AND88, 90, 91, and the second input of AND92. The input signal “−D0 EX” is applied to the second input of the AND 90 and the third input of the AND 92.
[0039]
Next, the AND 84 outputs a signal “+ D0 TO RS”. This signal "+ D0TO RS" is a selection signal for dispatching the instruction of IWR0 to the storage register group 42a. AND85 outputs the signal “+ D0 TO EU0”. This signal "+ D0 TO EU0" is a selection signal for dispatching the instruction of IWR0 to the execution unit EU0.
[0040]
The outputs of the ANDs 87 and 88 are connected to the inputs of the OR 89, respectively. OR89 outputs a signal “+ D1 TO RS”. This signal “+ D1 TO RS” is a selection signal for dispatching the instruction of IWR0 to the storage register group 42a. AND90 outputs the signal “+ D1 TO EU0”. This signal “+ D1 TOEU0” is a selection signal for dispatching the instruction of IWR1 to the execution unit EU0.
[0041]
The outputs of the ANDs 91 and 92 are connected to the input of the OR 93. OR93 outputs a signal “+ D1 TO EU1”. This signal “+ D1 TO EU1” is a selection signal for dispatching the instruction of IWR1 to the execution unit EU1.
Next, FIG. 9 is an example of an execution unit selection signal generation circuit in the selection control circuit 52. The execution unit selection signal generation circuit generates an execution unit selection signal based on the validity flag from each register of the storage register group 42a, and outputs it to the selection circuit 4.
[0042]
In FIG. 9, the signal “+ RES0 · V” is applied to the input of the buffer 94 and also to one input of the AND 97 and the first input of the AND 98. The signal “−RES0 · V” is applied to one input of AND95 and the first input of AND96,99.
The signal “+ RES1 · V” is applied to the other inputs of ANDs 95 and 97 and the second input of AND99. The signal “−RES1 · V” is applied to the second inputs of ANDs 96 and 98. “+ RES2 · V” is applied to the third inputs of ANDs 96, 98, and 99. The outputs of the ANDs 98 and 99 are connected to the inputs of the OR 100, respectively.
[0043]
The buffer 94 outputs a signal “+ SEL · RES0 · EU0”. This signal "+ SEL.RES0.EU0" is a selection signal for dispatching the valid instruction of the 0th register to the execution unit EU0. The AND 95 outputs a signal “+ SEL · RES1 · EU0”. The signal "+ SEL.RES1.EU0" is a selection signal for dispatching a valid instruction of the first register to the execution unit EU0 when the instruction of the 0th register is not valid and the instruction of the first register is valid.
[0044]
AND96 outputs the signal "+ SEL.RES2.EU0". This signal "+ SEL.RES2.EU0" causes the valid instruction of the second register to be dispatched to the execution unit EU0 when the instructions of the 0th and 1st registers are not valid and the instruction of the 2nd register is valid. This is a selection signal.
The AND 97 outputs a signal “+ SEL · RES1 · EU1”. This signal "+ SEL.RES1.EU1" is a selection signal for dispatching a valid instruction in the first register to the execution unit EU1 when both the instruction in the 0th register and the instruction in the first register are valid.
[0045]
OR100 outputs a signal “+ SEL · RES2 · EU1”. This signal "+ SEL.RES2.EU1" is output when both the instruction of the 0th register, the instruction of the first register, and the instruction of the second register are valid (output of AND98), or the instruction of the 0th register and the first instruction. When both register instructions are not valid and the second register instruction is valid (the output of AND99), this is a selection signal for dispatching the valid instruction of the second register to the execution unit EU1.
[0046]
FIG. 10 is an example of an instruction code selection circuit in the selection circuit 53. 10, in the selection circuit 53, the selection control circuit 52 outputs selection signals “+ SEL.RES0.EU0”, “+ SEL.RES1.EU0”, “+ SEL.RES2.EU0”, “+ SEL.RES1.EU1”, “+ SEL.RES1.EU1” + SEL.RES2.EU1 "respectively. Also, signals “+ RES0 · OPECODE”, “+ RES1 · OPECODE”, and “+ RES2 · OPECODE” are input from the storage register group 42a.
[0047]
Therefore, the AND 101 receives the signal “+ SEL.RES0.EU0” at one input and the signal “+ RES0.OPECODE” at the other input, and provides an output to the first input of the OR 103. The AND 102 receives the signal “+ SEL.RES1.EU0” at one input and the signal “+ RES1.OPECODE” at the other input, and provides an output to the second input of the OR 103.
[0048]
AND10 4 is The signal "+ SEL.RES2.EU0" is input to one input, and the signal "+ RES2.OPECODE" is input to the other input, and the output is given to the third input of the OR 103. The OR 103 outputs a signal “+ EU0 OPECODE” to the execution unit EU0.
The AND 105 receives the signal “+ SEL · RES1 · EU1” at one input and the signal “+ RES1 · OPECODE” at the other input, and provides an output to one input of the OR 107. The AND 106 receives the signal “+ SEL · RES2 · EU1” at one input and the signal “+ RES2 · OPECODE” at the other input, and provides an output to the other input of the OR 107. The OR 107 outputs a signal “+ EU1 OPECODE” to the execution unit EU1.
[0049]
The selection circuit 53 dispatches the information of IWR0 and IWR1 to the execution units EU0 and EU1 according to the selection signal shown in FIG. 8, dispatches the information to the storage register group 12, and further executes the instructions of the storage register group 12 to the execution units EU0 and EU0. Dispatch to EU1. At this time, "OPECODE" of each valid instruction is dispatched to the corresponding execution unit in the procedure shown in FIG.
[0050]
The correspondence between the above configuration and claim 1 is as follows. The execution unit 1 corresponds to the execution units 43-1 to 43-m (EU0, EU1). The decoder 51 corresponds to the necessary instruction detecting means 3. A storage register group 42 (42a) corresponds to the instruction storage means 4. The selection control circuit 52 corresponds to the valid instruction detection means 5. The selection control circuit 52 mainly corresponds to the feed control means 6.
[0051]
Hereinafter, the operation of the first embodiment will be described with reference to FIGS.
First, in a state where the decoded instruction is not stored in the storage register group 42a, that is, in a state where there is no valid instruction, in FIG. 7, the "-0. ENTRY" signal is low and the "-1. ENTRY" signal is low. High level. As a result, in FIG. 8, the output level of the inverter 82 is high, so that the input states of the ANDs 85, 90, and 91 are problematic. The following operations (1), (2), and (3) are performed.
[0052]
(1) When the decoder 51 detects that only the IWR0 instruction requires an execution unit. In this case, since the decoder 51 sets “+ D0 EX” to a high level and “+ D1 EX” to a low level, the AND 85 sets the output to a high level, and the ANDs 90 and 91 set the output to a low level. Therefore, the selection circuit 51 sends (dispatches) the instruction of IWR0 to the execution unit EU0 based on the output “+ D0 TO EU0” of the AND85.
[0053]
(2) When the decoder 41 detects that only the IWR1 instruction requires an execution unit. In this case, since the decoder 51 sets “+ D1 EX” and “−D0 EX” to the high level, the AND 90 sets the output to the high level, and the ANDs 85 and 91 set the output to the low level. Therefore, the selection circuit 51 dispatches the instruction of IWR1 to the execution unit EU0 based on the output “+ D1 TO EU0” of the AND90.
[0054]
(3) When the decoder 51 detects that both the IWR1 and IWR2 instructions require an execution unit. In this case, since the decoder 51 sets “+ D0 EX” and “+ D1 EX” to the high level, the ANDs 85 and 91 set the output to the high level, and the AND 90 sets the output to the low level. Therefore, the selection circuit 51 dispatches the instruction of IWR0 to the execution unit EU0 based on the output “+ D0 TO EU0” of AND85, and at the same time, transmits the instruction of IWR1 to the execution unit EU1 based on the output “+ D1 TO EU1” of OR93. Dispatch.
[0055]
Next, in the state where one valid instruction is stored in the storage register group 42a, in FIG. 7, the "-0 ENTRY" signal is at a high level, and the "-1 ENTRY" signal is at a low level. As a result, in FIG. 8, since the output of the inverter 83 is at a high level, the input states of the ANDs 86, 88, and 92 become problematic. The following operations (4), (5), and (6) are performed.
[0056]
(4) When the decoder 51 detects that only the instruction of IWR0 needs an execution unit. In this case, since the decoder 51 sets “+ D0 EX” to a high level and “+ D1 EX” to a low level, the AND 86 sets the output to a high level, and the ANDs 88 and 92 set the output to a low level. Therefore, the selection circuit 51 dispatches the instruction of IWR0 to the execution unit EU1 based on the output “+ D0 TO EU1” of the AND 86.
[0057]
(5) When the decoder 51 detects that only the IWR1 instruction requires an execution unit. In this case, since the decoder 51 sets “+ D1 EX” and “−D0 EX” to the high level, the AND 92 sets the output to the high level, and the ANDs 86 and 88 set the output to the low level. Therefore, the selection circuit 51 dispatches the instruction of the IWR1 to the execution unit EU1 based on the output “+ D1 TO EU1” of the OR93.
[0058]
(6) When the decoder 51 detects that both the IWR1 and IWR2 instructions require an execution unit. In this case, since the decoder 51 sets “+ D0 EX” and “+ D1 EX” to the high level, the ANDs 86 and 88 set the output to the high level, and the AND 92 sets the output to the low level. Therefore, the selection circuit 51 dispatches the instruction of IWR0 to the execution unit EU1 based on the output “+ D0 TO EU1” of the AND 86, and at the same time, stores the instruction of IWR1 based on the output “+ D1 TO RS” of the OR89. Dispatch to
[0059]
Next, in a state where two or more valid instructions are stored in the storage register group 42a, in FIG. 7, both the "-0 ENTRY" signal and the "-1 ENTRY" signal are at a high level. As a result, in FIG. 8, the output of the inverter 81 is at a high level, so that the input states of the ANDs 84 and 87 pose a problem. The following operations (7), (8), and (9) are performed.
[0060]
(7) When the decoder 51 detects that only the IWR0 instruction requires an execution unit. In this case, since the decoder 51 sets "+ D0 EX" to a high level and "+ D1 EX" to a low level, the AND 84 sets the output to a high level and the AND 87 sets the output to a low level. Therefore, the selection circuit 51 dispatches the instruction of IWR0 to the storage register group 42a based on the output “+ D0 TORS” of the AND84.
[0061]
(8) When the decoder 51 detects that only the IWR1 instruction requires an execution unit. In this case, since the decoder 51 sets “+ D1 EX” to the high level, the AND 87 sets the output to the high level, and the AND 84 sets the output to the low level. Therefore, the selection circuit 51 dispatches the instruction of IWR1 to the storage register group 42a based on the output “+ D1 TORS” of the OR89.
[0062]
(9) When the decoder 51 detects that both the IWR1 and IWR2 instructions require an execution unit. In this case, since the decoder 51 sets “+ D0 EX” and “+ D1 EX” to a high level, the ANDs 84 and 87 respectively set the outputs to a high level. Therefore, the selection circuit 51 dispatches the IWR0 instruction to the storage register group 42a based on the output “+ D0 TORS” of the AND 84, and at the same time, transmits the IWR1 instruction based on the output “+ D1 TORS” of the OR89. Dispatch to 42a.
[0063]
The selection control circuit shown in FIG. 8 operates as described above. The contents of the dispatch are arranged as follows.
(A) The signal "+ D0 TORS" for dispatching the IWR0 instruction to the storage register group 42a occurs when the IWR0 instruction uses an execution unit and the storage register group 42a has two or more valid instructions. I do. This is the case where the number of unprocessed instructions exceeds the number of execution units.
[0064]
(B) The signal “+ D0TO EU0” for dispatching the instruction of the IWR0 to the execution unit EU0 is generated when the instruction of the IWR0 uses the execution unit EU0 and there is no valid instruction in the storage register group 42a. This is the opposite case to (a).
(C) The signal "+ D0TO EU1" for dispatching the instruction of the IWR0 to the execution unit EU1 is generated when the instruction of the IWR0 uses the execution unit EU1 and there is one valid instruction in the storage register group 42a. This is the same case as (b).
[0065]
(D) A signal "+ D1TORS" for dispatching an IWR1 instruction to the storage register 42a is used when the IWR1 instruction uses an execution unit, when there are two or more valid instructions in the storage register group 42a, or when the instruction is stored. This occurs when there is one valid instruction in the register group 42b and the IWR0 instruction uses the execution unit.
[0066]
The former is the same case as (a). The latter is a case where the number of unprocessed instructions is smaller than the number of execution units, but one free execution unit is assigned to another competing instruction.
(E) The signal “+ D1TO EU0” for dispatching the instruction of the IWR1 to the execution unit EU0 indicates that when the instruction of the IWR1 uses the execution unit, there is no valid instruction in the storage register group 42a and the instruction of the IWR0 is the execution unit. Occurs when is not used. This is the case where there is no unprocessed instruction, the execution unit is empty, and there are no other conflicting instructions.
[0067]
(F) The signal "+ D1TO EU1" for dispatching the instruction of the IWR1 to the execution unit EU1 indicates that when the instruction of the IWR1 uses the execution unit, there is no valid instruction in the storage register group 42a and the instruction of the IWR0 is the execution unit. Or when there is one valid instruction in the storage register group 42a and the instruction of IWR0 does not use the execution unit.
[0068]
In the former case, there is no unprocessed instruction, the execution unit is empty, and the execution unit can be allocated together with other competing instructions. In the latter case, there are few unprocessed instructions and few free execution units, but there are no other instructions competing.
As described above, when the decoded instruction in the previous cycle is not stored in the storage register group 42a, the decoding instruction is dispatched directly to the execution unit, while the decoded instruction in the previous cycle is stored in the storage register group 42a. If it is stored, the instruction being decoded is dispatched to an empty execution unit, and the instruction being decoded that could not be dispatched to the execution unit is dispatched to the storage register group 42a.
[0069]
Then, in the next processing cycle, the selection control circuit 52 detects this storage instruction from the presence of the valid flag, and instructs the selection circuit 53 to retrieve the contents of each register of the storage register group 42a. Then, the selection circuit 53 takes out the instruction according to the selection signal shown in FIG. 7 and dispatches it to the corresponding execution unit.
[0070]
[Second Embodiment: Corresponding to Claims 2 to 4]
FIG. 11 is a configuration example of the control unit 41 of the second embodiment. The control unit of the second embodiment includes a decoder 111, a selection control circuit 112, an update pending state table 113, and a selection circuit 114. Note that the storage register group 42 is referred to as a storage register group 42b.
[0071]
IWR0, IWR1, and IWR2 are instructions set in the instruction register, respectively, and are input to the decoder 111 and the selection circuit 114, respectively. Of the two outputs of the decoder 111, one output (execution unit required) is provided to the selection control circuit 112, and the other output (reference address) is provided to the update pending state table 113.
[0072]
Of the two outputs of the storage register group 42b, one output (decoded instruction) is supplied to the selection circuit 114, and the other output (validity flag) is supplied to the selection control circuit 112. The update pending state table 113 is a table in which flags (P1, P2) indicating the update pending state are set for each register of the storage register group 42b, and the pending state flag (P1, P1) of the address designated by the selection control circuit 112 is set. P2) is output to the selection control circuit 112 and the selection circuit 114.
[0073]
The update pending state means that the instruction of the register is being processed or that the register is being used. The pending state flag given from the update pending state table 113 to the selection control circuit 112 is described as "D0 READY" or "D1 READY" (FIG. 14).
The selection control circuit 112 receives the outputs of the decoder 111, the storage register group 42b, and the update pending state table 113, and outputs a selection signal to the selection circuit 114. The selection circuit 114 selects five inputs according to the output of the selection control circuit 112 and distributes (dispatches) them to the three execution units EU0, EU1, and EU3 and the storage register group 42b.
[0074]
The three execution units EU0, EU1, and EU3 are execution unit groups in which the execution units EU0 and EU1 perform the same operation, and are execution unit groups in which the execution unit EU3 performs another operation. For example, the execution units EU0 and EU1 calculate an operand address, the execution unit EU3 calculates an instruction address, and so on.
[0075]
FIG. 12 is a configuration example of a storage register group 42b according to the second embodiment. In the second embodiment, in addition to the instruction and the validity bit shown in FIG. 6, addresses (ADRS1, ADRS2) and pending state flags (P1, P2) are stored in the storage register group 42b as shown in FIG. , An execution unit group (EU) is set.
[0076]
The address (ADRS1, ADRS2) is a register address for accessing a register of an execution unit that supplies (dispatches) an instruction. The pending state flags (P1, P2) are information indicating whether the register indicated by the address (ADRS1, ADRS2) is usable. If the register of the execution unit is available, that is, dispatchable, it means that the operand of the instruction dispatched to the register can be referred to.
[0077]
The pending state flags (P1, P2) are stored in the update pending state table 1 according to the reference address of the decoder 111 in the decoding cycle. 1 3 and output to the selection control circuit 112 as “D0 READY” and “D1 READY” described above.
In the dispatch cycle, the pending state flags (P1, P2) are read from the update pending state table 113 in accordance with the reference address of the decoder 111, and the selection circuit 114 causes the storage register group 42b to take in the storage registers 42b in accordance with the instruction of the selection control circuit 112. . These are operations for detecting whether an operand can be referred to and registering it.
[0078]
The execution unit group (EU) is information indicating which execution unit group an instruction stored in each register of the storage register group 42b uses.
The storage register group 42b of the second embodiment outputs signals such as “−RES0 · V”, “−RES0 · P1”, “−RES0 · P2”, “−RES0 · EU”, etc. 2 Output to
[0079]
FIG. 13 shows an example of the RES / READY generation circuit (a) and an example of the READY / EU generation circuit (b) in the selection control circuit 111.
In FIG. 13A, the RES / READY generation circuit includes four-input ANDs 131 and 133 and four-input NANDs 132 and 134.
“+ RES0 · V” is connected to first inputs of AND131, NAND132, AND133, and NAND134. “+ RES0 · P1” is connected to the second inputs of AND131, NAND132, AND133, and NAND134. “+ RES0 · P2” is connected to the third inputs of AND131, NAND132, AND133, and NAND134. “−RES0 · EU” is connected to the fourth inputs of the AND 131 and the NAND 132. “+ RES0 · EU” is connected to the fourth inputs of the AND 133 and the NAND 134.
[0080]
The AND 131 outputs “+ RES0 · READY 0/1”. The NAND 132 outputs “−RES0 · READY 0/1”. The AND 133 outputs “+ RES0 · READY 2”. The NAND 134 outputs “−RES0 · READY 2”.
Here, “+ RES0 · V” indicates that the instruction stored in the 0th register is valid. “+ RES0 · P1” indicates that the hold state flag P1 is not in the hold state, that is, the register specified by ADRES1 among the 0th registers can be referred to.
[0081]
“+ RES0 · P2” indicates that the hold state flag P2 is not in the hold state, that is, the register designated by ADRES2 among the 0th registers can be referred to. “−RES0 · EU” indicates that the instruction stored in the zeroth register does not use any of the execution units EU0 and EU1. “+ RES0 · EU” indicates that the instruction stored in the 0th register uses the execution unit EU2.
[0082]
Therefore, "+ RES0.READY 0/1" indicates that the registers specified by the 0th register ADRES1 and ADRES2 can both be referred to, and that the execution units EU0 and EU1 are used. Conversely, "-RES0.READY 0/1" indicates that the registers specified by the 0th register ADRES1 and ADRES2 can both be referred to, but there is no one that uses the execution units EU0 and EU1.
[0083]
“+ RES0 · READY 2” indicates that the registers specified by the 0th register ADRES1 and ADRES2 can both be referred to and that the execution unit EU2 is used. Conversely, "-RES0.READY2" indicates that the registers specified by the 0th register ADRES1 and ADRES2 can both be referred to, but there is no one that uses the execution unit EU2.
[0084]
Although not shown, similar circuits are prepared for RES1, RES2, and RES3. Thereby, "-RES0.READY 0/1, -RES1.READY 0/1, -RES2.READY 0/1, -RES3.READY0 / 1", "-RES0.READY2, -RES1.READY2, -RES2" READY 2, -RES3 READY 2 "and" + RES0 READY 0/1, + RES1 READY 0/1, + RES2 READY 0/1, + RES3 READY 0/1 ". These are given to the RES / EU generation circuit of FIG.
[0085]
In FIG. 13B, the RES / EU generation circuit includes four input NANDs 135, 136, and NAND137.
The NAND 135 receives “−RES0 • READY 0/1, −RES1 • READY 0/1, −RES2 • READY 0/1, −RES3 • READY 0/1” and “−0 READY • EU 0/1”. Is output. This output “−0 READY • EU 0/1” indicates that all the instructions stored in the 0th to 3rd registers are valid, and the registers specified by ADRES1 and ADRES2 can both be referred to. Indicates that there is no instruction that uses EU0 and EU1. This out Power" “-0READY · EU 0/1” is applied to one input of the AND 141 and the input of the inverter 142 of the selection control circuit shown in FIG.
[0086]
The NAND 136 receives “−RES0 • READY2, −RES1 • READY2, −RES2 • READY2, −RES3 • READY2” and outputs “−0 READY • EU2”. In this output "-0 READY.EU2", the instructions stored in the 0th to 3rd registers are all valid, and the registers specified by ADRES1 and ADRES2 can both be referred to, but the execution unit EU2 is used. Indicates that there is no instruction to perform. This output “−0 READY · EU2” is given to the buffer 144 and the inverter 145 of the selection control circuit shown in FIG.
[0087]
The NAND 137 receives “+ RES0 • READY 0/1, + RES1 • READY 0/1, + RES2 • READY 0/1, + RES3 • READY 0/1” and outputs “−1 READY • EU 0/1”. In this output "-1 READY.EU 0/1", the instructions stored in the 0th to 3rd registers are all valid, the registers specified by ADRES1 and ADRES2 can both be referred to, and the execution unit EU0 , EU1. This output “−1 READY · EU 0/1” is given to the other input of the AND 141 and the input of the inverter 143 of the selection control circuit shown in FIG.
[0088]
FIG. 14 shows the selection control circuit 11 2 5 is an example of a selection signal generation circuit in FIG. The output (selection signal) of the selection signal generation circuit is output to the selection circuit 114.
In FIG. 14, in the AND 141, one input is a signal “-0 READY EU 0/1”, the other input is a signal “+1 READY EU 0/1”, and the output is connected to one input of the ANDs 156 and 163. You. The input of the inverter 142 is a signal “−0 READY EU 0/1”, and the output is connected to the first inputs of the ANDs 150 and 158 and the second input of the AND 159. The input of the inverter 143 is a signal “+1 READY EU 0/1”, and the output is connected to the first input of the AND 151 and the second input of the AND 154.
[0089]
AND An input 144 is a signal “-0 READY EU 2”, and an output is connected to one input of ANDs 147 and 155. The inverter 145 has an input connected to the signal “−0 READY EU 2” and an output connected to first inputs of the ANDs 152 and 162.
The signals “+ D0 EX 0/1”, “+ D0 EX 2”, “+ D1 EX 0/1”, “+ D1 EX 2”, “−D0 EX”, and “−D0 EX 2” are input from the decoder 111. These are obtained from the instructions (IWR0, IWR1) being decoded by the decoder 111. The signals “−D0 READY” and “−D1 READY” are read from the update pending state table 113 according to the reference address of the decoder 111 and input in the decoding cycle.
[0090]
The signal “+ D0 EX 0/1” is a signal indicating that the instruction of IWR0 uses the execution units EU0 and EU1. This signal “+ D0 EX 0/1” is connected to the other input of AND146, one input of AND148, third inputs of AND150 and 151, and first inputs of AND154 and 159.
The signal “+ D0 EX2” is a signal indicating that the instruction of IWR0 uses the execution unit EU2. The signal “+ D0 EX 2” is connected to the other input of the AND 147 and the second input of the AND 152.
[0091]
The signal "-D0 READY" is a signal indicating that it is not possible to refer to the register operand of the IWR0 instruction. The signal “−D0 READY” is connected to the other input of the AND 148, the second inputs of the ANDs 150 and 151, and the third input of the AND 152.
The signal “+ D1 EX 0/1” is a signal indicating that the instruction of the IWR1 uses the execution units EU0 and EU1. This signal “+ D1 EX 0/1” is connected to the other input of the AND 153, the third input of the AND 154, one input of the AND 156, the fourth input of the 158 and 159, and the second input of the AND 160.
[0092]
The signal “+ D1 EX2” is a signal indicating that the instruction of the IWR1 uses the execution unit EU2. The signal “+ D1 EX2” is connected to the other input of the AND 155 and the second input of the AND 162.
The signal “−D1 READY” is a signal indicating that the signal cannot be referred to by the register operand of the IWR1 instruction. The signal “−D1 READY” is connected to the other input of the AND 156, the second input of the AND 158, the third input of the AND 159, the fourth input of the AND 160, and the third input of the AND 162.
[0093]
The signal “−D0 EX” is a signal indicating that the instruction of IWR0 does not use the execution unit. This signal “−D0 EX” is connected to the second input of AND 158 and the third input of AND 160.
The signal “−D0 EX2” is a signal indicating that the instruction of IWR0 does not use the execution unit EU2. The signal “−D0 EX 2” is connected to the fourth input of the AND 162.
[0094]
Next, the outputs of ANDs 146, 147, and 148 are connected to the inputs of OR 149, respectively. OR 149 outputs signal “+ D0 TO RS”. This signal "+ D0 TORS" is a selection signal for dispatching the instruction of IWR0 to the storage register group 42b.
AND 150 outputs a signal “+ D0 TO EU0”. This signal "+ D0 TO EU0" is a selection signal for dispatching the instruction of IWR0 to the execution unit EU0. The AND 151 outputs a signal “+ D0 TO EU1”. This signal "+ D0 TO EU1" is a selection signal for dispatching the instruction of IWR0 to the execution unit EU1. AND 152 outputs the signal “+ D1 TO EU2”. This signal “+ D1 TO EU2” is a selection signal for dispatching the instruction of IWR1 to the execution unit EU2.
[0095]
Outputs of the ANDs 153, 154, 155, and 156 are respectively connected to inputs of the OR 157. OR 157 outputs signal “+ D1 TO RS”. This signal "+ D1 TORS" is a selection signal for dispatching the IWR1 instruction to the storage register group 42b.
AND 158 outputs signal “+ D1 TO RS”. This signal "+ D1 TORS" is a selection signal for dispatching the IWR1 instruction to the storage register group 42b.
[0096]
Outputs of the ANDs 159 and 160 are respectively connected to inputs of the OR 161. OR 161 outputs signal “+ D1 TO EU1”. This signal “+ D1 TO EU1” is a selection signal for dispatching the instruction of IWR0 to the execution unit EU1.
AND 162 outputs signal “+ D1 TO EU2”. This signal “+ D1TO EU2” is a selection signal for dispatching the instruction of IWR1 to the execution unit EU2.
[0097]
The correspondence between the above configuration and claims 2 to 4 is as follows. The execution unit 1 corresponds to the execution units 43-1 to 43-m (EU0, EU1, EU2). The decoder 111 corresponds to the necessary instruction detecting means 3. A storage register group 42 (42b) corresponds to the instruction storage means 4. The update status table 113 corresponds to the processing status table 7. The decoder 111, the selection control circuit 112, and the entire update pending state table 113 correspond to the referenceable instruction detecting means 8. A selection control circuit 112 mainly corresponds to the first feed control unit 10, the registration unit 11, the second feed control unit 12, the command detection unit 13, and the third feed control unit 12.
[0098]
Hereinafter, the operation of the second embodiment will be described with reference to FIGS.
First, in a state where the decoded instruction is not stored in the storage register group 42b, that is, in a state where there is no valid instruction, the signals “−0 READY EU 0/1” and “−1 READY EU 0/1” in FIG. "-0 READY EU2" is both at a high level. As a result, in FIG. AND Since both outputs 144 have a high level, the input states of the ANDs 146 and 153 and the input states of the ANDs 147 and 155 are problematic. The following operations (10), (11), (12), and (13) are performed.
[0099]
(10) When the decoder 101 detects that only the instruction of IWR0 requires the execution units EU0 and EU1.
In this case, the decoder 111 sets the signal “+ D0 EX 0/1” to a high level and the signals “+ D0 EX 2”, “+ D1 EX 0/1”, and “+ D0 EX 2” to a low level. The signal “−D0 READY” input from the update pending state table 113 according to the reference address of the decoder 111 is at a low level. The output of AND 146 is provided to OR 149. Therefore, the selection circuit 114 dispatches the instruction of IWR0 to the storage register group 42b according to the output “+ D0 TORS” of the OR 149.
[0100]
(11) When the decoder 111 detects that only the instruction of IWR0 requires the execution unit EU2.
In this case, the decoder 111 sets the signal “+ D0 EX2” to a high level and the signals “+ D0 EX 0/1”, “+ D1 EX 0/1”, and “+ D0 EX2” to a low level. The signal “−D0 READY” input from the update pending state table 113 according to the reference address of the decoder 111 is at a low level.
[0101]
Therefore, the output of AND 147 is provided to OR 139, and selection circuit 114 dispatches the instruction of IWR 0 to storage register group 42b according to the output “+ D0 TO RS” of OR 149.
(12) When the decoder 111 detects that only the IWR1 instruction requires the execution units EU0 and EU1.
[0102]
In this case, the decoder 111 sets the signal “+ D1 EX 0/1” to a high level and the signals “+ D0 EX 2”, “+ D0 EX 0/1”, and “+ D1 EX 2” to a low level. The signal “−D1 READY” input from the update pending state table 113 in accordance with the reference address of the decoder 111 is at a low level.
Therefore, the output of AND 153 is provided to OR 157, and selection circuit 114 dispatches the instruction of IWR 1 to storage register group 42b according to the output “+ D1 TO RS” of OR 157.
[0103]
(13) When the decoder 111 detects that only the instruction of IWR1 requires the execution unit EU2. In this case, the decoder 111 sets the signal “+ D1 EX2” to a high level and the signals “+ D0 EX2”, “+ D0 EU 0/1”, and “+ D1 EU 0/1” to a low level. The signal “−D1 READY” input from the update pending state table 113 in accordance with the reference address of the decoder 111 is at a low level.
[0104]
Therefore, the output of AND 155 is provided to OR 157, and selection circuit 114 dispatches the instruction of IWR 1 to storage register group 42b according to the output “+ D1 TO RS” of OR 157.
Next, in the state where a valid instruction is stored in the storage register group 12b, the signals “−0 READY EU 0/1”, “−1 READY EU 0/1”, and “−0 READY EU 2” in FIG. It looks like this:
[0105]
a) The low-level signal "-0 READY EU 0/1" indicates that both the pending state flags P1 and P2 can refer to the operand when the execution unit group EU does not use the execution units EU0 and EU1. Is shown. In this case, in FIG. 14, since the output of the inverter 142 is at a high level, the input states of the ANDs 150, 158, and 159 pose a problem.
[0106]
The input signals of the AND 150 are “+ D0 EX 0/1” and “−D0 READY”. The signal "-D0 READY" indicates that the signal can be referred to by the register operand of the IWR0 instruction. The selection circuit 114 dispatches the instruction of IWR0 to the execution unit EU0 according to the output “+ D0 TOEU0” of the AND150.
The input signals of the AND 158 are “+ D1 EX 0/1” and “−D0 EX” from the decoder 111 and “−D1 READY” input from the update pending state table 113 according to the reference address of the decoder 111.
[0107]
The signal “+ D1 EX 0/1” is input when the decoder 111 detects that the instruction of the IWR1 requires the execution units EU0 and EU1. The signal “−D0 EX” is input when the decoder 111 detects that the instruction of IWR0 does not use the execution unit. The signal "-D1 READY" indicates that it can be referred to by the register operand of the IWR1 instruction.
[0108]
When these three input signals satisfy the conditions, the AND 158 outputs “+ D1 TO EU0”. The selection circuit 114 dispatches the instruction of IWR1 to the execution unit EU0.
The input signals of AND 159 are “+ D0 EX 0/1”, “+ D1 EX 0/1”, and “−D0 EX” from the decoder 111, and “−D1 READY” from the update pending state table 113. The signal “+ D0 EX 0/1” is input when the decoder 111 detects that the instruction of IWR0 requires the execution units EU0 and EU1.
[0109]
When these four signals satisfy such conditions, the AND 159 outputs “+ D1 TO EU1” via the OR 161. The selection circuit 114 dispatches the instruction of IWR1 to the execution unit EU1. Since the instruction of IWR0 has not been assigned an execution unit, it is dispatched to the storage register group 42b.
[0110]
b) The low-level signal "-1 READY EU 0/1" indicates that when the execution unit group EU uses one execution unit EU0 or EU1, both the pending state flags P1 and P2 can refer to operands. Indicates that there is. In this case, in FIG. 14, since the output of the inverter 143 is at a high level, the input states of the ANDs 151, 154, and 160 are problematic.
[0111]
The input signal of the AND 151 is “+ D0 EX 0/1” and “−D0 READY”. The signal "-D0 READY" indicates that the signal can be referred to by the register operand of the IWR0 instruction. The selection circuit 114 dispatches the instruction of IWR0 to the execution unit EU1 according to the output “+ D1 TO EU1” of the AND 151.
[0112]
The input signal of the AND 154 is “+ D0 EX 0/1” and “+ D1 EX 0/1”. The AND 154 outputs “+ D1 TO RS” via the OR 157 when the two signals satisfy such a condition. The selection circuit 114 dispatches the instruction of IWR1 to the storage register group 42b according to the output of the OR 157. The instruction of IWR0 is dispatched to the assigned execution unit.
[0113]
The input signals of the AND 160 are “+ D1 EX 0/1”, “−D1 READY”, and “−D0 EX”. The signal "-D1 READY" indicates that it can be referred to by the register operand of the IWR1 instruction.
When these three signals satisfy such conditions, the AND 160 outputs “+ D1 TO EU1” via the OR 161. The selection circuit 114 dispatches the IWRI instruction to the execution unit EU1 according to the output of the OR 161.
[0114]
c) The low-level signal "-0 READY EU2" indicates that both the pending state flags P1 and P2 can refer to the operands when the execution unit group EU does not use the execution unit EU2. In this case, in FIG. 14, since the output is made high by the inverter 145, the input state of the ANDs 152 and 162 becomes a problem.
[0115]
The input signal of the AND 152 is “+ D0 EX2” from the decoder 111 and “−D0 READY” input from the update pending state table 113.
The signal “+ D0 EX2” is input when the decoder 111 detects that the instruction of the IWR1 requires the execution unit EU2. The signal "-D0 READY" indicates that the signal can be referred to by the register operand of the IWR0 instruction.
[0116]
The AND 152 outputs “+ D0 TO EU2” when the two input signals satisfy the condition as described above. The selection circuit 114 dispatches the instruction of IWR0 to the execution unit EU2 according to the output of the AND 152.
[0117]
The input signals of the AND 162 are “+ D1 EX2” and “−D0 EX2” from the decoder 111 and “−D1 READY” from the update pending state table 113. The signal “+ D1 EX2” is input when the decoder 111 detects that the instruction of the IWR1 requires the execution unit EU2. The signal “−D0 EX2” is input when the decoder 111 detects that the instruction of IWR0 does not require the execution unit EU2.
[0118]
When these three signals satisfy such a condition, the AND 162 outputs a signal “+ D1 TO EU2”. The selection circuit 114 dispatches the instruction of IWR1 to the execution unit EU2 according to the output of AND162.
The AND 156 receives the signals “+ D1 EX 0/1” and “−D1 READY” and outputs the signal “+ D1 TORS” via the OR 157. The selection circuit 114 dispatches the instruction of IWR1 to the storage register group 42b according to the output of the OR 157. The execution unit could not be allocated.
[0119]
The selection control circuit shown in FIG. 13 operates as described above. The contents of the dispatch are arranged as follows.
(A) The signal "+ D0TORS" for dispatching the instruction of IWR0 to the storage register 12b occurs in the following cases.
* 1. When the instruction of IWR0 uses the execution units EU0 and EU1.
[0120]
When the operands can be referred to in the storage register group 42b and there are two or more instructions using the execution units EU0 and EU1,
Or, when the operand cannot be referenced in the storage register group 42b
* 2. When the instruction of IWR0 uses the execution unit EU2.
When operands can be referenced in storage register group 12b and one or more instructions using execution unit EU2 are valid
(B) The signal "+ D0TO EU0" for dispatching the instruction of the IWR0 to the execution unit EU0 is such that the instruction of the IWR0 can refer to the operand, and the execution units EU0 and EU1 can be used to refer to the operand in the storage register group 42b. , And an instruction using the execution units EU0 and EU1 is not valid.
[0121]
(C) The signal "+ D0TO EU1" for dispatching the instruction of the IWR0 to the execution unit EU1 can refer to the operand of the instruction of the IWR0, use the execution units EU0 and EU1, and refer to the operand in the storage register group 42b. , And when one instruction using the execution units EU0 and EU1 is valid.
[0122]
(D) The signal “+ D0TO EU2” for dispatching the instruction of the IWR0 to the execution unit EU2 can refer to the operand of the instruction of the IWR0, use the execution unit EU2, and refer to the operand in the storage register group 42b, and Occurs when an instruction using execution unit EU2 is not valid.
(E) The signal "+ D1TORS" for dispatching the instruction of the IWR1 to the storage register 42b is generated in the following cases.
[0123]
* 1. When the instruction of the IWR1 uses the execution units EU0 and EU1.
When the operands can be referred to in the storage register group 42b and there are two or more instructions that use the execution units EU0 and EU1, or when the operands cannot be referred to in the storage register group 42b, the IWR0 instruction is executed at the same time. When using units EU0 and EU1
* 2. When the instruction of the IWR1 uses the execution unit EU2, the operands can be referred to in the storage register group 42b, and one or more instructions using the execution unit EU2 are valid.
(F) The signal "+ D1TO EU0" for dispatching the instruction of the IWR1 to the execution unit EU0 is such that the instruction of the IWR1 can refer to the operand, and the execution units EU0 and EU1 can be used to refer to the operand in the storage register group 42b. Occurs when the instruction using the execution units EU0 and EU1 is valid and the instruction of IWR0 does not use the execution unit.
[0124]
(G) The signal “+ D1TO EU1” for dispatching the instruction of the IWR1 to the execution unit EU1 can refer to the operand of the instruction of the IWR1, use the execution units EU0 and EU1, and refer to the operand in the storage register group 42b. Occurs when one instruction using the execution units EU0 and EU1 is valid and the instruction of IWR0 does not use the execution unit.
(H) The signal “+ D1TO EU2” for dispatching the instruction of the IWR1 to the execution unit EU2 is such that the instruction of the IWR1 can refer to the operand, uses the execution unit EU2, and refers to the operand in the storage register group 42b, and Occurs when an instruction using the execution unit EU2 is not valid and the instruction of IWR0 does not use the execution unit EU2.
[0125]
In the second embodiment, it is shown that the CISC instruction set can be processed in the same number of cycles as the RISC instruction set, but the dispatch is controlled by referring to the operand. The processing speed can be improved as compared with the first embodiment in which the validity bit is confirmed and controlled. Therefore, as an embodiment corresponding to claims 2 and 3, in the method of the first embodiment, an update pending state table similar to that of the second embodiment is provided, and the storage register group 42a is configured like the storage register group 42b. Then, dispatch can be controlled with reference to the operand in the same manner, and the processing speed can be improved as in the second embodiment. In the second and third embodiments, the nature of the execution unit is not particularly limited, as in the first embodiment.
[0126]
【The invention's effect】
As described above, according to the first aspect of the present invention, in the decoding cycle, the number of instructions being decoded and the effective number of stored decoded instructions that require an execution unit are detected, and the number of execution units is set to the number of effective instructions. If the number is larger than the number, a part of the decoding instruction is supplied to the empty execution unit, and the decoding instruction which cannot be supplied because the execution unit is not allocated is supplied to the instruction storage means.
[0127]
In other words, the instructions during decoding can be sent to the execution unit in parallel in the same cycle (dispatch cycle) for sending to the instruction storage means, so that even a complicated instruction set can be processed at high speed.
According to a second aspect of the present invention, in the decoding cycle, the number of instructions being decoded that require an execution unit and the number of instructions being decoded that allow an operand to be referenced are detected, and the execution unit that has an available instruction whose operand can be referenced is vacant. The instruction which cannot be supplied to the execution unit because the operand is not referable is supplied to the instruction storage means and stored.
[0128]
Thus, the instruction during decoding can be fed to the execution unit in parallel in the same cycle (dispatch cycle) for feeding the instruction storing means, so that high-speed processing can be performed even for a complicated instruction set. At this time, since the feed control is performed based on whether or not the operands of the in-command instruction can be referred to, it is possible to avoid a possibility that the processing may be stagnated due to an increase in the number of stored decoded instructions.
[0129]
According to a third aspect of the present invention, in the decoding cycle, the number of instructions being decoded that require an execution unit and the number of instructions being decoded that can be referenced by an operand are detected, and the execution unit that has an instruction whose operand can be referenced is vacant. The instruction that could not be supplied to the execution unit because the operand was not available for reference is supplied to the instruction storage means for storage, and the instruction whether the operand of the decoded instruction to be supplied to the instruction storage means can be referenced is provided. The registration of the decoded instruction stored in the storage unit and the control of the decoded instruction stored in the instruction storage unit are performed based on the validity and the availability of the operand.
[0130]
Thus, the instruction during decoding can be sent to the execution unit in parallel in the same cycle (dispatch cycle) in which the instruction is sent to the instruction storage means without causing a stagnation of the processing. In addition, since the feed control of the decoded instruction in the instruction storage means is performed based on the validity of the decoded instruction and whether or not the operand can be referred to, the feed control can be performed more smoothly and reliably.
[0131]
According to a fourth aspect of the present invention, the feed control for a plurality of types of execution unit groups that perform different processes can be realized by the first aspect of the present invention.
As a result, the operation targeted by the instruction set of the CISC method can be processed in three cycles of {(decoding) cycle} and {(dispatch) + (execution) cycle} and {(execution) cycle}. Thus, high-speed processing of a complicated instruction set becomes possible.
[Brief description of the drawings]
FIG. 1 is a principle block diagram of the invention according to claim 1;
FIG. 2 is a principle block diagram of the invention according to claim 2;
FIG. 3 is a principle block diagram of the invention according to claim 3;
FIG. 4 is a configuration diagram of an embodiment corresponding to claims 1 to 4;
FIG. 5 is a configuration diagram of a control unit according to the first embodiment.
FIG. 6 is a configuration diagram of a storage register group according to the first embodiment.
FIG. 7 is a configuration diagram of a selection control circuit (ENTRY signal generation circuit) of the first embodiment.
FIG. 8 is a configuration diagram of a selection control circuit (feed destination selection signal generation circuit) of the first embodiment.
FIG. 9 is a configuration diagram of a selection control circuit (execution unit selection signal generation circuit) of the first embodiment.
FIG. 10 is a configuration diagram of a selection circuit (instruction code selection circuit) of the first embodiment.
FIG. 11 is a configuration diagram of a control unit according to a second embodiment.
FIG. 12 is a configuration diagram of a storage register group according to the second embodiment.
FIG. 13 is a configuration diagram of a selection control circuit according to a second embodiment. (A) is an example of a RES / READY generation circuit. (B) An example of a READY / EU generation circuit.
FIG. 14 is a configuration diagram of a selection control circuit (feed destination selection signal generation circuit) according to a second embodiment.
FIG. 15 is a configuration example of an information processing apparatus including a RISC instruction set.
FIG. 16 is a configuration example of an information processing apparatus including a CISC instruction set.
[Explanation of symbols]
1 execution unit
3 Required instruction detection means
4 Instruction storage means
5 Effective command detection means
6, 9 feeding control means
7 Processing status table
8 Referenceable instruction detection means
10 First feed control means
11 Registration means
12 Second feed control means
13 Instruction detection means
14 Third feed control means
41 Control unit
41-1 to 41-n instruction registers
42, 42a, 42b Storage register group
43-1 to 43-m execution unit
51,111 decoder
52, 112 selection control circuit
53, 114 selection circuit
113 Update pending status table

Claims (4)

In an information processing apparatus including a plurality of execution units that can be operated simultaneously, as a configuration that controls feeding of a plurality of instructions decoded at the same time to the plurality of execution units,
Required instruction detecting means for detecting an instruction requiring the execution unit from among a plurality of instructions being simultaneously decoded,
Command storage means for temporarily storing decoded commands;
Valid instruction detecting means for detecting a valid instruction in the instruction storing means;
In accordance with the magnitude relationship between the number of valid instructions detected by the valid instruction detection means and the number of vacant execution units, a part of the decoding instruction requiring the execution unit detected by the necessary instruction detection means is vacated. Feed control means for feeding to the instruction storage means and feeding the decoding instruction which could not be fed because the execution unit was not allocated to the execution unit. Information processing device. In an information processing apparatus including a plurality of execution units that can be operated simultaneously, as a configuration that controls feeding of a plurality of instructions decoded at the same time to the plurality of execution units,
Required instruction detecting means for detecting an instruction requiring the execution unit from among a plurality of instructions being simultaneously decoded,
Command storage means for temporarily storing decoded commands;
A processing status table in which the processing status of each of the plurality of instructions to be decoded is set;
Referenceable instruction detection means for detecting an instruction whose operand can be referred to among a plurality of instructions being simultaneously decoded with reference to the processing status table,
Among the decoding instructions that require the execution unit detected by the necessary instruction detection means, the instruction detected by the referenceable instruction detection means is supplied to the vacant execution unit and the usable instruction is supplied to the empty execution unit. An information processing apparatus comprising: a feed control unit that feeds an instruction that cannot be supplied to an execution unit because the instruction is not possible to the instruction storage unit and stores the instruction. In an information processing apparatus including a plurality of execution units that can be operated simultaneously, as a configuration that controls feeding of a plurality of instructions decoded at the same time to the plurality of execution units,
Required instruction detecting means for detecting an instruction requiring the execution unit from among a plurality of instructions being simultaneously decoded,
A processing status table in which the processing status of each of the plurality of instructions to be decoded is set;
Referenceable instruction detection means for detecting an instruction whose operand can be referred to among a plurality of instructions being simultaneously decoded with reference to the processing status table,
Command storage means for temporarily storing decoded commands;
Among the decoding instructions that require the execution unit detected by the necessary instruction detection means, the instruction detected by the referenceable instruction detection means is supplied to the vacant execution unit and the instruction which can be referred to by the operand is detected. First feeding control means for feeding means for feeding and storing instructions which cannot be fed to the execution unit because they are not possible to the command storage means;
Registration means for registering in the instruction storage means whether or not the operand of the decoded instruction can be referred to when the first feed control means feeds the decoded instruction to the instruction storage means;
Second feed control means for feeding, to the execution unit, an instruction whose operand can be referred to among the decoded instructions in the instruction storage means;
Instruction detection means for detecting a valid and operand-referenceable instruction among the decoded instructions in the instruction storage means;
According to the magnitude relation between the number of instructions detected by the instruction detection means and the number of free execution units among the decoded instructions in the instruction storage means, all of the valid and referable instructions in the instruction storage means are executed by the execution unit. And a third feed control unit that feeds a part of the valid and referable instruction to the empty execution unit. The information processing apparatus according to any one of claims 1 to 3,
The plurality of execution units include a plurality of types of execution unit groups that perform different processes,
The information processing apparatus according to claim 1, wherein said required instruction detecting means detects an instruction requiring an execution unit for each execution unit group.

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