JP3567599B2 - Diagnosis method for semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a structure of a MOS type semiconductor device, and more particularly to a MOS type semiconductor device capable of preventing deterioration due to injection of charges generated during dry etching.
[0002]
[Prior art]
In recent years, high integration of semiconductor integrated circuits has been greatly advanced, and also in MOS type semiconductor devices, gate insulating films have been made thinner with the miniaturization of transistor elements. As a result, specifically, a thin gate insulating film of 6 to 8 nm is being used in the 0.25 μm rule.
[0003]
When manufacturing a semiconductor device having a thin gate insulating film as described above, damage to the gate insulating film occurring during the manufacturing process becomes a problem, and in particular, in a dry etching process, electric charges injected into the wiring pattern are Breakdown and deterioration of the gate insulating film and deterioration of transistor characteristics (threshold voltage fluctuation and saturation current value decrease) caused by flowing in the gate insulating film become serious problems with miniaturization. On the other hand, as the density of wiring patterns increases with miniaturization of elements, current flowing to the gate insulating film in the dry etching step increases.
[0004]
As a conventional technique for solving the above-mentioned problems, there is a technique of optimizing a process condition of a dry etching process and minimizing a charge amount injected into a wiring pattern.
[0005]
[Problems to be solved by the invention]
However, even when the dry etching process conditions are optimized and the total charge incident on the entire wafer is controlled and optimized, the characteristics vary among the transistors that constitute the actual integrated circuit. There is.
[0006]
In the dry etching process, the amount of charge injected into the gate insulating film via the wiring pattern also depends on the wiring pattern and the wiring pattern adjacent to the wiring (a distance of 1 μm or less). However, the above-mentioned problems are greatly dependent on the layout of another wiring pattern that is not connected to the wiring. On the other hand, in an actual integrated circuit, the layout of a wiring pattern connected to a gate electrode of a transistor and a wiring pattern existing adjacent thereto are completely different depending on each transistor. Therefore, in each transistor in the integrated circuit, characteristics such as a threshold voltage and a saturation current value vary due to damage in the dry etching process, and a circuit operation failure occurs.
[0007]
FIG. 7 shows an example of such transistor deterioration characteristics due to damage during dry etching depending on the layout of adjacent wiring patterns.
[0008]
FIG. 7 shows a case where a floating wiring pattern (existence rate: 50%), which is not connected to the wiring pattern and the semiconductor substrate, is adjacent to a wiring pattern connected to the gate electrode of the MOS transistor. This shows how the characteristics of the MOS transistor deteriorate due to the etching process. Specifically, the layout is shown in FIG. 7A, and FIG. 7B shows how the MOS transistor deteriorates when the width of the floating wiring region is changed. As is clear from FIG. 7, as the width of the adjacent floating wiring region increases, transistor characteristics such as threshold voltage and saturation current value deteriorate. Note that the above-mentioned abundance is the ratio of the area of the floating wiring pattern to the area of the region where the floating wiring pattern is present. In the example shown in FIG. Although the case of% is taken up, if the abundance is 40% or more, the above-described problem occurs.
[0009]
As described above, the problem to be solved by the present invention has been described. At present, the threshold shift is suppressed to some extent by the heat treatment performed after the dry etching. However, as described above, with the increase in the width of the floating wiring region in the future, there is a high possibility that the characteristics cannot be sufficiently recovered by the heat treatment after the dry etching.
[0010]
Next, the mechanism by which the MOS transistor deteriorates in the dry etching process as described above will be described with reference to FIG.
[0011]
FIG. 8 is a schematic view showing a case where a wiring connected to a gate electrode of a MOS transistor is formed by dry etching. FIG. 8A shows a floating wiring adjacent to a wiring connected to the gate electrode. FIG. 8B shows the case where there is a floating wiring adjacent to the wiring connected to the gate electrode.
[0012]
In a normal dry etching process, it is known that a resist mask is negatively charged by electrons supplied from a plasma ion source. Therefore, in a dense wiring region, electrons from a plasma ion source to a wiring pattern from a plasma ion source are known. And the balance between the positive and negative charges in the wiring pattern is lost (specifically, the positive charges are excessively supplied). Therefore, as a result, the effective amount of charge injected into the wiring pattern increases. In particular, in a resist mask for patterning a floating wiring, a path through which charged electrons flow in the resist mask does not exist in the semiconductor device, and thus the charge amount is larger than that in a case where a path exists. Therefore, the disturbance of the charge balance due to the presence of the floating wiring is large, and the influence extends to the adjacent wiring. When such floating wiring patterns are densely arranged, the influence on adjacent wiring patterns becomes very large.
[0013]
In fact, such a layout in which floating wiring patterns are densely present often exists in an integrated circuit, and the influence on the wiring pattern connected to the gate electrode adjacent thereto is affected by a process in consideration of characteristic variations, This is very important in device design. For example, in the example shown in FIG. 7, in order to suppress the threshold voltage fluctuation of the transistor due to the damage in the dry etching process to about 20 mV or less, it is necessary to place the transistor adjacent to the wiring pattern connected to the gate electrode of the transistor. It is necessary to design the layout so that a wiring region having a density of 50%, which is constituted only by floating wirings having a length of 100 μm and a width of more than 5 μm, is not provided.
[0014]
Therefore, the present invention has been made in view of the above problems, and when a plurality of dense floating wiring patterns exist, even when a wiring connected to the gate electrode of the transistor is provided adjacent to the floating wiring pattern, the present invention An object of the present invention is to provide a structure of a semiconductor device capable of preventing an increase in characteristic variation due to deterioration and a method of diagnosing a wiring layout thereof.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, a wiring pattern electrically connected to a semiconductor substrate is provided adjacent to a plurality of dense floating wiring patterns, and the floating wiring pattern exists adjacent to the floating wiring pattern. It is characterized by reducing the amount of charge-up of electric charges to a resist mask of a wiring pattern connected to a gate electrode, and specifically, a semiconductor substrate such as connecting a part of a floating wiring pattern to a diode. It is configured to be electrically connected to.
[0016]
In addition, as a wiring pattern layout method for reducing variation in transistor characteristics regardless of the density of floating wirings around the gate electrode wiring, the wiring layout of each wiring layer of the semiconductor integrated circuit is changed by changing the transistor characteristics due to the density of floating wirings. The diagnosis is made from the viewpoint of characteristic variation.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
(Embodiment 1)
Hereinafter, the present invention will be described in detail with reference to embodiments. First, a semiconductor device according to Embodiment 1 of the present invention will be described with reference to the drawings.
[0018]
FIG. 1 is a structural view of a semiconductor device according to the first embodiment of the present invention. FIG. 1A is a plan view of the semiconductor device according to the present embodiment, and FIG. FIG. 3 is a cross-sectional view of a MOS transistor and a diode corresponding to AA ′ in FIG.
[0019]
In FIG. 1, 101 is an element isolation region formed on a P-type semiconductor substrate 100, 102 is a gate oxide film constituting an N-type MOS transistor 103, 104 is a gate electrode, and 105 is an interlayer insulating film formed on a semiconductor element. The film and the metal wiring 106 are connected via a contact plug 107 to the gate electrode 104 of the N-type MOS transistor. Reference numeral 108 denotes an N-type semiconductor region formed in the P-type semiconductor substrate 100, and forms a diode 109. The metal wiring 110 is connected to the diode 109 via a contact plug 111. Reference numeral 112 denotes a densely arranged metal wiring pattern, which is electrically insulated from any semiconductor device or semiconductor substrate in a wiring layer after the step shown in FIG. In the present embodiment, as an example of a densely arranged metal wiring pattern, a plurality (two in FIG. 1) of metal wiring patterns laid out in parallel is shown. The metal wiring 106 connected to the gate electrode and the metal wiring 110 connected to the diode are adjacent to the dense metal wiring region and exist at positions sandwiching the dense metal wiring region.
[0020]
Next, a method for manufacturing the semiconductor device according to the present embodiment shown in FIG. 1 will be described with reference to the process sectional views shown in FIG.
[0021]
First, as shown in FIG. 2A, after forming a MOS transistor 103, a diode 109, an interlayer insulating film 105, and contact plugs 107 and 111 by a known method, a metal film 113 is deposited on the entire surface and a photoresist 114 is formed. Is used for patterning. Next, as shown in FIG. 2B, the metal film 113 is etched by a dry etching process using the photoresist 114 as a mask. After the completion of the dry etching, the photoresist 114 is removed to complete the metal wiring patterning step (FIG. 2C).
[0022]
According to this embodiment, transistor characteristic deterioration due to the presence of dense floating metal wiring adjacent to the metal wiring connected to the gate electrode is greatly reduced by the presence of the metal wiring connected to the diode. be able to.
[0023]
FIG. 3 shows adjacent floating metal wirings (existence rate = 50%) densely laid out with a line / space of 0.6 μm / 0.6 μm over a range of 100 μm of the metal wiring connected to the gate electrode. 4 shows transistor deterioration characteristics with respect to the number of floating wirings. When the metal wiring connected to the diode is not provided, the threshold voltage of the transistor is 20 mV or more because four floating wirings are adjacent to each other (floating wirings having an abundance ratio of 50% exist over a range of 6 μm). Fluctuating. On the other hand, when the metal wiring connected to the diode is installed adjacent to the floating metal wiring, about 50 floating wirings are adjacent to each other (the floating wiring having an abundance ratio of 50% exists over a range of a distance of 60 μm). The fluctuation of the threshold voltage is suppressed to 20 mV or less until now, and the resistance to the denseness of the floating metal wiring is improved 10 times.
[0024]
A mechanism capable of reducing the threshold shift amount of the MOS transistor as shown in FIG. 3 will be described with reference to FIG.
[0025]
FIG. 4B shows a state in which a floating wiring pattern adjacent to a wiring pattern connected to a gate electrode exists as in the related art, and FIG. 4A shows a wiring pattern shown in FIG. On the other hand, a floating wiring connected to a diode is further provided adjacent to the floating wiring pattern. As shown in FIG. 4A, by providing the metal wiring connected to the diode, charge-up of the electric charge to the resist mask on the floating wiring and the metal wiring connected to the gate electrode is largely suppressed. It is thought that it is. Specifically, the mechanism is as follows. Even if the resist formed on the floating wiring pattern connected to the diode is charged up, the charge flows to the substrate through the diode, so that the resist does not charge up forever. . Therefore, the charge generated during the dry etching is preferentially supplied to the resist on the wiring pattern connected to the diode, and is not supplied to the resist on the original floating wiring pattern, and the effective current is not supplied. The increase can be fundamentally prevented.
[0026]
In the present embodiment, the floating wiring patterns are shown laid out in parallel, but the same effect can be obtained for floating wiring patterns of any layout having the same abundance.
[0027]
Although metal wiring connected to a diode is used as wiring for reducing the charge-up charge on the resist, the same effect can be obtained when metal wiring in resistive contact with the semiconductor substrate is used. Can be
[0028]
Further, in the present embodiment, a dummy wiring pattern which is not necessary for the operation of the integrated circuit is provided in order to form electrical conduction with the semiconductor substrate. The same effect can be obtained by effectively arranging the metal wiring pattern connected to the drain, the substrate terminal and the like.
[0029]
(Embodiment 2)
FIG. 5 is a diagram showing the structure of a semiconductor device according to the second embodiment of the present invention. In order to explain the advantages of the semiconductor device according to the second embodiment, the structure is compared with that of the conventional semiconductor device shown in FIG. Will be described.
[0030]
First, in FIGS. 9A and 9B showing a conventional wiring layout, a metal wiring 106 connected to a gate electrode of a transistor 103 exists close to a region 112 in which floating wirings are densely laid out. . The metal wiring 106 connected to the gate electrode of the MOS transistor 103 in FIGS. 9C and 9D exists in a sparse region where other wiring patterns are not laid out. In the dry etching process of the wiring layout as shown in FIGS. 9A and 9B, charge-up occurs in the mask resist on the floating wiring around the metal wiring connected to the gate electrode, and as a result, The deterioration of the transistor is large. On the other hand, in the wiring layouts as shown in FIGS. 9C and 9D, since no other wiring is laid out around the metal wiring connected to the gate electrode, deterioration of the transistor characteristics in the dry etching process is small. Therefore, in the dry etching process, variations in transistor characteristics in the integrated circuit increase.
[0031]
On the other hand, the metal wiring 106 connected to the gate electrode of the MOS transistor 103 in FIGS. 5A and 5B showing the semiconductor device of the present invention exists close to the region 112 where floating wirings are densely laid out. Further, a metal wiring 110 connected to the diode 109 is provided adjacent to a region where the floating wiring is densely laid out. In addition, adjacent to the wiring 107 connected to the gate electrode of the MOS transistor 103 in FIGS. 5C and 5D, the floating wiring 112 (the floating wiring in FIG. 5A and FIG. Are sparsely present) and a metal wiring 110 connected to the diode. The floating wiring 112 and the wiring 110 are dummy wiring patterns that are not necessary for the operation of the integrated circuit.
[0032]
By adopting the configuration shown in FIG. 5, the threshold value shift can be suppressed to, for example, about 10 mV in the region where the floating wirings are densely laid out, while the threshold shift can be suppressed in the region where the floating wirings are sparse. The threshold value shift can be set to, for example, about 10 mv, and although the threshold value shifts, the shift amount can be kept almost constant. As a result, a highly reliable MOS transistor can be formed. Can be.
[0033]
In other words, when dense floating wiring patterns exist over a wide area, wiring patterns connected to the semiconductor substrate at appropriate intervals are replaced with sparse wiring patterns around which no wiring patterns exist. By sequentially arranging the dummy floating wiring and the wiring pattern connected to the semiconductor substrate, it is possible to suppress the occurrence of variation in transistor characteristics depending on the wiring layout in the dry etching step.
[0034]
(Example 3)
FIG. 6 is a flowchart showing a method of diagnosing a wiring layout according to the third embodiment of the present invention. Hereinafter, the present embodiment will be described along this flowchart.
[0035]
In step 200 in the figure, the contact connecting the (N-1) th layer and the Nth layer is changed according to the connection mode with the semiconductor substrate in the wiring layer below the (N) th layer. And (3) contacts that are not connected to any of the resistive or rectifying connections with the semiconductor substrate. In step 201, independent wiring patterns are extracted from the wiring layout data in the Nth wiring layer, and K wiring patterns independent of each other are obtained. In step 202, based on the results of steps 200 and 201, (1) the wiring pattern A1 connected only to the gate electrode, depending on the form of connection between the N-th wiring pattern and the semiconductor substrate in the wiring layers below the N-th layer. , A2,..., Ak (providing total gate insulating film area information S1, S2,. , (3) a wiring pattern C not connected to any of them. Subsequently, in step 203, the wiring pattern area B is expanded and inverted by, for example, 50 μm on a computer to obtain the area B. In step 204, a region having a density of 40% or more in the wiring pattern region is extracted to obtain a region C. Next, in step 205, a logical product of the area B and the area C is obtained to obtain an area D. In step 206, the AND of the wiring patterns A1, A2,..., Ak connected to only the k independent gate electrodes obtained in step 202 with the region D is calculated, and the regions E1, E2,. , Ek. Finally, in step 207, the lengths of the regions E1, E2,..., Ek are calculated, and if any of the k wirings has, for example, Sn (n = 1 to k) × 15 / H μm or more. In this case, "NG" is output, and if not, "OK" is output (here, the height of the N-th layer metal wiring is H [μm]).
[0036]
In the present embodiment, in step 203, a region B in which charge-up to a resist mask in a dry etching step is reduced due to the presence of a wiring pattern electrically connected to a semiconductor substrate, and in step 204, A region C where floating wirings are densely obtained is obtained. Therefore, by taking the logical product of these in step 205, it is possible to obtain a region D in which the resist mask is significantly charged up. In a wiring pattern connected only to the gate electrode of the transistor, if the length of the region included in the region D exceeds, for example, Sn (n = 1 to k) × 50 / H μm, Since the characteristic deterioration exceeds the specified value, the existence thereof can be known in step 206. Therefore, according to this embodiment, it can be diagnosed by computer processing of the wiring layout whether or not the increase in transistor characteristic deterioration in the dry etching step exceeds a specified value.
[0037]
【The invention's effect】
As described above, according to the present invention, a wiring pattern electrically connected to a semiconductor substrate is provided adjacent to a plurality of dense floating wiring patterns, and the floating wiring pattern and a gate electrode existing adjacent thereto are provided. A structure of a semiconductor device for reducing an effective charge amount injected into a gate insulating film of the transistor in a dry etching step by reducing a charge-up amount of charges to a resist mask of a connected wiring pattern; and A wiring pattern layout method for reducing transistor characteristic variations regardless of the density of floating wirings around the gate electrode wiring, and a wiring layout of each wiring layer of a semiconductor integrated circuit, in which transistor characteristic variations and characteristic variations due to floating wiring density Layout diagnosis can be realized from the viewpoint of the above.
[Brief description of the drawings]
FIG. 1 is a structural view of a semiconductor device according to an embodiment of the present invention; FIG. 2 is a cross-sectional view of a metal wiring forming step of the semiconductor device according to an embodiment of the present invention; FIG. FIG. 4 is a schematic diagram showing a charge-up amount to a resist in an over-etching step. FIG. 5 is a structural diagram of a semiconductor device according to an embodiment of the present invention. FIG. 6 is a wiring diagram according to an embodiment of the present invention. FIG. 7 is a diagram showing a process characteristic of a structure diagnosis. FIG. 7 is a diagram showing deterioration of transistor characteristics induced by a floating wiring existing around a gate electrode. FIG. 8 is a schematic diagram showing an increase in resist charge-up due to an adjacent floating wiring. Of semiconductor device
Reference Signs List 100 P-type semiconductor substrate 101 Element isolation region 102 Gate oxide film 103 N-type MOS transistor 104 Gate electrode 105 Interlayer insulating film 106 Metal wiring connected to gate electrode 107 Contact plug 108 N-type semiconductor region 109 Diode 110 Connected to diode Metal wiring 111 contact plug 112 metal wiring 113 metal thin film 114 photoresist

Claims (1)

A first wiring pattern connected to a gate electrode of a MOS transistor is formed by extracting independent wiring patterns from the wiring layout data and connecting the independent wiring patterns to a semiconductor substrate according to a connection mode with the semiconductor substrate. Or a step of classifying the wiring pattern into a second wiring pattern having a rectifying connection, or a third wiring pattern which does not apply to any of the first wiring pattern and the second wiring pattern, and a region of the second wiring pattern. Is extended by a specific distance and inverted to obtain a first region, and a region having an area density of 40% or more is extracted from among the regions of the third wiring pattern to obtain a second region. Calculating a logical product of the first area and the second area to obtain a third area; and calculating a logical value of the first wiring pattern and the third area. Look, diagnostic method of a semiconductor device having a step of comparing a preset reference value the value.

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